1dd8c7b78SManivannan Sadhasivam// SPDX-License-Identifier: GPL-2.0 2dd8c7b78SManivannan Sadhasivam/* 3dd8c7b78SManivannan Sadhasivam * dts file for Hisilicon Hi3670 SoC 4dd8c7b78SManivannan Sadhasivam * 5dd8c7b78SManivannan Sadhasivam * Copyright (C) 2016, Hisilicon Ltd. 6dd8c7b78SManivannan Sadhasivam * Copyright (C) 2018, Linaro Ltd. 7dd8c7b78SManivannan Sadhasivam */ 8dd8c7b78SManivannan Sadhasivam 9dd8c7b78SManivannan Sadhasivam#include <dt-bindings/interrupt-controller/arm-gic.h> 10dd8c7b78SManivannan Sadhasivam 11dd8c7b78SManivannan Sadhasivam/ { 12dd8c7b78SManivannan Sadhasivam compatible = "hisilicon,hi3670"; 13dd8c7b78SManivannan Sadhasivam interrupt-parent = <&gic>; 14dd8c7b78SManivannan Sadhasivam #address-cells = <2>; 15dd8c7b78SManivannan Sadhasivam #size-cells = <2>; 16dd8c7b78SManivannan Sadhasivam 17dd8c7b78SManivannan Sadhasivam psci { 18dd8c7b78SManivannan Sadhasivam compatible = "arm,psci-0.2"; 19dd8c7b78SManivannan Sadhasivam method = "smc"; 20dd8c7b78SManivannan Sadhasivam }; 21dd8c7b78SManivannan Sadhasivam 22dd8c7b78SManivannan Sadhasivam cpus { 23dd8c7b78SManivannan Sadhasivam #address-cells = <2>; 24dd8c7b78SManivannan Sadhasivam #size-cells = <0>; 25dd8c7b78SManivannan Sadhasivam 26dd8c7b78SManivannan Sadhasivam cpu-map { 27dd8c7b78SManivannan Sadhasivam cluster0 { 28dd8c7b78SManivannan Sadhasivam core0 { 29dd8c7b78SManivannan Sadhasivam cpu = <&cpu0>; 30dd8c7b78SManivannan Sadhasivam }; 31dd8c7b78SManivannan Sadhasivam core1 { 32dd8c7b78SManivannan Sadhasivam cpu = <&cpu1>; 33dd8c7b78SManivannan Sadhasivam }; 34dd8c7b78SManivannan Sadhasivam core2 { 35dd8c7b78SManivannan Sadhasivam cpu = <&cpu2>; 36dd8c7b78SManivannan Sadhasivam }; 37dd8c7b78SManivannan Sadhasivam core3 { 38dd8c7b78SManivannan Sadhasivam cpu = <&cpu3>; 39dd8c7b78SManivannan Sadhasivam }; 40dd8c7b78SManivannan Sadhasivam }; 41dd8c7b78SManivannan Sadhasivam cluster1 { 42dd8c7b78SManivannan Sadhasivam core0 { 43dd8c7b78SManivannan Sadhasivam cpu = <&cpu4>; 44dd8c7b78SManivannan Sadhasivam }; 45dd8c7b78SManivannan Sadhasivam core1 { 46dd8c7b78SManivannan Sadhasivam cpu = <&cpu5>; 47dd8c7b78SManivannan Sadhasivam }; 48dd8c7b78SManivannan Sadhasivam core2 { 49dd8c7b78SManivannan Sadhasivam cpu = <&cpu6>; 50dd8c7b78SManivannan Sadhasivam }; 51dd8c7b78SManivannan Sadhasivam core3 { 52dd8c7b78SManivannan Sadhasivam cpu = <&cpu7>; 53dd8c7b78SManivannan Sadhasivam }; 54dd8c7b78SManivannan Sadhasivam }; 55dd8c7b78SManivannan Sadhasivam }; 56dd8c7b78SManivannan Sadhasivam 57dd8c7b78SManivannan Sadhasivam cpu0: cpu@0 { 58dd8c7b78SManivannan Sadhasivam compatible = "arm,cortex-a53", "arm,armv8"; 59dd8c7b78SManivannan Sadhasivam device_type = "cpu"; 60dd8c7b78SManivannan Sadhasivam reg = <0x0 0x0>; 61dd8c7b78SManivannan Sadhasivam enable-method = "psci"; 62dd8c7b78SManivannan Sadhasivam }; 63dd8c7b78SManivannan Sadhasivam 64dd8c7b78SManivannan Sadhasivam cpu1: cpu@1 { 65dd8c7b78SManivannan Sadhasivam compatible = "arm,cortex-a53", "arm,armv8"; 66dd8c7b78SManivannan Sadhasivam device_type = "cpu"; 67dd8c7b78SManivannan Sadhasivam reg = <0x0 0x1>; 68dd8c7b78SManivannan Sadhasivam enable-method = "psci"; 69dd8c7b78SManivannan Sadhasivam }; 70dd8c7b78SManivannan Sadhasivam 71dd8c7b78SManivannan Sadhasivam cpu2: cpu@2 { 72dd8c7b78SManivannan Sadhasivam compatible = "arm,cortex-a53", "arm,armv8"; 73dd8c7b78SManivannan Sadhasivam device_type = "cpu"; 74dd8c7b78SManivannan Sadhasivam reg = <0x0 0x2>; 75dd8c7b78SManivannan Sadhasivam enable-method = "psci"; 76dd8c7b78SManivannan Sadhasivam }; 77dd8c7b78SManivannan Sadhasivam 78dd8c7b78SManivannan Sadhasivam cpu3: cpu@3 { 79dd8c7b78SManivannan Sadhasivam compatible = "arm,cortex-a53", "arm,armv8"; 80dd8c7b78SManivannan Sadhasivam device_type = "cpu"; 81dd8c7b78SManivannan Sadhasivam reg = <0x0 0x3>; 82dd8c7b78SManivannan Sadhasivam enable-method = "psci"; 83dd8c7b78SManivannan Sadhasivam }; 84dd8c7b78SManivannan Sadhasivam 85dd8c7b78SManivannan Sadhasivam cpu4: cpu@100 { 86dd8c7b78SManivannan Sadhasivam compatible = "arm,cortex-a73", "arm,armv8"; 87dd8c7b78SManivannan Sadhasivam device_type = "cpu"; 88dd8c7b78SManivannan Sadhasivam reg = <0x0 0x100>; 89dd8c7b78SManivannan Sadhasivam enable-method = "psci"; 90dd8c7b78SManivannan Sadhasivam }; 91dd8c7b78SManivannan Sadhasivam 92dd8c7b78SManivannan Sadhasivam cpu5: cpu@101 { 93dd8c7b78SManivannan Sadhasivam compatible = "arm,cortex-a73", "arm,armv8"; 94dd8c7b78SManivannan Sadhasivam device_type = "cpu"; 95dd8c7b78SManivannan Sadhasivam reg = <0x0 0x101>; 96dd8c7b78SManivannan Sadhasivam enable-method = "psci"; 97dd8c7b78SManivannan Sadhasivam }; 98dd8c7b78SManivannan Sadhasivam 99dd8c7b78SManivannan Sadhasivam cpu6: cpu@102 { 100dd8c7b78SManivannan Sadhasivam compatible = "arm,cortex-a73", "arm,armv8"; 101dd8c7b78SManivannan Sadhasivam device_type = "cpu"; 102dd8c7b78SManivannan Sadhasivam reg = <0x0 0x102>; 103dd8c7b78SManivannan Sadhasivam enable-method = "psci"; 104dd8c7b78SManivannan Sadhasivam }; 105dd8c7b78SManivannan Sadhasivam 106dd8c7b78SManivannan Sadhasivam cpu7: cpu@103 { 107dd8c7b78SManivannan Sadhasivam compatible = "arm,cortex-a73", "arm,armv8"; 108dd8c7b78SManivannan Sadhasivam device_type = "cpu"; 109dd8c7b78SManivannan Sadhasivam reg = <0x0 0x103>; 110dd8c7b78SManivannan Sadhasivam enable-method = "psci"; 111dd8c7b78SManivannan Sadhasivam }; 112dd8c7b78SManivannan Sadhasivam }; 113dd8c7b78SManivannan Sadhasivam 114dd8c7b78SManivannan Sadhasivam gic: interrupt-controller@e82b0000 { 115dd8c7b78SManivannan Sadhasivam compatible = "arm,gic-400"; 116dd8c7b78SManivannan Sadhasivam reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 117dd8c7b78SManivannan Sadhasivam <0x0 0xe82b2000 0 0x2000>, /* GICC */ 118dd8c7b78SManivannan Sadhasivam <0x0 0xe82b4000 0 0x2000>, /* GICH */ 119dd8c7b78SManivannan Sadhasivam <0x0 0xe82b6000 0 0x2000>; /* GICV */ 120dd8c7b78SManivannan Sadhasivam #interrupt-cells = <3>; 121dd8c7b78SManivannan Sadhasivam #address-cells = <0>; 122dd8c7b78SManivannan Sadhasivam interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 123dd8c7b78SManivannan Sadhasivam IRQ_TYPE_LEVEL_HIGH)>; 124dd8c7b78SManivannan Sadhasivam interrupt-controller; 125dd8c7b78SManivannan Sadhasivam }; 126dd8c7b78SManivannan Sadhasivam 127dd8c7b78SManivannan Sadhasivam timer { 128dd8c7b78SManivannan Sadhasivam compatible = "arm,armv8-timer"; 129dd8c7b78SManivannan Sadhasivam interrupt-parent = <&gic>; 130dd8c7b78SManivannan Sadhasivam interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 131dd8c7b78SManivannan Sadhasivam IRQ_TYPE_LEVEL_LOW)>, 132dd8c7b78SManivannan Sadhasivam <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 133dd8c7b78SManivannan Sadhasivam IRQ_TYPE_LEVEL_LOW)>, 134dd8c7b78SManivannan Sadhasivam <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 135dd8c7b78SManivannan Sadhasivam IRQ_TYPE_LEVEL_LOW)>, 136dd8c7b78SManivannan Sadhasivam <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 137dd8c7b78SManivannan Sadhasivam IRQ_TYPE_LEVEL_LOW)>; 138dd8c7b78SManivannan Sadhasivam clock-frequency = <1920000>; 139dd8c7b78SManivannan Sadhasivam }; 140dd8c7b78SManivannan Sadhasivam 141dd8c7b78SManivannan Sadhasivam soc { 142dd8c7b78SManivannan Sadhasivam compatible = "simple-bus"; 143dd8c7b78SManivannan Sadhasivam #address-cells = <2>; 144dd8c7b78SManivannan Sadhasivam #size-cells = <2>; 145dd8c7b78SManivannan Sadhasivam ranges; 146dd8c7b78SManivannan Sadhasivam 147dd8c7b78SManivannan Sadhasivam uart6_clk: clk_19_2M { 148dd8c7b78SManivannan Sadhasivam compatible = "fixed-clock"; 149dd8c7b78SManivannan Sadhasivam #clock-cells = <0>; 150dd8c7b78SManivannan Sadhasivam clock-frequency = <19200000>; 151dd8c7b78SManivannan Sadhasivam }; 152dd8c7b78SManivannan Sadhasivam 153dd8c7b78SManivannan Sadhasivam uart6: serial@fff32000 { 154dd8c7b78SManivannan Sadhasivam compatible = "arm,pl011", "arm,primecell"; 155dd8c7b78SManivannan Sadhasivam reg = <0x0 0xfff32000 0x0 0x1000>; 156dd8c7b78SManivannan Sadhasivam interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 157dd8c7b78SManivannan Sadhasivam clocks = <&uart6_clk &uart6_clk>; 158dd8c7b78SManivannan Sadhasivam clock-names = "uartclk", "apb_pclk"; 159dd8c7b78SManivannan Sadhasivam status = "disabled"; 160dd8c7b78SManivannan Sadhasivam }; 161dd8c7b78SManivannan Sadhasivam }; 162dd8c7b78SManivannan Sadhasivam}; 163