135ca8168SChen Feng/* 235ca8168SChen Feng * dts file for Hisilicon Hi3660 SoC 335ca8168SChen Feng * 435ca8168SChen Feng * Copyright (C) 2016, Hisilicon Ltd. 535ca8168SChen Feng */ 635ca8168SChen Feng 735ca8168SChen Feng#include <dt-bindings/interrupt-controller/arm-gic.h> 8a4e36ae0SZhangfei Gao#include <dt-bindings/clock/hi3660-clock.h> 935ca8168SChen Feng 1035ca8168SChen Feng/ { 1135ca8168SChen Feng compatible = "hisilicon,hi3660"; 1235ca8168SChen Feng interrupt-parent = <&gic>; 1335ca8168SChen Feng #address-cells = <2>; 1435ca8168SChen Feng #size-cells = <2>; 1535ca8168SChen Feng 1635ca8168SChen Feng psci { 1735ca8168SChen Feng compatible = "arm,psci-0.2"; 1835ca8168SChen Feng method = "smc"; 1935ca8168SChen Feng }; 2035ca8168SChen Feng 2135ca8168SChen Feng cpus { 2235ca8168SChen Feng #address-cells = <2>; 2335ca8168SChen Feng #size-cells = <0>; 2435ca8168SChen Feng 2535ca8168SChen Feng cpu-map { 2635ca8168SChen Feng cluster0 { 2735ca8168SChen Feng core0 { 2835ca8168SChen Feng cpu = <&cpu0>; 2935ca8168SChen Feng }; 3035ca8168SChen Feng core1 { 3135ca8168SChen Feng cpu = <&cpu1>; 3235ca8168SChen Feng }; 3335ca8168SChen Feng core2 { 3435ca8168SChen Feng cpu = <&cpu2>; 3535ca8168SChen Feng }; 3635ca8168SChen Feng core3 { 3735ca8168SChen Feng cpu = <&cpu3>; 3835ca8168SChen Feng }; 3935ca8168SChen Feng }; 4035ca8168SChen Feng cluster1 { 4135ca8168SChen Feng core0 { 4235ca8168SChen Feng cpu = <&cpu4>; 4335ca8168SChen Feng }; 4435ca8168SChen Feng core1 { 4535ca8168SChen Feng cpu = <&cpu5>; 4635ca8168SChen Feng }; 4735ca8168SChen Feng core2 { 4835ca8168SChen Feng cpu = <&cpu6>; 4935ca8168SChen Feng }; 5035ca8168SChen Feng core3 { 5135ca8168SChen Feng cpu = <&cpu7>; 5235ca8168SChen Feng }; 5335ca8168SChen Feng }; 5435ca8168SChen Feng }; 5535ca8168SChen Feng 5635ca8168SChen Feng cpu0: cpu@0 { 5735ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 5835ca8168SChen Feng device_type = "cpu"; 5935ca8168SChen Feng reg = <0x0 0x0>; 6035ca8168SChen Feng enable-method = "psci"; 61a6d08344SLeo Yan next-level-cache = <&A53_L2>; 6230fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 6335ca8168SChen Feng }; 6435ca8168SChen Feng 6535ca8168SChen Feng cpu1: cpu@1 { 6635ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 6735ca8168SChen Feng device_type = "cpu"; 6835ca8168SChen Feng reg = <0x0 0x1>; 6935ca8168SChen Feng enable-method = "psci"; 70a6d08344SLeo Yan next-level-cache = <&A53_L2>; 7130fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 7235ca8168SChen Feng }; 7335ca8168SChen Feng 7435ca8168SChen Feng cpu2: cpu@2 { 7535ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 7635ca8168SChen Feng device_type = "cpu"; 7735ca8168SChen Feng reg = <0x0 0x2>; 7835ca8168SChen Feng enable-method = "psci"; 79a6d08344SLeo Yan next-level-cache = <&A53_L2>; 8030fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 8135ca8168SChen Feng }; 8235ca8168SChen Feng 8335ca8168SChen Feng cpu3: cpu@3 { 8435ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 8535ca8168SChen Feng device_type = "cpu"; 8635ca8168SChen Feng reg = <0x0 0x3>; 8735ca8168SChen Feng enable-method = "psci"; 88a6d08344SLeo Yan next-level-cache = <&A53_L2>; 8930fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 9035ca8168SChen Feng }; 9135ca8168SChen Feng 9235ca8168SChen Feng cpu4: cpu@100 { 9335ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 9435ca8168SChen Feng device_type = "cpu"; 9535ca8168SChen Feng reg = <0x0 0x100>; 9635ca8168SChen Feng enable-method = "psci"; 97a6d08344SLeo Yan next-level-cache = <&A73_L2>; 9830fec826SLeo Yan cpu-idle-states = < 9930fec826SLeo Yan &CPU_NAP 10030fec826SLeo Yan &CPU_SLEEP 10130fec826SLeo Yan &CLUSTER_SLEEP_1 10230fec826SLeo Yan >; 10335ca8168SChen Feng }; 10435ca8168SChen Feng 10535ca8168SChen Feng cpu5: cpu@101 { 10635ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 10735ca8168SChen Feng device_type = "cpu"; 10835ca8168SChen Feng reg = <0x0 0x101>; 10935ca8168SChen Feng enable-method = "psci"; 110a6d08344SLeo Yan next-level-cache = <&A73_L2>; 11130fec826SLeo Yan cpu-idle-states = < 11230fec826SLeo Yan &CPU_NAP 11330fec826SLeo Yan &CPU_SLEEP 11430fec826SLeo Yan &CLUSTER_SLEEP_1 11530fec826SLeo Yan >; 11635ca8168SChen Feng }; 11735ca8168SChen Feng 11835ca8168SChen Feng cpu6: cpu@102 { 11935ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 12035ca8168SChen Feng device_type = "cpu"; 12135ca8168SChen Feng reg = <0x0 0x102>; 12235ca8168SChen Feng enable-method = "psci"; 123a6d08344SLeo Yan next-level-cache = <&A73_L2>; 12430fec826SLeo Yan cpu-idle-states = < 12530fec826SLeo Yan &CPU_NAP 12630fec826SLeo Yan &CPU_SLEEP 12730fec826SLeo Yan &CLUSTER_SLEEP_1 12830fec826SLeo Yan >; 12935ca8168SChen Feng }; 13035ca8168SChen Feng 13135ca8168SChen Feng cpu7: cpu@103 { 13235ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 13335ca8168SChen Feng device_type = "cpu"; 13435ca8168SChen Feng reg = <0x0 0x103>; 13535ca8168SChen Feng enable-method = "psci"; 136a6d08344SLeo Yan next-level-cache = <&A73_L2>; 13730fec826SLeo Yan cpu-idle-states = < 13830fec826SLeo Yan &CPU_NAP 13930fec826SLeo Yan &CPU_SLEEP 14030fec826SLeo Yan &CLUSTER_SLEEP_1 14130fec826SLeo Yan >; 14230fec826SLeo Yan }; 14330fec826SLeo Yan 14430fec826SLeo Yan idle-states { 14530fec826SLeo Yan entry-method = "psci"; 14630fec826SLeo Yan 14730fec826SLeo Yan CPU_NAP: cpu-nap { 14830fec826SLeo Yan compatible = "arm,idle-state"; 14930fec826SLeo Yan arm,psci-suspend-param = <0x0000001>; 15030fec826SLeo Yan entry-latency-us = <7>; 15130fec826SLeo Yan exit-latency-us = <2>; 15230fec826SLeo Yan min-residency-us = <15>; 15330fec826SLeo Yan }; 15430fec826SLeo Yan 15530fec826SLeo Yan CPU_SLEEP: cpu-sleep { 15630fec826SLeo Yan compatible = "arm,idle-state"; 15730fec826SLeo Yan local-timer-stop; 15830fec826SLeo Yan arm,psci-suspend-param = <0x0010000>; 15930fec826SLeo Yan entry-latency-us = <40>; 16030fec826SLeo Yan exit-latency-us = <70>; 16130fec826SLeo Yan min-residency-us = <3000>; 16230fec826SLeo Yan }; 16330fec826SLeo Yan 16430fec826SLeo Yan CLUSTER_SLEEP_0: cluster-sleep-0 { 16530fec826SLeo Yan compatible = "arm,idle-state"; 16630fec826SLeo Yan local-timer-stop; 16730fec826SLeo Yan arm,psci-suspend-param = <0x1010000>; 16830fec826SLeo Yan entry-latency-us = <500>; 16930fec826SLeo Yan exit-latency-us = <5000>; 17030fec826SLeo Yan min-residency-us = <20000>; 17130fec826SLeo Yan }; 17230fec826SLeo Yan 17330fec826SLeo Yan CLUSTER_SLEEP_1: cluster-sleep-1 { 17430fec826SLeo Yan compatible = "arm,idle-state"; 17530fec826SLeo Yan local-timer-stop; 17630fec826SLeo Yan arm,psci-suspend-param = <0x1010000>; 17730fec826SLeo Yan entry-latency-us = <1000>; 17830fec826SLeo Yan exit-latency-us = <5000>; 17930fec826SLeo Yan min-residency-us = <20000>; 18030fec826SLeo Yan }; 18135ca8168SChen Feng }; 182a6d08344SLeo Yan 183a6d08344SLeo Yan A53_L2: l2-cache0 { 184a6d08344SLeo Yan compatible = "cache"; 185a6d08344SLeo Yan }; 186a6d08344SLeo Yan 187a6d08344SLeo Yan A73_L2: l2-cache1 { 188a6d08344SLeo Yan compatible = "cache"; 189a6d08344SLeo Yan }; 19035ca8168SChen Feng }; 19135ca8168SChen Feng 19235ca8168SChen Feng gic: interrupt-controller@e82b0000 { 19335ca8168SChen Feng compatible = "arm,gic-400"; 19435ca8168SChen Feng reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 19535ca8168SChen Feng <0x0 0xe82b2000 0 0x2000>, /* GICC */ 19635ca8168SChen Feng <0x0 0xe82b4000 0 0x2000>, /* GICH */ 19735ca8168SChen Feng <0x0 0xe82b6000 0 0x2000>; /* GICV */ 19835ca8168SChen Feng #address-cells = <0>; 19935ca8168SChen Feng #interrupt-cells = <3>; 20035ca8168SChen Feng interrupt-controller; 20135ca8168SChen Feng interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 20235ca8168SChen Feng IRQ_TYPE_LEVEL_HIGH)>; 20335ca8168SChen Feng }; 20435ca8168SChen Feng 205f8054fb8SYiPing Xu pmu { 206f8054fb8SYiPing Xu compatible = "arm,armv8-pmuv3"; 207f8054fb8SYiPing Xu interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 208f8054fb8SYiPing Xu <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 209f8054fb8SYiPing Xu <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 210f8054fb8SYiPing Xu <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 211f8054fb8SYiPing Xu <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 212f8054fb8SYiPing Xu <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 213f8054fb8SYiPing Xu <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 214f8054fb8SYiPing Xu <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 215f8054fb8SYiPing Xu interrupt-affinity = <&cpu0>, 216f8054fb8SYiPing Xu <&cpu1>, 217f8054fb8SYiPing Xu <&cpu2>, 218f8054fb8SYiPing Xu <&cpu3>, 219f8054fb8SYiPing Xu <&cpu4>, 220f8054fb8SYiPing Xu <&cpu5>, 221f8054fb8SYiPing Xu <&cpu6>, 222f8054fb8SYiPing Xu <&cpu7>; 223f8054fb8SYiPing Xu }; 224f8054fb8SYiPing Xu 22535ca8168SChen Feng timer { 22635ca8168SChen Feng compatible = "arm,armv8-timer"; 22735ca8168SChen Feng interrupt-parent = <&gic>; 22835ca8168SChen Feng interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 22935ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 23035ca8168SChen Feng <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 23135ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 23235ca8168SChen Feng <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 23335ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 23435ca8168SChen Feng <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 23535ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>; 23635ca8168SChen Feng }; 23735ca8168SChen Feng 23835ca8168SChen Feng soc { 23935ca8168SChen Feng compatible = "simple-bus"; 24035ca8168SChen Feng #address-cells = <2>; 24135ca8168SChen Feng #size-cells = <2>; 24235ca8168SChen Feng ranges; 24335ca8168SChen Feng 244a4e36ae0SZhangfei Gao crg_ctrl: crg_ctrl@fff35000 { 245a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-crgctrl", "syscon"; 246a4e36ae0SZhangfei Gao reg = <0x0 0xfff35000 0x0 0x1000>; 247a4e36ae0SZhangfei Gao #clock-cells = <1>; 24835ca8168SChen Feng }; 24935ca8168SChen Feng 250a4e36ae0SZhangfei Gao crg_rst: crg_rst_controller { 251a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 252a4e36ae0SZhangfei Gao #reset-cells = <2>; 253a4e36ae0SZhangfei Gao hisi,rst-syscon = <&crg_ctrl>; 254a4e36ae0SZhangfei Gao }; 255a4e36ae0SZhangfei Gao 256a4e36ae0SZhangfei Gao 257a4e36ae0SZhangfei Gao pctrl: pctrl@e8a09000 { 258a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pctrl", "syscon"; 259a4e36ae0SZhangfei Gao reg = <0x0 0xe8a09000 0x0 0x2000>; 260a4e36ae0SZhangfei Gao #clock-cells = <1>; 261a4e36ae0SZhangfei Gao }; 262a4e36ae0SZhangfei Gao 263a4e36ae0SZhangfei Gao pmuctrl: crg_ctrl@fff34000 { 264a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 265a4e36ae0SZhangfei Gao reg = <0x0 0xfff34000 0x0 0x1000>; 266a4e36ae0SZhangfei Gao #clock-cells = <1>; 267a4e36ae0SZhangfei Gao }; 268a4e36ae0SZhangfei Gao 269a4e36ae0SZhangfei Gao sctrl: sctrl@fff0a000 { 270a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-sctrl", "syscon"; 271a4e36ae0SZhangfei Gao reg = <0x0 0xfff0a000 0x0 0x1000>; 272a4e36ae0SZhangfei Gao #clock-cells = <1>; 273a4e36ae0SZhangfei Gao }; 274a4e36ae0SZhangfei Gao 275a4e36ae0SZhangfei Gao iomcu: iomcu@ffd7e000 { 276a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-iomcu", "syscon"; 277a4e36ae0SZhangfei Gao reg = <0x0 0xffd7e000 0x0 0x1000>; 278a4e36ae0SZhangfei Gao #clock-cells = <1>; 279a4e36ae0SZhangfei Gao 280a4e36ae0SZhangfei Gao }; 281a4e36ae0SZhangfei Gao 282a4e36ae0SZhangfei Gao iomcu_rst: reset { 283a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 284a4e36ae0SZhangfei Gao hisi,rst-syscon = <&iomcu>; 285a4e36ae0SZhangfei Gao #reset-cells = <2>; 286a4e36ae0SZhangfei Gao }; 287a4e36ae0SZhangfei Gao 28875196330SLeo Yan dual_timer0: timer@fff14000 { 28975196330SLeo Yan compatible = "arm,sp804", "arm,primecell"; 29075196330SLeo Yan reg = <0x0 0xfff14000 0x0 0x1000>; 29175196330SLeo Yan interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 29275196330SLeo Yan <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 29375196330SLeo Yan clocks = <&crg_ctrl HI3660_OSC32K>, 29475196330SLeo Yan <&crg_ctrl HI3660_OSC32K>, 29575196330SLeo Yan <&crg_ctrl HI3660_OSC32K>; 29675196330SLeo Yan clock-names = "timer1", "timer2", "apb_pclk"; 29775196330SLeo Yan }; 29875196330SLeo Yan 2995f8a3b77SZhangfei Gao i2c0: i2c@ffd71000 { 3005f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 3015f8a3b77SZhangfei Gao reg = <0x0 0xffd71000 0x0 0x1000>; 3025f8a3b77SZhangfei Gao interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 3035f8a3b77SZhangfei Gao #address-cells = <1>; 3045f8a3b77SZhangfei Gao #size-cells = <0>; 3055f8a3b77SZhangfei Gao clock-frequency = <400000>; 3065f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 3075f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 3>; 3085f8a3b77SZhangfei Gao pinctrl-names = "default"; 3095f8a3b77SZhangfei Gao pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 3105f8a3b77SZhangfei Gao status = "disabled"; 3115f8a3b77SZhangfei Gao }; 3125f8a3b77SZhangfei Gao 3135f8a3b77SZhangfei Gao i2c1: i2c@ffd72000 { 3145f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 3155f8a3b77SZhangfei Gao reg = <0x0 0xffd72000 0x0 0x1000>; 3165f8a3b77SZhangfei Gao interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 3175f8a3b77SZhangfei Gao #address-cells = <1>; 3185f8a3b77SZhangfei Gao #size-cells = <0>; 3195f8a3b77SZhangfei Gao clock-frequency = <400000>; 3205f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 3215f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 4>; 3225f8a3b77SZhangfei Gao pinctrl-names = "default"; 3235f8a3b77SZhangfei Gao pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 3245f8a3b77SZhangfei Gao status = "disabled"; 3255f8a3b77SZhangfei Gao }; 3265f8a3b77SZhangfei Gao 3275f8a3b77SZhangfei Gao i2c3: i2c@fdf0c000 { 3285f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 3295f8a3b77SZhangfei Gao reg = <0x0 0xfdf0c000 0x0 0x1000>; 3305f8a3b77SZhangfei Gao interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3315f8a3b77SZhangfei Gao #address-cells = <1>; 3325f8a3b77SZhangfei Gao #size-cells = <0>; 3335f8a3b77SZhangfei Gao clock-frequency = <400000>; 3345f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 3355f8a3b77SZhangfei Gao resets = <&crg_rst 0x78 7>; 3365f8a3b77SZhangfei Gao pinctrl-names = "default"; 3375f8a3b77SZhangfei Gao pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 3385f8a3b77SZhangfei Gao status = "disabled"; 3395f8a3b77SZhangfei Gao }; 3405f8a3b77SZhangfei Gao 3415f8a3b77SZhangfei Gao i2c7: i2c@fdf0b000 { 3425f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 3435f8a3b77SZhangfei Gao reg = <0x0 0xfdf0b000 0x0 0x1000>; 3445f8a3b77SZhangfei Gao interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 3455f8a3b77SZhangfei Gao #address-cells = <1>; 3465f8a3b77SZhangfei Gao #size-cells = <0>; 3475f8a3b77SZhangfei Gao clock-frequency = <400000>; 3485f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 3495f8a3b77SZhangfei Gao resets = <&crg_rst 0x60 14>; 3505f8a3b77SZhangfei Gao pinctrl-names = "default"; 3515f8a3b77SZhangfei Gao pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 3525f8a3b77SZhangfei Gao status = "disabled"; 3535f8a3b77SZhangfei Gao }; 3545f8a3b77SZhangfei Gao 355254b07b2SChen Feng uart0: serial@fdf02000 { 356254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 357254b07b2SChen Feng reg = <0x0 0xfdf02000 0x0 0x1000>; 358254b07b2SChen Feng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 359254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 360254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 361254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 362254b07b2SChen Feng pinctrl-names = "default"; 363254b07b2SChen Feng pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 364254b07b2SChen Feng status = "disabled"; 365254b07b2SChen Feng }; 366254b07b2SChen Feng 367254b07b2SChen Feng uart1: serial@fdf00000 { 368254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 369254b07b2SChen Feng reg = <0x0 0xfdf00000 0x0 0x1000>; 370254b07b2SChen Feng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 371254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 372254b07b2SChen Feng <&crg_ctrl HI3660_CLK_GATE_UART1>; 373254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 374254b07b2SChen Feng pinctrl-names = "default"; 375254b07b2SChen Feng pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 376254b07b2SChen Feng status = "disabled"; 377254b07b2SChen Feng }; 378254b07b2SChen Feng 379254b07b2SChen Feng uart2: serial@fdf03000 { 380254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 381254b07b2SChen Feng reg = <0x0 0xfdf03000 0x0 0x1000>; 382254b07b2SChen Feng interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 383254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 384254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 385254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 386254b07b2SChen Feng pinctrl-names = "default"; 387254b07b2SChen Feng pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 388254b07b2SChen Feng status = "disabled"; 389254b07b2SChen Feng }; 390254b07b2SChen Feng 391254b07b2SChen Feng uart3: serial@ffd74000 { 392254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 393254b07b2SChen Feng reg = <0x0 0xffd74000 0x0 0x1000>; 394254b07b2SChen Feng interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 395254b07b2SChen Feng clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 396254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 397254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 398254b07b2SChen Feng pinctrl-names = "default"; 399254b07b2SChen Feng pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 400254b07b2SChen Feng status = "disabled"; 401254b07b2SChen Feng }; 402254b07b2SChen Feng 403254b07b2SChen Feng uart4: serial@fdf01000 { 404254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 405254b07b2SChen Feng reg = <0x0 0xfdf01000 0x0 0x1000>; 406254b07b2SChen Feng interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 407254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 408254b07b2SChen Feng <&crg_ctrl HI3660_CLK_GATE_UART4>; 409254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 410254b07b2SChen Feng pinctrl-names = "default"; 411254b07b2SChen Feng pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 412254b07b2SChen Feng status = "disabled"; 413254b07b2SChen Feng }; 414254b07b2SChen Feng 415a4e36ae0SZhangfei Gao uart5: serial@fdf05000 { 41635ca8168SChen Feng compatible = "arm,pl011", "arm,primecell"; 41735ca8168SChen Feng reg = <0x0 0xfdf05000 0x0 0x1000>; 41835ca8168SChen Feng interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 419a4e36ae0SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 420a4e36ae0SZhangfei Gao <&crg_ctrl HI3660_CLK_GATE_UART5>; 42135ca8168SChen Feng clock-names = "uartclk", "apb_pclk"; 422254b07b2SChen Feng pinctrl-names = "default"; 423254b07b2SChen Feng pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 424254b07b2SChen Feng status = "disabled"; 425254b07b2SChen Feng }; 426254b07b2SChen Feng 427254b07b2SChen Feng uart6: serial@fff32000 { 428254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 429254b07b2SChen Feng reg = <0x0 0xfff32000 0x0 0x1000>; 430254b07b2SChen Feng interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 431254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_UART6>, 432254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 433254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 434254b07b2SChen Feng pinctrl-names = "default"; 435254b07b2SChen Feng pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 43635ca8168SChen Feng status = "disabled"; 43735ca8168SChen Feng }; 438d94eab86SWang Xiaoyin 4390a0698f6SChen Feng rtc0: rtc@fff04000 { 4400a0698f6SChen Feng compatible = "arm,pl031", "arm,primecell"; 4410a0698f6SChen Feng reg = <0x0 0Xfff04000 0x0 0x1000>; 4420a0698f6SChen Feng interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 4430a0698f6SChen Feng clocks = <&crg_ctrl HI3660_PCLK>; 4440a0698f6SChen Feng clock-names = "apb_pclk"; 4450a0698f6SChen Feng }; 4460a0698f6SChen Feng 447d94eab86SWang Xiaoyin gpio0: gpio@e8a0b000 { 448d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 449d94eab86SWang Xiaoyin reg = <0 0xe8a0b000 0 0x1000>; 450d94eab86SWang Xiaoyin interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 451d94eab86SWang Xiaoyin gpio-controller; 452d94eab86SWang Xiaoyin #gpio-cells = <2>; 453d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 0 7>; 454d94eab86SWang Xiaoyin interrupt-controller; 455d94eab86SWang Xiaoyin #interrupt-cells = <2>; 456d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 457d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 458d94eab86SWang Xiaoyin }; 459d94eab86SWang Xiaoyin 460d94eab86SWang Xiaoyin gpio1: gpio@e8a0c000 { 461d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 462d94eab86SWang Xiaoyin reg = <0 0xe8a0c000 0 0x1000>; 463d94eab86SWang Xiaoyin interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 464d94eab86SWang Xiaoyin gpio-controller; 465d94eab86SWang Xiaoyin #gpio-cells = <2>; 466d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 7 7>; 467d94eab86SWang Xiaoyin interrupt-controller; 468d94eab86SWang Xiaoyin #interrupt-cells = <2>; 469d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 470d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 471d94eab86SWang Xiaoyin }; 472d94eab86SWang Xiaoyin 473d94eab86SWang Xiaoyin gpio2: gpio@e8a0d000 { 474d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 475d94eab86SWang Xiaoyin reg = <0 0xe8a0d000 0 0x1000>; 476d94eab86SWang Xiaoyin interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 477d94eab86SWang Xiaoyin gpio-controller; 478d94eab86SWang Xiaoyin #gpio-cells = <2>; 479d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 14 8>; 480d94eab86SWang Xiaoyin interrupt-controller; 481d94eab86SWang Xiaoyin #interrupt-cells = <2>; 482d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 483d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 484d94eab86SWang Xiaoyin }; 485d94eab86SWang Xiaoyin 486d94eab86SWang Xiaoyin gpio3: gpio@e8a0e000 { 487d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 488d94eab86SWang Xiaoyin reg = <0 0xe8a0e000 0 0x1000>; 489d94eab86SWang Xiaoyin interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 490d94eab86SWang Xiaoyin gpio-controller; 491d94eab86SWang Xiaoyin #gpio-cells = <2>; 492d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 22 8>; 493d94eab86SWang Xiaoyin interrupt-controller; 494d94eab86SWang Xiaoyin #interrupt-cells = <2>; 495d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 496d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 497d94eab86SWang Xiaoyin }; 498d94eab86SWang Xiaoyin 499d94eab86SWang Xiaoyin gpio4: gpio@e8a0f000 { 500d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 501d94eab86SWang Xiaoyin reg = <0 0xe8a0f000 0 0x1000>; 502d94eab86SWang Xiaoyin interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 503d94eab86SWang Xiaoyin gpio-controller; 504d94eab86SWang Xiaoyin #gpio-cells = <2>; 505d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 30 8>; 506d94eab86SWang Xiaoyin interrupt-controller; 507d94eab86SWang Xiaoyin #interrupt-cells = <2>; 508d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 509d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 510d94eab86SWang Xiaoyin }; 511d94eab86SWang Xiaoyin 512d94eab86SWang Xiaoyin gpio5: gpio@e8a10000 { 513d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 514d94eab86SWang Xiaoyin reg = <0 0xe8a10000 0 0x1000>; 515d94eab86SWang Xiaoyin interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 516d94eab86SWang Xiaoyin gpio-controller; 517d94eab86SWang Xiaoyin #gpio-cells = <2>; 518d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 38 8>; 519d94eab86SWang Xiaoyin interrupt-controller; 520d94eab86SWang Xiaoyin #interrupt-cells = <2>; 521d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 522d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 523d94eab86SWang Xiaoyin }; 524d94eab86SWang Xiaoyin 525d94eab86SWang Xiaoyin gpio6: gpio@e8a11000 { 526d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 527d94eab86SWang Xiaoyin reg = <0 0xe8a11000 0 0x1000>; 528d94eab86SWang Xiaoyin interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 529d94eab86SWang Xiaoyin gpio-controller; 530d94eab86SWang Xiaoyin #gpio-cells = <2>; 531d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 46 8>; 532d94eab86SWang Xiaoyin interrupt-controller; 533d94eab86SWang Xiaoyin #interrupt-cells = <2>; 534d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 535d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 536d94eab86SWang Xiaoyin }; 537d94eab86SWang Xiaoyin 538d94eab86SWang Xiaoyin gpio7: gpio@e8a12000 { 539d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 540d94eab86SWang Xiaoyin reg = <0 0xe8a12000 0 0x1000>; 541d94eab86SWang Xiaoyin interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 542d94eab86SWang Xiaoyin gpio-controller; 543d94eab86SWang Xiaoyin #gpio-cells = <2>; 544d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 54 8>; 545d94eab86SWang Xiaoyin interrupt-controller; 546d94eab86SWang Xiaoyin #interrupt-cells = <2>; 547d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 548d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 549d94eab86SWang Xiaoyin }; 550d94eab86SWang Xiaoyin 551d94eab86SWang Xiaoyin gpio8: gpio@e8a13000 { 552d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 553d94eab86SWang Xiaoyin reg = <0 0xe8a13000 0 0x1000>; 554d94eab86SWang Xiaoyin interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 555d94eab86SWang Xiaoyin gpio-controller; 556d94eab86SWang Xiaoyin #gpio-cells = <2>; 557d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 62 8>; 558d94eab86SWang Xiaoyin interrupt-controller; 559d94eab86SWang Xiaoyin #interrupt-cells = <2>; 560d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 561d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 562d94eab86SWang Xiaoyin }; 563d94eab86SWang Xiaoyin 564d94eab86SWang Xiaoyin gpio9: gpio@e8a14000 { 565d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 566d94eab86SWang Xiaoyin reg = <0 0xe8a14000 0 0x1000>; 567d94eab86SWang Xiaoyin interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 568d94eab86SWang Xiaoyin gpio-controller; 569d94eab86SWang Xiaoyin #gpio-cells = <2>; 570d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 70 8>; 571d94eab86SWang Xiaoyin interrupt-controller; 572d94eab86SWang Xiaoyin #interrupt-cells = <2>; 573d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 574d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 575d94eab86SWang Xiaoyin }; 576d94eab86SWang Xiaoyin 577d94eab86SWang Xiaoyin gpio10: gpio@e8a15000 { 578d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 579d94eab86SWang Xiaoyin reg = <0 0xe8a15000 0 0x1000>; 580d94eab86SWang Xiaoyin interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 581d94eab86SWang Xiaoyin gpio-controller; 582d94eab86SWang Xiaoyin #gpio-cells = <2>; 583d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 78 8>; 584d94eab86SWang Xiaoyin interrupt-controller; 585d94eab86SWang Xiaoyin #interrupt-cells = <2>; 586d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 587d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 588d94eab86SWang Xiaoyin }; 589d94eab86SWang Xiaoyin 590d94eab86SWang Xiaoyin gpio11: gpio@e8a16000 { 591d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 592d94eab86SWang Xiaoyin reg = <0 0xe8a16000 0 0x1000>; 593d94eab86SWang Xiaoyin interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 594d94eab86SWang Xiaoyin gpio-controller; 595d94eab86SWang Xiaoyin #gpio-cells = <2>; 596d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 86 8>; 597d94eab86SWang Xiaoyin interrupt-controller; 598d94eab86SWang Xiaoyin #interrupt-cells = <2>; 599d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 600d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 601d94eab86SWang Xiaoyin }; 602d94eab86SWang Xiaoyin 603d94eab86SWang Xiaoyin gpio12: gpio@e8a17000 { 604d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 605d94eab86SWang Xiaoyin reg = <0 0xe8a17000 0 0x1000>; 606d94eab86SWang Xiaoyin interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 607d94eab86SWang Xiaoyin gpio-controller; 608d94eab86SWang Xiaoyin #gpio-cells = <2>; 609d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 610d94eab86SWang Xiaoyin interrupt-controller; 611d94eab86SWang Xiaoyin #interrupt-cells = <2>; 612d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 613d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 614d94eab86SWang Xiaoyin }; 615d94eab86SWang Xiaoyin 616d94eab86SWang Xiaoyin gpio13: gpio@e8a18000 { 617d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 618d94eab86SWang Xiaoyin reg = <0 0xe8a18000 0 0x1000>; 619d94eab86SWang Xiaoyin interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 620d94eab86SWang Xiaoyin gpio-controller; 621d94eab86SWang Xiaoyin #gpio-cells = <2>; 622d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 102 8>; 623d94eab86SWang Xiaoyin interrupt-controller; 624d94eab86SWang Xiaoyin #interrupt-cells = <2>; 625d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 626d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 627d94eab86SWang Xiaoyin }; 628d94eab86SWang Xiaoyin 629d94eab86SWang Xiaoyin gpio14: gpio@e8a19000 { 630d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 631d94eab86SWang Xiaoyin reg = <0 0xe8a19000 0 0x1000>; 632d94eab86SWang Xiaoyin interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 633d94eab86SWang Xiaoyin gpio-controller; 634d94eab86SWang Xiaoyin #gpio-cells = <2>; 635d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 110 8>; 636d94eab86SWang Xiaoyin interrupt-controller; 637d94eab86SWang Xiaoyin #interrupt-cells = <2>; 638d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 639d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 640d94eab86SWang Xiaoyin }; 641d94eab86SWang Xiaoyin 642d94eab86SWang Xiaoyin gpio15: gpio@e8a1a000 { 643d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 644d94eab86SWang Xiaoyin reg = <0 0xe8a1a000 0 0x1000>; 645d94eab86SWang Xiaoyin interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 646d94eab86SWang Xiaoyin gpio-controller; 647d94eab86SWang Xiaoyin #gpio-cells = <2>; 648d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 118 6>; 649d94eab86SWang Xiaoyin interrupt-controller; 650d94eab86SWang Xiaoyin #interrupt-cells = <2>; 651d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 652d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 653d94eab86SWang Xiaoyin }; 654d94eab86SWang Xiaoyin 655d94eab86SWang Xiaoyin gpio16: gpio@e8a1b000 { 656d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 657d94eab86SWang Xiaoyin reg = <0 0xe8a1b000 0 0x1000>; 658d94eab86SWang Xiaoyin interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 659d94eab86SWang Xiaoyin gpio-controller; 660d94eab86SWang Xiaoyin #gpio-cells = <2>; 661d94eab86SWang Xiaoyin interrupt-controller; 662d94eab86SWang Xiaoyin #interrupt-cells = <2>; 663d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 664d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 665d94eab86SWang Xiaoyin }; 666d94eab86SWang Xiaoyin 667d94eab86SWang Xiaoyin gpio17: gpio@e8a1c000 { 668d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 669d94eab86SWang Xiaoyin reg = <0 0xe8a1c000 0 0x1000>; 670d94eab86SWang Xiaoyin interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 671d94eab86SWang Xiaoyin gpio-controller; 672d94eab86SWang Xiaoyin #gpio-cells = <2>; 673d94eab86SWang Xiaoyin interrupt-controller; 674d94eab86SWang Xiaoyin #interrupt-cells = <2>; 675d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 676d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 677d94eab86SWang Xiaoyin }; 678d94eab86SWang Xiaoyin 679d94eab86SWang Xiaoyin gpio18: gpio@ff3b4000 { 680d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 681d94eab86SWang Xiaoyin reg = <0 0xff3b4000 0 0x1000>; 682d94eab86SWang Xiaoyin interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 683d94eab86SWang Xiaoyin gpio-controller; 684d94eab86SWang Xiaoyin #gpio-cells = <2>; 685d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 0 8>; 686d94eab86SWang Xiaoyin interrupt-controller; 687d94eab86SWang Xiaoyin #interrupt-cells = <2>; 688d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 689d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 690d94eab86SWang Xiaoyin }; 691d94eab86SWang Xiaoyin 692d94eab86SWang Xiaoyin gpio19: gpio@ff3b5000 { 693d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 694d94eab86SWang Xiaoyin reg = <0 0xff3b5000 0 0x1000>; 695d94eab86SWang Xiaoyin interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 696d94eab86SWang Xiaoyin gpio-controller; 697d94eab86SWang Xiaoyin #gpio-cells = <2>; 698d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 8 4>; 699d94eab86SWang Xiaoyin interrupt-controller; 700d94eab86SWang Xiaoyin #interrupt-cells = <2>; 701d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 702d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 703d94eab86SWang Xiaoyin }; 704d94eab86SWang Xiaoyin 705d94eab86SWang Xiaoyin gpio20: gpio@e8a1f000 { 706d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 707d94eab86SWang Xiaoyin reg = <0 0xe8a1f000 0 0x1000>; 708d94eab86SWang Xiaoyin interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 709d94eab86SWang Xiaoyin gpio-controller; 710d94eab86SWang Xiaoyin #gpio-cells = <2>; 711d94eab86SWang Xiaoyin gpio-ranges = <&pmx1 0 0 6>; 712d94eab86SWang Xiaoyin interrupt-controller; 713d94eab86SWang Xiaoyin #interrupt-cells = <2>; 714d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 715d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 716d94eab86SWang Xiaoyin }; 717d94eab86SWang Xiaoyin 718d94eab86SWang Xiaoyin gpio21: gpio@e8a20000 { 719d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 720d94eab86SWang Xiaoyin reg = <0 0xe8a20000 0 0x1000>; 721d94eab86SWang Xiaoyin interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 722d94eab86SWang Xiaoyin gpio-controller; 723d94eab86SWang Xiaoyin #gpio-cells = <2>; 724d94eab86SWang Xiaoyin interrupt-controller; 725d94eab86SWang Xiaoyin #interrupt-cells = <2>; 726d94eab86SWang Xiaoyin gpio-ranges = <&pmx3 0 0 6>; 727d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 728d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 729d94eab86SWang Xiaoyin }; 730d94eab86SWang Xiaoyin 731d94eab86SWang Xiaoyin gpio22: gpio@fff0b000 { 732d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 733d94eab86SWang Xiaoyin reg = <0 0xfff0b000 0 0x1000>; 734d94eab86SWang Xiaoyin interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 735d94eab86SWang Xiaoyin gpio-controller; 736d94eab86SWang Xiaoyin #gpio-cells = <2>; 737d94eab86SWang Xiaoyin /* GPIO176 */ 738d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 2 0 6>; 739d94eab86SWang Xiaoyin interrupt-controller; 740d94eab86SWang Xiaoyin #interrupt-cells = <2>; 741d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 742d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 743d94eab86SWang Xiaoyin }; 744d94eab86SWang Xiaoyin 745d94eab86SWang Xiaoyin gpio23: gpio@fff0c000 { 746d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 747d94eab86SWang Xiaoyin reg = <0 0xfff0c000 0 0x1000>; 748d94eab86SWang Xiaoyin interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 749d94eab86SWang Xiaoyin gpio-controller; 750d94eab86SWang Xiaoyin #gpio-cells = <2>; 751d94eab86SWang Xiaoyin /* GPIO184 */ 752d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 6 7>; 753d94eab86SWang Xiaoyin interrupt-controller; 754d94eab86SWang Xiaoyin #interrupt-cells = <2>; 755d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 756d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 757d94eab86SWang Xiaoyin }; 758d94eab86SWang Xiaoyin 759d94eab86SWang Xiaoyin gpio24: gpio@fff0d000 { 760d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 761d94eab86SWang Xiaoyin reg = <0 0xfff0d000 0 0x1000>; 762d94eab86SWang Xiaoyin interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 763d94eab86SWang Xiaoyin gpio-controller; 764d94eab86SWang Xiaoyin #gpio-cells = <2>; 765d94eab86SWang Xiaoyin /* GPIO192 */ 766d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 13 8>; 767d94eab86SWang Xiaoyin interrupt-controller; 768d94eab86SWang Xiaoyin #interrupt-cells = <2>; 769d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 770d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 771d94eab86SWang Xiaoyin }; 772d94eab86SWang Xiaoyin 773d94eab86SWang Xiaoyin gpio25: gpio@fff0e000 { 774d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 775d94eab86SWang Xiaoyin reg = <0 0xfff0e000 0 0x1000>; 776d94eab86SWang Xiaoyin interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 777d94eab86SWang Xiaoyin gpio-controller; 778d94eab86SWang Xiaoyin #gpio-cells = <2>; 779d94eab86SWang Xiaoyin /* GPIO200 */ 780d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 781d94eab86SWang Xiaoyin interrupt-controller; 782d94eab86SWang Xiaoyin #interrupt-cells = <2>; 783d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 784d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 785d94eab86SWang Xiaoyin }; 786d94eab86SWang Xiaoyin 787d94eab86SWang Xiaoyin gpio26: gpio@fff0f000 { 788d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 789d94eab86SWang Xiaoyin reg = <0 0xfff0f000 0 0x1000>; 790d94eab86SWang Xiaoyin interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 791d94eab86SWang Xiaoyin gpio-controller; 792d94eab86SWang Xiaoyin #gpio-cells = <2>; 793d94eab86SWang Xiaoyin /* GPIO208 */ 794d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 28 8>; 795d94eab86SWang Xiaoyin interrupt-controller; 796d94eab86SWang Xiaoyin #interrupt-cells = <2>; 797d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 798d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 799d94eab86SWang Xiaoyin }; 800d94eab86SWang Xiaoyin 801d94eab86SWang Xiaoyin gpio27: gpio@fff10000 { 802d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 803d94eab86SWang Xiaoyin reg = <0 0xfff10000 0 0x1000>; 804d94eab86SWang Xiaoyin interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 805d94eab86SWang Xiaoyin gpio-controller; 806d94eab86SWang Xiaoyin #gpio-cells = <2>; 807d94eab86SWang Xiaoyin /* GPIO216 */ 808d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 36 6>; 809d94eab86SWang Xiaoyin interrupt-controller; 810d94eab86SWang Xiaoyin #interrupt-cells = <2>; 811d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 812d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 813d94eab86SWang Xiaoyin }; 814d94eab86SWang Xiaoyin 815d94eab86SWang Xiaoyin gpio28: gpio@fff1d000 { 816d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 817d94eab86SWang Xiaoyin reg = <0 0xfff1d000 0 0x1000>; 818d94eab86SWang Xiaoyin interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 819d94eab86SWang Xiaoyin gpio-controller; 820d94eab86SWang Xiaoyin #gpio-cells = <2>; 821d94eab86SWang Xiaoyin interrupt-controller; 822d94eab86SWang Xiaoyin #interrupt-cells = <2>; 823d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 824d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 825d94eab86SWang Xiaoyin }; 82638810497SWang Xiaoyin 82738810497SWang Xiaoyin spi2: spi@ffd68000 { 82838810497SWang Xiaoyin compatible = "arm,pl022", "arm,primecell"; 82938810497SWang Xiaoyin reg = <0x0 0xffd68000 0x0 0x1000>; 83038810497SWang Xiaoyin #address-cells = <1>; 83138810497SWang Xiaoyin #size-cells = <0>; 83238810497SWang Xiaoyin interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 83338810497SWang Xiaoyin clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; 83438810497SWang Xiaoyin clock-names = "apb_pclk"; 83538810497SWang Xiaoyin pinctrl-names = "default"; 83638810497SWang Xiaoyin pinctrl-0 = <&spi2_pmx_func>; 83738810497SWang Xiaoyin num-cs = <1>; 83838810497SWang Xiaoyin cs-gpios = <&gpio27 2 0>; 83938810497SWang Xiaoyin status = "disabled"; 84038810497SWang Xiaoyin }; 84138810497SWang Xiaoyin 84238810497SWang Xiaoyin spi3: spi@ff3b3000 { 84338810497SWang Xiaoyin compatible = "arm,pl022", "arm,primecell"; 84438810497SWang Xiaoyin reg = <0x0 0xff3b3000 0x0 0x1000>; 84538810497SWang Xiaoyin #address-cells = <1>; 84638810497SWang Xiaoyin #size-cells = <0>; 84738810497SWang Xiaoyin interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 84838810497SWang Xiaoyin clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; 84938810497SWang Xiaoyin clock-names = "apb_pclk"; 85038810497SWang Xiaoyin pinctrl-names = "default"; 85138810497SWang Xiaoyin pinctrl-0 = <&spi3_pmx_func>; 85238810497SWang Xiaoyin num-cs = <1>; 85338810497SWang Xiaoyin cs-gpios = <&gpio18 5 0>; 85438810497SWang Xiaoyin status = "disabled"; 85538810497SWang Xiaoyin }; 85696909778SXiaowei Song 85796909778SXiaowei Song pcie@f4000000 { 85896909778SXiaowei Song compatible = "hisilicon,kirin960-pcie"; 85996909778SXiaowei Song reg = <0x0 0xf4000000 0x0 0x1000>, 86096909778SXiaowei Song <0x0 0xff3fe000 0x0 0x1000>, 86196909778SXiaowei Song <0x0 0xf3f20000 0x0 0x40000>, 86296909778SXiaowei Song <0x0 0xf5000000 0x0 0x2000>; 86396909778SXiaowei Song reg-names = "dbi", "apb", "phy", "config"; 86496909778SXiaowei Song bus-range = <0x0 0x1>; 86596909778SXiaowei Song #address-cells = <3>; 86696909778SXiaowei Song #size-cells = <2>; 86796909778SXiaowei Song device_type = "pci"; 86896909778SXiaowei Song ranges = <0x02000000 0x0 0x00000000 86996909778SXiaowei Song 0x0 0xf6000000 87096909778SXiaowei Song 0x0 0x02000000>; 87196909778SXiaowei Song num-lanes = <1>; 87296909778SXiaowei Song #interrupt-cells = <1>; 87396909778SXiaowei Song interrupt-map-mask = <0xf800 0 0 7>; 87496909778SXiaowei Song interrupt-map = <0x0 0 0 1 87596909778SXiaowei Song &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 87696909778SXiaowei Song <0x0 0 0 2 87796909778SXiaowei Song &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 87896909778SXiaowei Song <0x0 0 0 3 87996909778SXiaowei Song &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 88096909778SXiaowei Song <0x0 0 0 4 88196909778SXiaowei Song &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 88296909778SXiaowei Song clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 88396909778SXiaowei Song <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 88496909778SXiaowei Song <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 88596909778SXiaowei Song <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 88696909778SXiaowei Song <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 88796909778SXiaowei Song clock-names = "pcie_phy_ref", "pcie_aux", 88896909778SXiaowei Song "pcie_apb_phy", "pcie_apb_sys", 88996909778SXiaowei Song "pcie_aclk"; 89096909778SXiaowei Song reset-gpios = <&gpio11 1 0 >; 89196909778SXiaowei Song }; 892804d7d7aSLi Wei 893804d7d7aSLi Wei /* SD */ 894804d7d7aSLi Wei dwmmc1: dwmmc1@ff37f000 { 895804d7d7aSLi Wei #address-cells = <1>; 896804d7d7aSLi Wei #size-cells = <0>; 897804d7d7aSLi Wei cd-inverted; 898804d7d7aSLi Wei compatible = "hisilicon,hi3660-dw-mshc"; 899804d7d7aSLi Wei num-slots = <1>; 900804d7d7aSLi Wei bus-width = <0x4>; 901804d7d7aSLi Wei disable-wp; 902804d7d7aSLi Wei cap-sd-highspeed; 903804d7d7aSLi Wei supports-highspeed; 904804d7d7aSLi Wei card-detect-delay = <200>; 905804d7d7aSLi Wei reg = <0x0 0xff37f000 0x0 0x1000>; 906804d7d7aSLi Wei interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 907804d7d7aSLi Wei clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, 908804d7d7aSLi Wei <&crg_ctrl HI3660_HCLK_GATE_SD>; 909804d7d7aSLi Wei clock-names = "ciu", "biu"; 910804d7d7aSLi Wei clock-frequency = <3200000>; 911804d7d7aSLi Wei resets = <&crg_rst 0x94 18>; 912804d7d7aSLi Wei cd-gpios = <&gpio25 3 0>; 913804d7d7aSLi Wei hisilicon,peripheral-syscon = <&sctrl>; 914804d7d7aSLi Wei pinctrl-names = "default"; 915804d7d7aSLi Wei pinctrl-0 = <&sd_pmx_func 916804d7d7aSLi Wei &sd_clk_cfg_func 917804d7d7aSLi Wei &sd_cfg_func>; 918804d7d7aSLi Wei sd-uhs-sdr12; 919804d7d7aSLi Wei sd-uhs-sdr25; 920804d7d7aSLi Wei sd-uhs-sdr50; 921804d7d7aSLi Wei sd-uhs-sdr104; 922804d7d7aSLi Wei status = "disabled"; 923804d7d7aSLi Wei 924804d7d7aSLi Wei slot@0 { 925804d7d7aSLi Wei reg = <0x0>; 926804d7d7aSLi Wei bus-width = <4>; 927804d7d7aSLi Wei disable-wp; 928804d7d7aSLi Wei }; 929804d7d7aSLi Wei }; 930804d7d7aSLi Wei 931804d7d7aSLi Wei /* SDIO */ 932804d7d7aSLi Wei dwmmc2: dwmmc2@ff3ff000 { 933804d7d7aSLi Wei compatible = "hisilicon,hi3660-dw-mshc"; 934804d7d7aSLi Wei reg = <0x0 0xff3ff000 0x0 0x1000>; 935804d7d7aSLi Wei interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 936804d7d7aSLi Wei num-slots = <1>; 937804d7d7aSLi Wei clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, 938804d7d7aSLi Wei <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; 939804d7d7aSLi Wei clock-names = "ciu", "biu"; 940804d7d7aSLi Wei resets = <&crg_rst 0x94 20>; 941804d7d7aSLi Wei card-detect-delay = <200>; 942804d7d7aSLi Wei supports-highspeed; 943804d7d7aSLi Wei keep-power-in-suspend; 944804d7d7aSLi Wei pinctrl-names = "default"; 945804d7d7aSLi Wei pinctrl-0 = <&sdio_pmx_func 946804d7d7aSLi Wei &sdio_clk_cfg_func 947804d7d7aSLi Wei &sdio_cfg_func>; 948804d7d7aSLi Wei status = "disabled"; 949804d7d7aSLi Wei }; 95035ca8168SChen Feng }; 95135ca8168SChen Feng}; 952