1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 235ca8168SChen Feng/* 335ca8168SChen Feng * dts file for Hisilicon Hi3660 SoC 435ca8168SChen Feng * 535ca8168SChen Feng * Copyright (C) 2016, Hisilicon Ltd. 635ca8168SChen Feng */ 735ca8168SChen Feng 835ca8168SChen Feng#include <dt-bindings/interrupt-controller/arm-gic.h> 9a4e36ae0SZhangfei Gao#include <dt-bindings/clock/hi3660-clock.h> 1035ca8168SChen Feng 1135ca8168SChen Feng/ { 1235ca8168SChen Feng compatible = "hisilicon,hi3660"; 1335ca8168SChen Feng interrupt-parent = <&gic>; 1435ca8168SChen Feng #address-cells = <2>; 1535ca8168SChen Feng #size-cells = <2>; 1635ca8168SChen Feng 1735ca8168SChen Feng psci { 1835ca8168SChen Feng compatible = "arm,psci-0.2"; 1935ca8168SChen Feng method = "smc"; 2035ca8168SChen Feng }; 2135ca8168SChen Feng 2235ca8168SChen Feng cpus { 2335ca8168SChen Feng #address-cells = <2>; 2435ca8168SChen Feng #size-cells = <0>; 2535ca8168SChen Feng 2635ca8168SChen Feng cpu-map { 2735ca8168SChen Feng cluster0 { 2835ca8168SChen Feng core0 { 2935ca8168SChen Feng cpu = <&cpu0>; 3035ca8168SChen Feng }; 3135ca8168SChen Feng core1 { 3235ca8168SChen Feng cpu = <&cpu1>; 3335ca8168SChen Feng }; 3435ca8168SChen Feng core2 { 3535ca8168SChen Feng cpu = <&cpu2>; 3635ca8168SChen Feng }; 3735ca8168SChen Feng core3 { 3835ca8168SChen Feng cpu = <&cpu3>; 3935ca8168SChen Feng }; 4035ca8168SChen Feng }; 4135ca8168SChen Feng cluster1 { 4235ca8168SChen Feng core0 { 4335ca8168SChen Feng cpu = <&cpu4>; 4435ca8168SChen Feng }; 4535ca8168SChen Feng core1 { 4635ca8168SChen Feng cpu = <&cpu5>; 4735ca8168SChen Feng }; 4835ca8168SChen Feng core2 { 4935ca8168SChen Feng cpu = <&cpu6>; 5035ca8168SChen Feng }; 5135ca8168SChen Feng core3 { 5235ca8168SChen Feng cpu = <&cpu7>; 5335ca8168SChen Feng }; 5435ca8168SChen Feng }; 5535ca8168SChen Feng }; 5635ca8168SChen Feng 5735ca8168SChen Feng cpu0: cpu@0 { 5835ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 5935ca8168SChen Feng device_type = "cpu"; 6035ca8168SChen Feng reg = <0x0 0x0>; 6135ca8168SChen Feng enable-method = "psci"; 62a6d08344SLeo Yan next-level-cache = <&A53_L2>; 6330fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 649a9760deSValentin Schneider capacity-dmips-mhz = <592>; 65dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 66dfeae9e5SLeo Yan operating-points-v2 = <&cluster0_opp>; 6735ca8168SChen Feng }; 6835ca8168SChen Feng 6935ca8168SChen Feng cpu1: cpu@1 { 7035ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 7135ca8168SChen Feng device_type = "cpu"; 7235ca8168SChen Feng reg = <0x0 0x1>; 7335ca8168SChen Feng enable-method = "psci"; 74a6d08344SLeo Yan next-level-cache = <&A53_L2>; 7530fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 769a9760deSValentin Schneider capacity-dmips-mhz = <592>; 77dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 78dfeae9e5SLeo Yan operating-points-v2 = <&cluster0_opp>; 7935ca8168SChen Feng }; 8035ca8168SChen Feng 8135ca8168SChen Feng cpu2: cpu@2 { 8235ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 8335ca8168SChen Feng device_type = "cpu"; 8435ca8168SChen Feng reg = <0x0 0x2>; 8535ca8168SChen Feng enable-method = "psci"; 86a6d08344SLeo Yan next-level-cache = <&A53_L2>; 8730fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 889a9760deSValentin Schneider capacity-dmips-mhz = <592>; 89dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 90dfeae9e5SLeo Yan operating-points-v2 = <&cluster0_opp>; 9135ca8168SChen Feng }; 9235ca8168SChen Feng 9335ca8168SChen Feng cpu3: cpu@3 { 9435ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 9535ca8168SChen Feng device_type = "cpu"; 9635ca8168SChen Feng reg = <0x0 0x3>; 9735ca8168SChen Feng enable-method = "psci"; 98a6d08344SLeo Yan next-level-cache = <&A53_L2>; 9930fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 1009a9760deSValentin Schneider capacity-dmips-mhz = <592>; 101dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 102dfeae9e5SLeo Yan operating-points-v2 = <&cluster0_opp>; 10335ca8168SChen Feng }; 10435ca8168SChen Feng 10535ca8168SChen Feng cpu4: cpu@100 { 10635ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 10735ca8168SChen Feng device_type = "cpu"; 10835ca8168SChen Feng reg = <0x0 0x100>; 10935ca8168SChen Feng enable-method = "psci"; 110a6d08344SLeo Yan next-level-cache = <&A73_L2>; 111928c4a5cSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 1129a9760deSValentin Schneider capacity-dmips-mhz = <1024>; 113dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 114dfeae9e5SLeo Yan operating-points-v2 = <&cluster1_opp>; 11535ca8168SChen Feng }; 11635ca8168SChen Feng 11735ca8168SChen Feng cpu5: cpu@101 { 11835ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 11935ca8168SChen Feng device_type = "cpu"; 12035ca8168SChen Feng reg = <0x0 0x101>; 12135ca8168SChen Feng enable-method = "psci"; 122a6d08344SLeo Yan next-level-cache = <&A73_L2>; 123928c4a5cSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 1249a9760deSValentin Schneider capacity-dmips-mhz = <1024>; 125dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 126dfeae9e5SLeo Yan operating-points-v2 = <&cluster1_opp>; 12735ca8168SChen Feng }; 12835ca8168SChen Feng 12935ca8168SChen Feng cpu6: cpu@102 { 13035ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 13135ca8168SChen Feng device_type = "cpu"; 13235ca8168SChen Feng reg = <0x0 0x102>; 13335ca8168SChen Feng enable-method = "psci"; 134a6d08344SLeo Yan next-level-cache = <&A73_L2>; 135928c4a5cSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 1369a9760deSValentin Schneider capacity-dmips-mhz = <1024>; 137dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 138dfeae9e5SLeo Yan operating-points-v2 = <&cluster1_opp>; 13935ca8168SChen Feng }; 14035ca8168SChen Feng 14135ca8168SChen Feng cpu7: cpu@103 { 14235ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 14335ca8168SChen Feng device_type = "cpu"; 14435ca8168SChen Feng reg = <0x0 0x103>; 14535ca8168SChen Feng enable-method = "psci"; 146a6d08344SLeo Yan next-level-cache = <&A73_L2>; 147928c4a5cSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 1489a9760deSValentin Schneider capacity-dmips-mhz = <1024>; 149dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 150dfeae9e5SLeo Yan operating-points-v2 = <&cluster1_opp>; 15130fec826SLeo Yan }; 15230fec826SLeo Yan 15330fec826SLeo Yan idle-states { 15430fec826SLeo Yan entry-method = "psci"; 15530fec826SLeo Yan 15630fec826SLeo Yan CPU_SLEEP: cpu-sleep { 15730fec826SLeo Yan compatible = "arm,idle-state"; 15830fec826SLeo Yan local-timer-stop; 15930fec826SLeo Yan arm,psci-suspend-param = <0x0010000>; 16030fec826SLeo Yan entry-latency-us = <40>; 16130fec826SLeo Yan exit-latency-us = <70>; 16230fec826SLeo Yan min-residency-us = <3000>; 16330fec826SLeo Yan }; 16430fec826SLeo Yan 16530fec826SLeo Yan CLUSTER_SLEEP_0: cluster-sleep-0 { 16630fec826SLeo Yan compatible = "arm,idle-state"; 16730fec826SLeo Yan local-timer-stop; 16830fec826SLeo Yan arm,psci-suspend-param = <0x1010000>; 16930fec826SLeo Yan entry-latency-us = <500>; 17030fec826SLeo Yan exit-latency-us = <5000>; 17130fec826SLeo Yan min-residency-us = <20000>; 17230fec826SLeo Yan }; 17330fec826SLeo Yan 17430fec826SLeo Yan CLUSTER_SLEEP_1: cluster-sleep-1 { 17530fec826SLeo Yan compatible = "arm,idle-state"; 17630fec826SLeo Yan local-timer-stop; 17730fec826SLeo Yan arm,psci-suspend-param = <0x1010000>; 17830fec826SLeo Yan entry-latency-us = <1000>; 17930fec826SLeo Yan exit-latency-us = <5000>; 18030fec826SLeo Yan min-residency-us = <20000>; 18130fec826SLeo Yan }; 18235ca8168SChen Feng }; 183a6d08344SLeo Yan 184a6d08344SLeo Yan A53_L2: l2-cache0 { 185a6d08344SLeo Yan compatible = "cache"; 186a6d08344SLeo Yan }; 187a6d08344SLeo Yan 188a6d08344SLeo Yan A73_L2: l2-cache1 { 189a6d08344SLeo Yan compatible = "cache"; 190a6d08344SLeo Yan }; 19135ca8168SChen Feng }; 19235ca8168SChen Feng 193dfeae9e5SLeo Yan cluster0_opp: opp_table0 { 194dfeae9e5SLeo Yan compatible = "operating-points-v2"; 195dfeae9e5SLeo Yan opp-shared; 196dfeae9e5SLeo Yan 197dfeae9e5SLeo Yan opp00 { 198dfeae9e5SLeo Yan opp-hz = /bits/ 64 <533000000>; 199dfeae9e5SLeo Yan opp-microvolt = <700000>; 200dfeae9e5SLeo Yan clock-latency-ns = <300000>; 201dfeae9e5SLeo Yan }; 202dfeae9e5SLeo Yan 203dfeae9e5SLeo Yan opp01 { 204dfeae9e5SLeo Yan opp-hz = /bits/ 64 <999000000>; 205dfeae9e5SLeo Yan opp-microvolt = <800000>; 206dfeae9e5SLeo Yan clock-latency-ns = <300000>; 207dfeae9e5SLeo Yan }; 208dfeae9e5SLeo Yan 209dfeae9e5SLeo Yan opp02 { 210dfeae9e5SLeo Yan opp-hz = /bits/ 64 <1402000000>; 211dfeae9e5SLeo Yan opp-microvolt = <900000>; 212dfeae9e5SLeo Yan clock-latency-ns = <300000>; 213dfeae9e5SLeo Yan }; 214dfeae9e5SLeo Yan 215dfeae9e5SLeo Yan opp03 { 216dfeae9e5SLeo Yan opp-hz = /bits/ 64 <1709000000>; 217dfeae9e5SLeo Yan opp-microvolt = <1000000>; 218dfeae9e5SLeo Yan clock-latency-ns = <300000>; 219dfeae9e5SLeo Yan }; 220dfeae9e5SLeo Yan 221dfeae9e5SLeo Yan opp04 { 222dfeae9e5SLeo Yan opp-hz = /bits/ 64 <1844000000>; 223dfeae9e5SLeo Yan opp-microvolt = <1100000>; 224dfeae9e5SLeo Yan clock-latency-ns = <300000>; 225dfeae9e5SLeo Yan }; 226dfeae9e5SLeo Yan }; 227dfeae9e5SLeo Yan 228dfeae9e5SLeo Yan cluster1_opp: opp_table1 { 229dfeae9e5SLeo Yan compatible = "operating-points-v2"; 230dfeae9e5SLeo Yan opp-shared; 231dfeae9e5SLeo Yan 232dfeae9e5SLeo Yan opp10 { 233dfeae9e5SLeo Yan opp-hz = /bits/ 64 <903000000>; 234dfeae9e5SLeo Yan opp-microvolt = <700000>; 235dfeae9e5SLeo Yan clock-latency-ns = <300000>; 236dfeae9e5SLeo Yan }; 237dfeae9e5SLeo Yan 238dfeae9e5SLeo Yan opp11 { 239dfeae9e5SLeo Yan opp-hz = /bits/ 64 <1421000000>; 240dfeae9e5SLeo Yan opp-microvolt = <800000>; 241dfeae9e5SLeo Yan clock-latency-ns = <300000>; 242dfeae9e5SLeo Yan }; 243dfeae9e5SLeo Yan 244dfeae9e5SLeo Yan opp12 { 245dfeae9e5SLeo Yan opp-hz = /bits/ 64 <1805000000>; 246dfeae9e5SLeo Yan opp-microvolt = <900000>; 247dfeae9e5SLeo Yan clock-latency-ns = <300000>; 248dfeae9e5SLeo Yan }; 249dfeae9e5SLeo Yan 250dfeae9e5SLeo Yan opp13 { 251dfeae9e5SLeo Yan opp-hz = /bits/ 64 <2112000000>; 252dfeae9e5SLeo Yan opp-microvolt = <1000000>; 253dfeae9e5SLeo Yan clock-latency-ns = <300000>; 254dfeae9e5SLeo Yan }; 255dfeae9e5SLeo Yan 256dfeae9e5SLeo Yan opp14 { 257dfeae9e5SLeo Yan opp-hz = /bits/ 64 <2362000000>; 258dfeae9e5SLeo Yan opp-microvolt = <1100000>; 259dfeae9e5SLeo Yan clock-latency-ns = <300000>; 260dfeae9e5SLeo Yan }; 261dfeae9e5SLeo Yan }; 262dfeae9e5SLeo Yan 26335ca8168SChen Feng gic: interrupt-controller@e82b0000 { 26435ca8168SChen Feng compatible = "arm,gic-400"; 26535ca8168SChen Feng reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 26635ca8168SChen Feng <0x0 0xe82b2000 0 0x2000>, /* GICC */ 26735ca8168SChen Feng <0x0 0xe82b4000 0 0x2000>, /* GICH */ 26835ca8168SChen Feng <0x0 0xe82b6000 0 0x2000>; /* GICV */ 26935ca8168SChen Feng #address-cells = <0>; 27035ca8168SChen Feng #interrupt-cells = <3>; 27135ca8168SChen Feng interrupt-controller; 27235ca8168SChen Feng interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 27335ca8168SChen Feng IRQ_TYPE_LEVEL_HIGH)>; 27435ca8168SChen Feng }; 27535ca8168SChen Feng 276e07642faSXu YiPing a53-pmu { 277e07642faSXu YiPing compatible = "arm,cortex-a53-pmu"; 278f8054fb8SYiPing Xu interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 279f8054fb8SYiPing Xu <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 280f8054fb8SYiPing Xu <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 281e07642faSXu YiPing <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 282f8054fb8SYiPing Xu interrupt-affinity = <&cpu0>, 283f8054fb8SYiPing Xu <&cpu1>, 284f8054fb8SYiPing Xu <&cpu2>, 285e07642faSXu YiPing <&cpu3>; 286e07642faSXu YiPing }; 287e07642faSXu YiPing 288e07642faSXu YiPing a73-pmu { 289e07642faSXu YiPing compatible = "arm,cortex-a73-pmu"; 290e07642faSXu YiPing interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 291e07642faSXu YiPing <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 292e07642faSXu YiPing <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 293e07642faSXu YiPing <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 294e07642faSXu YiPing interrupt-affinity = <&cpu4>, 295f8054fb8SYiPing Xu <&cpu5>, 296f8054fb8SYiPing Xu <&cpu6>, 297f8054fb8SYiPing Xu <&cpu7>; 298f8054fb8SYiPing Xu }; 299f8054fb8SYiPing Xu 30035ca8168SChen Feng timer { 30135ca8168SChen Feng compatible = "arm,armv8-timer"; 30235ca8168SChen Feng interrupt-parent = <&gic>; 30335ca8168SChen Feng interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 30435ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 30535ca8168SChen Feng <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 30635ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 30735ca8168SChen Feng <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 30835ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 30935ca8168SChen Feng <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 31035ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>; 31135ca8168SChen Feng }; 31235ca8168SChen Feng 31335ca8168SChen Feng soc { 31435ca8168SChen Feng compatible = "simple-bus"; 31535ca8168SChen Feng #address-cells = <2>; 31635ca8168SChen Feng #size-cells = <2>; 31735ca8168SChen Feng ranges; 31835ca8168SChen Feng 319a4e36ae0SZhangfei Gao crg_ctrl: crg_ctrl@fff35000 { 320a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-crgctrl", "syscon"; 321a4e36ae0SZhangfei Gao reg = <0x0 0xfff35000 0x0 0x1000>; 322a4e36ae0SZhangfei Gao #clock-cells = <1>; 32335ca8168SChen Feng }; 32435ca8168SChen Feng 325a4e36ae0SZhangfei Gao crg_rst: crg_rst_controller { 326a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 327a4e36ae0SZhangfei Gao #reset-cells = <2>; 328a4e36ae0SZhangfei Gao hisi,rst-syscon = <&crg_ctrl>; 329a4e36ae0SZhangfei Gao }; 330a4e36ae0SZhangfei Gao 331a4e36ae0SZhangfei Gao 332a4e36ae0SZhangfei Gao pctrl: pctrl@e8a09000 { 333a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pctrl", "syscon"; 334a4e36ae0SZhangfei Gao reg = <0x0 0xe8a09000 0x0 0x2000>; 335a4e36ae0SZhangfei Gao #clock-cells = <1>; 336a4e36ae0SZhangfei Gao }; 337a4e36ae0SZhangfei Gao 338a4e36ae0SZhangfei Gao pmuctrl: crg_ctrl@fff34000 { 339a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 340a4e36ae0SZhangfei Gao reg = <0x0 0xfff34000 0x0 0x1000>; 341a4e36ae0SZhangfei Gao #clock-cells = <1>; 342a4e36ae0SZhangfei Gao }; 343a4e36ae0SZhangfei Gao 344a4e36ae0SZhangfei Gao sctrl: sctrl@fff0a000 { 345a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-sctrl", "syscon"; 346a4e36ae0SZhangfei Gao reg = <0x0 0xfff0a000 0x0 0x1000>; 347a4e36ae0SZhangfei Gao #clock-cells = <1>; 348a4e36ae0SZhangfei Gao }; 349a4e36ae0SZhangfei Gao 350a4e36ae0SZhangfei Gao iomcu: iomcu@ffd7e000 { 351a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-iomcu", "syscon"; 352a4e36ae0SZhangfei Gao reg = <0x0 0xffd7e000 0x0 0x1000>; 353a4e36ae0SZhangfei Gao #clock-cells = <1>; 354a4e36ae0SZhangfei Gao 355a4e36ae0SZhangfei Gao }; 356a4e36ae0SZhangfei Gao 357a4e36ae0SZhangfei Gao iomcu_rst: reset { 358a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 359a4e36ae0SZhangfei Gao hisi,rst-syscon = <&iomcu>; 360a4e36ae0SZhangfei Gao #reset-cells = <2>; 361a4e36ae0SZhangfei Gao }; 362a4e36ae0SZhangfei Gao 363ca905780SKaihua Zhong mailbox: mailbox@e896b000 { 364ca905780SKaihua Zhong compatible = "hisilicon,hi3660-mbox"; 365ca905780SKaihua Zhong reg = <0x0 0xe896b000 0x0 0x1000>; 366ca905780SKaihua Zhong interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 367ca905780SKaihua Zhong <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 368ca905780SKaihua Zhong #mbox-cells = <3>; 369ca905780SKaihua Zhong }; 370ca905780SKaihua Zhong 3716e2c52b3SKaihua Zhong stub_clock: stub_clock@e896b500 { 3726e2c52b3SKaihua Zhong compatible = "hisilicon,hi3660-stub-clk"; 3736e2c52b3SKaihua Zhong reg = <0x0 0xe896b500 0x0 0x0100>; 3746e2c52b3SKaihua Zhong #clock-cells = <1>; 3756e2c52b3SKaihua Zhong mboxes = <&mailbox 13 3 0>; 3766e2c52b3SKaihua Zhong }; 3776e2c52b3SKaihua Zhong 37875196330SLeo Yan dual_timer0: timer@fff14000 { 37975196330SLeo Yan compatible = "arm,sp804", "arm,primecell"; 38075196330SLeo Yan reg = <0x0 0xfff14000 0x0 0x1000>; 38175196330SLeo Yan interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 38275196330SLeo Yan <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 38375196330SLeo Yan clocks = <&crg_ctrl HI3660_OSC32K>, 38475196330SLeo Yan <&crg_ctrl HI3660_OSC32K>, 38575196330SLeo Yan <&crg_ctrl HI3660_OSC32K>; 38675196330SLeo Yan clock-names = "timer1", "timer2", "apb_pclk"; 38775196330SLeo Yan }; 38875196330SLeo Yan 3895f8a3b77SZhangfei Gao i2c0: i2c@ffd71000 { 3905f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 3915f8a3b77SZhangfei Gao reg = <0x0 0xffd71000 0x0 0x1000>; 3925f8a3b77SZhangfei Gao interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 3935f8a3b77SZhangfei Gao #address-cells = <1>; 3945f8a3b77SZhangfei Gao #size-cells = <0>; 3955f8a3b77SZhangfei Gao clock-frequency = <400000>; 3965f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 3975f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 3>; 3985f8a3b77SZhangfei Gao pinctrl-names = "default"; 3995f8a3b77SZhangfei Gao pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 4005f8a3b77SZhangfei Gao status = "disabled"; 4015f8a3b77SZhangfei Gao }; 4025f8a3b77SZhangfei Gao 4035f8a3b77SZhangfei Gao i2c1: i2c@ffd72000 { 4045f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 4055f8a3b77SZhangfei Gao reg = <0x0 0xffd72000 0x0 0x1000>; 4065f8a3b77SZhangfei Gao interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 4075f8a3b77SZhangfei Gao #address-cells = <1>; 4085f8a3b77SZhangfei Gao #size-cells = <0>; 4095f8a3b77SZhangfei Gao clock-frequency = <400000>; 4105f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 4115f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 4>; 4125f8a3b77SZhangfei Gao pinctrl-names = "default"; 4135f8a3b77SZhangfei Gao pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 4145f8a3b77SZhangfei Gao status = "disabled"; 4155f8a3b77SZhangfei Gao }; 4165f8a3b77SZhangfei Gao 4175f8a3b77SZhangfei Gao i2c3: i2c@fdf0c000 { 4185f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 4195f8a3b77SZhangfei Gao reg = <0x0 0xfdf0c000 0x0 0x1000>; 4205f8a3b77SZhangfei Gao interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4215f8a3b77SZhangfei Gao #address-cells = <1>; 4225f8a3b77SZhangfei Gao #size-cells = <0>; 4235f8a3b77SZhangfei Gao clock-frequency = <400000>; 4245f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 4255f8a3b77SZhangfei Gao resets = <&crg_rst 0x78 7>; 4265f8a3b77SZhangfei Gao pinctrl-names = "default"; 4275f8a3b77SZhangfei Gao pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 4285f8a3b77SZhangfei Gao status = "disabled"; 4295f8a3b77SZhangfei Gao }; 4305f8a3b77SZhangfei Gao 4315f8a3b77SZhangfei Gao i2c7: i2c@fdf0b000 { 4325f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 4335f8a3b77SZhangfei Gao reg = <0x0 0xfdf0b000 0x0 0x1000>; 4345f8a3b77SZhangfei Gao interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 4355f8a3b77SZhangfei Gao #address-cells = <1>; 4365f8a3b77SZhangfei Gao #size-cells = <0>; 4375f8a3b77SZhangfei Gao clock-frequency = <400000>; 4385f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 4395f8a3b77SZhangfei Gao resets = <&crg_rst 0x60 14>; 4405f8a3b77SZhangfei Gao pinctrl-names = "default"; 4415f8a3b77SZhangfei Gao pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 4425f8a3b77SZhangfei Gao status = "disabled"; 4435f8a3b77SZhangfei Gao }; 4445f8a3b77SZhangfei Gao 445254b07b2SChen Feng uart0: serial@fdf02000 { 446254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 447254b07b2SChen Feng reg = <0x0 0xfdf02000 0x0 0x1000>; 448254b07b2SChen Feng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 449254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 450254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 451254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 452254b07b2SChen Feng pinctrl-names = "default"; 453254b07b2SChen Feng pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 454254b07b2SChen Feng status = "disabled"; 455254b07b2SChen Feng }; 456254b07b2SChen Feng 457254b07b2SChen Feng uart1: serial@fdf00000 { 458254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 459254b07b2SChen Feng reg = <0x0 0xfdf00000 0x0 0x1000>; 460254b07b2SChen Feng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 461254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 462254b07b2SChen Feng <&crg_ctrl HI3660_CLK_GATE_UART1>; 463254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 464254b07b2SChen Feng pinctrl-names = "default"; 465254b07b2SChen Feng pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 466254b07b2SChen Feng status = "disabled"; 467254b07b2SChen Feng }; 468254b07b2SChen Feng 469254b07b2SChen Feng uart2: serial@fdf03000 { 470254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 471254b07b2SChen Feng reg = <0x0 0xfdf03000 0x0 0x1000>; 472254b07b2SChen Feng interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 473254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 474254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 475254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 476254b07b2SChen Feng pinctrl-names = "default"; 477254b07b2SChen Feng pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 478254b07b2SChen Feng status = "disabled"; 479254b07b2SChen Feng }; 480254b07b2SChen Feng 481254b07b2SChen Feng uart3: serial@ffd74000 { 482254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 483254b07b2SChen Feng reg = <0x0 0xffd74000 0x0 0x1000>; 484254b07b2SChen Feng interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 485254b07b2SChen Feng clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 486254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 487254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 488254b07b2SChen Feng pinctrl-names = "default"; 489254b07b2SChen Feng pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 490254b07b2SChen Feng status = "disabled"; 491254b07b2SChen Feng }; 492254b07b2SChen Feng 493254b07b2SChen Feng uart4: serial@fdf01000 { 494254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 495254b07b2SChen Feng reg = <0x0 0xfdf01000 0x0 0x1000>; 496254b07b2SChen Feng interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 497254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 498254b07b2SChen Feng <&crg_ctrl HI3660_CLK_GATE_UART4>; 499254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 500254b07b2SChen Feng pinctrl-names = "default"; 501254b07b2SChen Feng pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 502254b07b2SChen Feng status = "disabled"; 503254b07b2SChen Feng }; 504254b07b2SChen Feng 505a4e36ae0SZhangfei Gao uart5: serial@fdf05000 { 50635ca8168SChen Feng compatible = "arm,pl011", "arm,primecell"; 50735ca8168SChen Feng reg = <0x0 0xfdf05000 0x0 0x1000>; 50835ca8168SChen Feng interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 509a4e36ae0SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 510a4e36ae0SZhangfei Gao <&crg_ctrl HI3660_CLK_GATE_UART5>; 51135ca8168SChen Feng clock-names = "uartclk", "apb_pclk"; 512254b07b2SChen Feng pinctrl-names = "default"; 513254b07b2SChen Feng pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 514254b07b2SChen Feng status = "disabled"; 515254b07b2SChen Feng }; 516254b07b2SChen Feng 517254b07b2SChen Feng uart6: serial@fff32000 { 518254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 519254b07b2SChen Feng reg = <0x0 0xfff32000 0x0 0x1000>; 520254b07b2SChen Feng interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 521254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_UART6>, 522254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 523254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 524254b07b2SChen Feng pinctrl-names = "default"; 525254b07b2SChen Feng pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 52635ca8168SChen Feng status = "disabled"; 52735ca8168SChen Feng }; 528d94eab86SWang Xiaoyin 5290b507e91SWang Ruyi dma0: dma@fdf30000 { 5300b507e91SWang Ruyi compatible = "hisilicon,k3-dma-1.0"; 5310b507e91SWang Ruyi reg = <0x0 0xfdf30000 0x0 0x1000>; 5320b507e91SWang Ruyi #dma-cells = <1>; 5330b507e91SWang Ruyi dma-channels = <16>; 5340b507e91SWang Ruyi dma-requests = <32>; 5350b507e91SWang Ruyi dma-min-chan = <1>; 5360b507e91SWang Ruyi interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 5370b507e91SWang Ruyi clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; 5380b507e91SWang Ruyi dma-no-cci; 5390b507e91SWang Ruyi dma-type = "hi3660_dma"; 5400b507e91SWang Ruyi }; 5410b507e91SWang Ruyi 5420a0698f6SChen Feng rtc0: rtc@fff04000 { 5430a0698f6SChen Feng compatible = "arm,pl031", "arm,primecell"; 5440a0698f6SChen Feng reg = <0x0 0Xfff04000 0x0 0x1000>; 5450a0698f6SChen Feng interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 5460a0698f6SChen Feng clocks = <&crg_ctrl HI3660_PCLK>; 5470a0698f6SChen Feng clock-names = "apb_pclk"; 5480a0698f6SChen Feng }; 5490a0698f6SChen Feng 550d94eab86SWang Xiaoyin gpio0: gpio@e8a0b000 { 551d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 552d94eab86SWang Xiaoyin reg = <0 0xe8a0b000 0 0x1000>; 553d94eab86SWang Xiaoyin interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 554d94eab86SWang Xiaoyin gpio-controller; 555d94eab86SWang Xiaoyin #gpio-cells = <2>; 556d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 0 7>; 557d94eab86SWang Xiaoyin interrupt-controller; 558d94eab86SWang Xiaoyin #interrupt-cells = <2>; 559d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 560d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 561d94eab86SWang Xiaoyin }; 562d94eab86SWang Xiaoyin 563d94eab86SWang Xiaoyin gpio1: gpio@e8a0c000 { 564d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 565d94eab86SWang Xiaoyin reg = <0 0xe8a0c000 0 0x1000>; 566d94eab86SWang Xiaoyin interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 567d94eab86SWang Xiaoyin gpio-controller; 568d94eab86SWang Xiaoyin #gpio-cells = <2>; 569d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 7 7>; 570d94eab86SWang Xiaoyin interrupt-controller; 571d94eab86SWang Xiaoyin #interrupt-cells = <2>; 572d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 573d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 574d94eab86SWang Xiaoyin }; 575d94eab86SWang Xiaoyin 576d94eab86SWang Xiaoyin gpio2: gpio@e8a0d000 { 577d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 578d94eab86SWang Xiaoyin reg = <0 0xe8a0d000 0 0x1000>; 579d94eab86SWang Xiaoyin interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 580d94eab86SWang Xiaoyin gpio-controller; 581d94eab86SWang Xiaoyin #gpio-cells = <2>; 582d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 14 8>; 583d94eab86SWang Xiaoyin interrupt-controller; 584d94eab86SWang Xiaoyin #interrupt-cells = <2>; 585d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 586d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 587d94eab86SWang Xiaoyin }; 588d94eab86SWang Xiaoyin 589d94eab86SWang Xiaoyin gpio3: gpio@e8a0e000 { 590d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 591d94eab86SWang Xiaoyin reg = <0 0xe8a0e000 0 0x1000>; 592d94eab86SWang Xiaoyin interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 593d94eab86SWang Xiaoyin gpio-controller; 594d94eab86SWang Xiaoyin #gpio-cells = <2>; 595d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 22 8>; 596d94eab86SWang Xiaoyin interrupt-controller; 597d94eab86SWang Xiaoyin #interrupt-cells = <2>; 598d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 599d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 600d94eab86SWang Xiaoyin }; 601d94eab86SWang Xiaoyin 602d94eab86SWang Xiaoyin gpio4: gpio@e8a0f000 { 603d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 604d94eab86SWang Xiaoyin reg = <0 0xe8a0f000 0 0x1000>; 605d94eab86SWang Xiaoyin interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 606d94eab86SWang Xiaoyin gpio-controller; 607d94eab86SWang Xiaoyin #gpio-cells = <2>; 608d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 30 8>; 609d94eab86SWang Xiaoyin interrupt-controller; 610d94eab86SWang Xiaoyin #interrupt-cells = <2>; 611d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 612d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 613d94eab86SWang Xiaoyin }; 614d94eab86SWang Xiaoyin 615d94eab86SWang Xiaoyin gpio5: gpio@e8a10000 { 616d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 617d94eab86SWang Xiaoyin reg = <0 0xe8a10000 0 0x1000>; 618d94eab86SWang Xiaoyin interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 619d94eab86SWang Xiaoyin gpio-controller; 620d94eab86SWang Xiaoyin #gpio-cells = <2>; 621d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 38 8>; 622d94eab86SWang Xiaoyin interrupt-controller; 623d94eab86SWang Xiaoyin #interrupt-cells = <2>; 624d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 625d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 626d94eab86SWang Xiaoyin }; 627d94eab86SWang Xiaoyin 628d94eab86SWang Xiaoyin gpio6: gpio@e8a11000 { 629d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 630d94eab86SWang Xiaoyin reg = <0 0xe8a11000 0 0x1000>; 631d94eab86SWang Xiaoyin interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 632d94eab86SWang Xiaoyin gpio-controller; 633d94eab86SWang Xiaoyin #gpio-cells = <2>; 634d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 46 8>; 635d94eab86SWang Xiaoyin interrupt-controller; 636d94eab86SWang Xiaoyin #interrupt-cells = <2>; 637d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 638d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 639d94eab86SWang Xiaoyin }; 640d94eab86SWang Xiaoyin 641d94eab86SWang Xiaoyin gpio7: gpio@e8a12000 { 642d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 643d94eab86SWang Xiaoyin reg = <0 0xe8a12000 0 0x1000>; 644d94eab86SWang Xiaoyin interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 645d94eab86SWang Xiaoyin gpio-controller; 646d94eab86SWang Xiaoyin #gpio-cells = <2>; 647d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 54 8>; 648d94eab86SWang Xiaoyin interrupt-controller; 649d94eab86SWang Xiaoyin #interrupt-cells = <2>; 650d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 651d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 652d94eab86SWang Xiaoyin }; 653d94eab86SWang Xiaoyin 654d94eab86SWang Xiaoyin gpio8: gpio@e8a13000 { 655d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 656d94eab86SWang Xiaoyin reg = <0 0xe8a13000 0 0x1000>; 657d94eab86SWang Xiaoyin interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 658d94eab86SWang Xiaoyin gpio-controller; 659d94eab86SWang Xiaoyin #gpio-cells = <2>; 660d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 62 8>; 661d94eab86SWang Xiaoyin interrupt-controller; 662d94eab86SWang Xiaoyin #interrupt-cells = <2>; 663d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 664d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 665d94eab86SWang Xiaoyin }; 666d94eab86SWang Xiaoyin 667d94eab86SWang Xiaoyin gpio9: gpio@e8a14000 { 668d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 669d94eab86SWang Xiaoyin reg = <0 0xe8a14000 0 0x1000>; 670d94eab86SWang Xiaoyin interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 671d94eab86SWang Xiaoyin gpio-controller; 672d94eab86SWang Xiaoyin #gpio-cells = <2>; 673d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 70 8>; 674d94eab86SWang Xiaoyin interrupt-controller; 675d94eab86SWang Xiaoyin #interrupt-cells = <2>; 676d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 677d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 678d94eab86SWang Xiaoyin }; 679d94eab86SWang Xiaoyin 680d94eab86SWang Xiaoyin gpio10: gpio@e8a15000 { 681d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 682d94eab86SWang Xiaoyin reg = <0 0xe8a15000 0 0x1000>; 683d94eab86SWang Xiaoyin interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 684d94eab86SWang Xiaoyin gpio-controller; 685d94eab86SWang Xiaoyin #gpio-cells = <2>; 686d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 78 8>; 687d94eab86SWang Xiaoyin interrupt-controller; 688d94eab86SWang Xiaoyin #interrupt-cells = <2>; 689d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 690d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 691d94eab86SWang Xiaoyin }; 692d94eab86SWang Xiaoyin 693d94eab86SWang Xiaoyin gpio11: gpio@e8a16000 { 694d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 695d94eab86SWang Xiaoyin reg = <0 0xe8a16000 0 0x1000>; 696d94eab86SWang Xiaoyin interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 697d94eab86SWang Xiaoyin gpio-controller; 698d94eab86SWang Xiaoyin #gpio-cells = <2>; 699d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 86 8>; 700d94eab86SWang Xiaoyin interrupt-controller; 701d94eab86SWang Xiaoyin #interrupt-cells = <2>; 702d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 703d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 704d94eab86SWang Xiaoyin }; 705d94eab86SWang Xiaoyin 706d94eab86SWang Xiaoyin gpio12: gpio@e8a17000 { 707d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 708d94eab86SWang Xiaoyin reg = <0 0xe8a17000 0 0x1000>; 709d94eab86SWang Xiaoyin interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 710d94eab86SWang Xiaoyin gpio-controller; 711d94eab86SWang Xiaoyin #gpio-cells = <2>; 712d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 713d94eab86SWang Xiaoyin interrupt-controller; 714d94eab86SWang Xiaoyin #interrupt-cells = <2>; 715d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 716d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 717d94eab86SWang Xiaoyin }; 718d94eab86SWang Xiaoyin 719d94eab86SWang Xiaoyin gpio13: gpio@e8a18000 { 720d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 721d94eab86SWang Xiaoyin reg = <0 0xe8a18000 0 0x1000>; 722d94eab86SWang Xiaoyin interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 723d94eab86SWang Xiaoyin gpio-controller; 724d94eab86SWang Xiaoyin #gpio-cells = <2>; 725d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 102 8>; 726d94eab86SWang Xiaoyin interrupt-controller; 727d94eab86SWang Xiaoyin #interrupt-cells = <2>; 728d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 729d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 730d94eab86SWang Xiaoyin }; 731d94eab86SWang Xiaoyin 732d94eab86SWang Xiaoyin gpio14: gpio@e8a19000 { 733d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 734d94eab86SWang Xiaoyin reg = <0 0xe8a19000 0 0x1000>; 735d94eab86SWang Xiaoyin interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 736d94eab86SWang Xiaoyin gpio-controller; 737d94eab86SWang Xiaoyin #gpio-cells = <2>; 738d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 110 8>; 739d94eab86SWang Xiaoyin interrupt-controller; 740d94eab86SWang Xiaoyin #interrupt-cells = <2>; 741d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 742d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 743d94eab86SWang Xiaoyin }; 744d94eab86SWang Xiaoyin 745d94eab86SWang Xiaoyin gpio15: gpio@e8a1a000 { 746d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 747d94eab86SWang Xiaoyin reg = <0 0xe8a1a000 0 0x1000>; 748d94eab86SWang Xiaoyin interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 749d94eab86SWang Xiaoyin gpio-controller; 750d94eab86SWang Xiaoyin #gpio-cells = <2>; 751d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 118 6>; 752d94eab86SWang Xiaoyin interrupt-controller; 753d94eab86SWang Xiaoyin #interrupt-cells = <2>; 754d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 755d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 756d94eab86SWang Xiaoyin }; 757d94eab86SWang Xiaoyin 758d94eab86SWang Xiaoyin gpio16: gpio@e8a1b000 { 759d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 760d94eab86SWang Xiaoyin reg = <0 0xe8a1b000 0 0x1000>; 761d94eab86SWang Xiaoyin interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 762d94eab86SWang Xiaoyin gpio-controller; 763d94eab86SWang Xiaoyin #gpio-cells = <2>; 764d94eab86SWang Xiaoyin interrupt-controller; 765d94eab86SWang Xiaoyin #interrupt-cells = <2>; 766d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 767d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 768d94eab86SWang Xiaoyin }; 769d94eab86SWang Xiaoyin 770d94eab86SWang Xiaoyin gpio17: gpio@e8a1c000 { 771d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 772d94eab86SWang Xiaoyin reg = <0 0xe8a1c000 0 0x1000>; 773d94eab86SWang Xiaoyin interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 774d94eab86SWang Xiaoyin gpio-controller; 775d94eab86SWang Xiaoyin #gpio-cells = <2>; 776d94eab86SWang Xiaoyin interrupt-controller; 777d94eab86SWang Xiaoyin #interrupt-cells = <2>; 778d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 779d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 780d94eab86SWang Xiaoyin }; 781d94eab86SWang Xiaoyin 782d94eab86SWang Xiaoyin gpio18: gpio@ff3b4000 { 783d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 784d94eab86SWang Xiaoyin reg = <0 0xff3b4000 0 0x1000>; 785d94eab86SWang Xiaoyin interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 786d94eab86SWang Xiaoyin gpio-controller; 787d94eab86SWang Xiaoyin #gpio-cells = <2>; 788d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 0 8>; 789d94eab86SWang Xiaoyin interrupt-controller; 790d94eab86SWang Xiaoyin #interrupt-cells = <2>; 791d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 792d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 793d94eab86SWang Xiaoyin }; 794d94eab86SWang Xiaoyin 795d94eab86SWang Xiaoyin gpio19: gpio@ff3b5000 { 796d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 797d94eab86SWang Xiaoyin reg = <0 0xff3b5000 0 0x1000>; 798d94eab86SWang Xiaoyin interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 799d94eab86SWang Xiaoyin gpio-controller; 800d94eab86SWang Xiaoyin #gpio-cells = <2>; 801d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 8 4>; 802d94eab86SWang Xiaoyin interrupt-controller; 803d94eab86SWang Xiaoyin #interrupt-cells = <2>; 804d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 805d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 806d94eab86SWang Xiaoyin }; 807d94eab86SWang Xiaoyin 808d94eab86SWang Xiaoyin gpio20: gpio@e8a1f000 { 809d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 810d94eab86SWang Xiaoyin reg = <0 0xe8a1f000 0 0x1000>; 811d94eab86SWang Xiaoyin interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 812d94eab86SWang Xiaoyin gpio-controller; 813d94eab86SWang Xiaoyin #gpio-cells = <2>; 814d94eab86SWang Xiaoyin gpio-ranges = <&pmx1 0 0 6>; 815d94eab86SWang Xiaoyin interrupt-controller; 816d94eab86SWang Xiaoyin #interrupt-cells = <2>; 817d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 818d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 819d94eab86SWang Xiaoyin }; 820d94eab86SWang Xiaoyin 821d94eab86SWang Xiaoyin gpio21: gpio@e8a20000 { 822d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 823d94eab86SWang Xiaoyin reg = <0 0xe8a20000 0 0x1000>; 824d94eab86SWang Xiaoyin interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 825d94eab86SWang Xiaoyin gpio-controller; 826d94eab86SWang Xiaoyin #gpio-cells = <2>; 827d94eab86SWang Xiaoyin interrupt-controller; 828d94eab86SWang Xiaoyin #interrupt-cells = <2>; 829d94eab86SWang Xiaoyin gpio-ranges = <&pmx3 0 0 6>; 830d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 831d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 832d94eab86SWang Xiaoyin }; 833d94eab86SWang Xiaoyin 834d94eab86SWang Xiaoyin gpio22: gpio@fff0b000 { 835d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 836d94eab86SWang Xiaoyin reg = <0 0xfff0b000 0 0x1000>; 837d94eab86SWang Xiaoyin interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 838d94eab86SWang Xiaoyin gpio-controller; 839d94eab86SWang Xiaoyin #gpio-cells = <2>; 840d94eab86SWang Xiaoyin /* GPIO176 */ 841d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 2 0 6>; 842d94eab86SWang Xiaoyin interrupt-controller; 843d94eab86SWang Xiaoyin #interrupt-cells = <2>; 844d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 845d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 846d94eab86SWang Xiaoyin }; 847d94eab86SWang Xiaoyin 848d94eab86SWang Xiaoyin gpio23: gpio@fff0c000 { 849d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 850d94eab86SWang Xiaoyin reg = <0 0xfff0c000 0 0x1000>; 851d94eab86SWang Xiaoyin interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 852d94eab86SWang Xiaoyin gpio-controller; 853d94eab86SWang Xiaoyin #gpio-cells = <2>; 854d94eab86SWang Xiaoyin /* GPIO184 */ 855d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 6 7>; 856d94eab86SWang Xiaoyin interrupt-controller; 857d94eab86SWang Xiaoyin #interrupt-cells = <2>; 858d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 859d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 860d94eab86SWang Xiaoyin }; 861d94eab86SWang Xiaoyin 862d94eab86SWang Xiaoyin gpio24: gpio@fff0d000 { 863d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 864d94eab86SWang Xiaoyin reg = <0 0xfff0d000 0 0x1000>; 865d94eab86SWang Xiaoyin interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 866d94eab86SWang Xiaoyin gpio-controller; 867d94eab86SWang Xiaoyin #gpio-cells = <2>; 868d94eab86SWang Xiaoyin /* GPIO192 */ 869d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 13 8>; 870d94eab86SWang Xiaoyin interrupt-controller; 871d94eab86SWang Xiaoyin #interrupt-cells = <2>; 872d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 873d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 874d94eab86SWang Xiaoyin }; 875d94eab86SWang Xiaoyin 876d94eab86SWang Xiaoyin gpio25: gpio@fff0e000 { 877d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 878d94eab86SWang Xiaoyin reg = <0 0xfff0e000 0 0x1000>; 879d94eab86SWang Xiaoyin interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 880d94eab86SWang Xiaoyin gpio-controller; 881d94eab86SWang Xiaoyin #gpio-cells = <2>; 882d94eab86SWang Xiaoyin /* GPIO200 */ 883d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 884d94eab86SWang Xiaoyin interrupt-controller; 885d94eab86SWang Xiaoyin #interrupt-cells = <2>; 886d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 887d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 888d94eab86SWang Xiaoyin }; 889d94eab86SWang Xiaoyin 890d94eab86SWang Xiaoyin gpio26: gpio@fff0f000 { 891d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 892d94eab86SWang Xiaoyin reg = <0 0xfff0f000 0 0x1000>; 893d94eab86SWang Xiaoyin interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 894d94eab86SWang Xiaoyin gpio-controller; 895d94eab86SWang Xiaoyin #gpio-cells = <2>; 896d94eab86SWang Xiaoyin /* GPIO208 */ 897d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 28 8>; 898d94eab86SWang Xiaoyin interrupt-controller; 899d94eab86SWang Xiaoyin #interrupt-cells = <2>; 900d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 901d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 902d94eab86SWang Xiaoyin }; 903d94eab86SWang Xiaoyin 904d94eab86SWang Xiaoyin gpio27: gpio@fff10000 { 905d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 906d94eab86SWang Xiaoyin reg = <0 0xfff10000 0 0x1000>; 907d94eab86SWang Xiaoyin interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 908d94eab86SWang Xiaoyin gpio-controller; 909d94eab86SWang Xiaoyin #gpio-cells = <2>; 910d94eab86SWang Xiaoyin /* GPIO216 */ 911d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 36 6>; 912d94eab86SWang Xiaoyin interrupt-controller; 913d94eab86SWang Xiaoyin #interrupt-cells = <2>; 914d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 915d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 916d94eab86SWang Xiaoyin }; 917d94eab86SWang Xiaoyin 918d94eab86SWang Xiaoyin gpio28: gpio@fff1d000 { 919d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 920d94eab86SWang Xiaoyin reg = <0 0xfff1d000 0 0x1000>; 921d94eab86SWang Xiaoyin interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 922d94eab86SWang Xiaoyin gpio-controller; 923d94eab86SWang Xiaoyin #gpio-cells = <2>; 924d94eab86SWang Xiaoyin interrupt-controller; 925d94eab86SWang Xiaoyin #interrupt-cells = <2>; 926d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 927d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 928d94eab86SWang Xiaoyin }; 92938810497SWang Xiaoyin 93038810497SWang Xiaoyin spi2: spi@ffd68000 { 93138810497SWang Xiaoyin compatible = "arm,pl022", "arm,primecell"; 93238810497SWang Xiaoyin reg = <0x0 0xffd68000 0x0 0x1000>; 93338810497SWang Xiaoyin #address-cells = <1>; 93438810497SWang Xiaoyin #size-cells = <0>; 93538810497SWang Xiaoyin interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 93638810497SWang Xiaoyin clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; 93738810497SWang Xiaoyin clock-names = "apb_pclk"; 93838810497SWang Xiaoyin pinctrl-names = "default"; 93938810497SWang Xiaoyin pinctrl-0 = <&spi2_pmx_func>; 94038810497SWang Xiaoyin num-cs = <1>; 94138810497SWang Xiaoyin cs-gpios = <&gpio27 2 0>; 94238810497SWang Xiaoyin status = "disabled"; 94338810497SWang Xiaoyin }; 94438810497SWang Xiaoyin 94538810497SWang Xiaoyin spi3: spi@ff3b3000 { 94638810497SWang Xiaoyin compatible = "arm,pl022", "arm,primecell"; 94738810497SWang Xiaoyin reg = <0x0 0xff3b3000 0x0 0x1000>; 94838810497SWang Xiaoyin #address-cells = <1>; 94938810497SWang Xiaoyin #size-cells = <0>; 95038810497SWang Xiaoyin interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 95138810497SWang Xiaoyin clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; 95238810497SWang Xiaoyin clock-names = "apb_pclk"; 95338810497SWang Xiaoyin pinctrl-names = "default"; 95438810497SWang Xiaoyin pinctrl-0 = <&spi3_pmx_func>; 95538810497SWang Xiaoyin num-cs = <1>; 95638810497SWang Xiaoyin cs-gpios = <&gpio18 5 0>; 95738810497SWang Xiaoyin status = "disabled"; 95838810497SWang Xiaoyin }; 95996909778SXiaowei Song 96096909778SXiaowei Song pcie@f4000000 { 96196909778SXiaowei Song compatible = "hisilicon,kirin960-pcie"; 96296909778SXiaowei Song reg = <0x0 0xf4000000 0x0 0x1000>, 96396909778SXiaowei Song <0x0 0xff3fe000 0x0 0x1000>, 96496909778SXiaowei Song <0x0 0xf3f20000 0x0 0x40000>, 96596909778SXiaowei Song <0x0 0xf5000000 0x0 0x2000>; 96696909778SXiaowei Song reg-names = "dbi", "apb", "phy", "config"; 96796909778SXiaowei Song bus-range = <0x0 0x1>; 96896909778SXiaowei Song #address-cells = <3>; 96996909778SXiaowei Song #size-cells = <2>; 97096909778SXiaowei Song device_type = "pci"; 97196909778SXiaowei Song ranges = <0x02000000 0x0 0x00000000 97296909778SXiaowei Song 0x0 0xf6000000 97396909778SXiaowei Song 0x0 0x02000000>; 97496909778SXiaowei Song num-lanes = <1>; 97596909778SXiaowei Song #interrupt-cells = <1>; 97696909778SXiaowei Song interrupt-map-mask = <0xf800 0 0 7>; 97796909778SXiaowei Song interrupt-map = <0x0 0 0 1 97896909778SXiaowei Song &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 97996909778SXiaowei Song <0x0 0 0 2 98096909778SXiaowei Song &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 98196909778SXiaowei Song <0x0 0 0 3 98296909778SXiaowei Song &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 98396909778SXiaowei Song <0x0 0 0 4 98496909778SXiaowei Song &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 98596909778SXiaowei Song clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 98696909778SXiaowei Song <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 98796909778SXiaowei Song <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 98896909778SXiaowei Song <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 98996909778SXiaowei Song <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 99096909778SXiaowei Song clock-names = "pcie_phy_ref", "pcie_aux", 99196909778SXiaowei Song "pcie_apb_phy", "pcie_apb_sys", 99296909778SXiaowei Song "pcie_aclk"; 99396909778SXiaowei Song reset-gpios = <&gpio11 1 0 >; 99496909778SXiaowei Song }; 995804d7d7aSLi Wei 996804d7d7aSLi Wei /* SD */ 997804d7d7aSLi Wei dwmmc1: dwmmc1@ff37f000 { 998804d7d7aSLi Wei #address-cells = <1>; 999804d7d7aSLi Wei #size-cells = <0>; 1000804d7d7aSLi Wei cd-inverted; 1001804d7d7aSLi Wei compatible = "hisilicon,hi3660-dw-mshc"; 1002804d7d7aSLi Wei bus-width = <0x4>; 1003804d7d7aSLi Wei disable-wp; 1004804d7d7aSLi Wei cap-sd-highspeed; 1005804d7d7aSLi Wei supports-highspeed; 1006804d7d7aSLi Wei card-detect-delay = <200>; 1007804d7d7aSLi Wei reg = <0x0 0xff37f000 0x0 0x1000>; 1008804d7d7aSLi Wei interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1009804d7d7aSLi Wei clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, 1010804d7d7aSLi Wei <&crg_ctrl HI3660_HCLK_GATE_SD>; 1011804d7d7aSLi Wei clock-names = "ciu", "biu"; 1012804d7d7aSLi Wei clock-frequency = <3200000>; 1013804d7d7aSLi Wei resets = <&crg_rst 0x94 18>; 1014996707d7SGuodong Xu reset-names = "reset"; 1015804d7d7aSLi Wei cd-gpios = <&gpio25 3 0>; 1016804d7d7aSLi Wei hisilicon,peripheral-syscon = <&sctrl>; 1017804d7d7aSLi Wei pinctrl-names = "default"; 1018804d7d7aSLi Wei pinctrl-0 = <&sd_pmx_func 1019804d7d7aSLi Wei &sd_clk_cfg_func 1020804d7d7aSLi Wei &sd_cfg_func>; 1021804d7d7aSLi Wei sd-uhs-sdr12; 1022804d7d7aSLi Wei sd-uhs-sdr25; 1023804d7d7aSLi Wei sd-uhs-sdr50; 1024804d7d7aSLi Wei sd-uhs-sdr104; 1025804d7d7aSLi Wei status = "disabled"; 1026804d7d7aSLi Wei 1027804d7d7aSLi Wei slot@0 { 1028804d7d7aSLi Wei reg = <0x0>; 1029804d7d7aSLi Wei bus-width = <4>; 1030804d7d7aSLi Wei disable-wp; 1031804d7d7aSLi Wei }; 1032804d7d7aSLi Wei }; 1033804d7d7aSLi Wei 1034804d7d7aSLi Wei /* SDIO */ 1035804d7d7aSLi Wei dwmmc2: dwmmc2@ff3ff000 { 1036804d7d7aSLi Wei compatible = "hisilicon,hi3660-dw-mshc"; 1037804d7d7aSLi Wei reg = <0x0 0xff3ff000 0x0 0x1000>; 1038804d7d7aSLi Wei interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1039804d7d7aSLi Wei clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, 1040804d7d7aSLi Wei <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; 1041804d7d7aSLi Wei clock-names = "ciu", "biu"; 1042804d7d7aSLi Wei resets = <&crg_rst 0x94 20>; 1043996707d7SGuodong Xu reset-names = "reset"; 1044804d7d7aSLi Wei card-detect-delay = <200>; 1045804d7d7aSLi Wei supports-highspeed; 1046804d7d7aSLi Wei keep-power-in-suspend; 1047804d7d7aSLi Wei pinctrl-names = "default"; 1048804d7d7aSLi Wei pinctrl-0 = <&sdio_pmx_func 1049804d7d7aSLi Wei &sdio_clk_cfg_func 1050804d7d7aSLi Wei &sdio_cfg_func>; 1051804d7d7aSLi Wei status = "disabled"; 1052804d7d7aSLi Wei }; 1053487f00d4SLeo Yan 1054487f00d4SLeo Yan watchdog0: watchdog@e8a06000 { 1055487f00d4SLeo Yan compatible = "arm,sp805-wdt", "arm,primecell"; 1056487f00d4SLeo Yan reg = <0x0 0xe8a06000 0x0 0x1000>; 1057487f00d4SLeo Yan interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1058487f00d4SLeo Yan clocks = <&crg_ctrl HI3660_OSC32K>; 1059487f00d4SLeo Yan clock-names = "apb_pclk"; 1060487f00d4SLeo Yan }; 1061487f00d4SLeo Yan 1062487f00d4SLeo Yan watchdog1: watchdog@e8a07000 { 1063487f00d4SLeo Yan compatible = "arm,sp805-wdt", "arm,primecell"; 1064487f00d4SLeo Yan reg = <0x0 0xe8a07000 0x0 0x1000>; 1065487f00d4SLeo Yan interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1066487f00d4SLeo Yan clocks = <&crg_ctrl HI3660_OSC32K>; 1067487f00d4SLeo Yan clock-names = "apb_pclk"; 1068487f00d4SLeo Yan }; 1069a7ab4cb4SKevin Wangtao 1070a7ab4cb4SKevin Wangtao tsensor: tsensor@fff30000 { 1071a7ab4cb4SKevin Wangtao compatible = "hisilicon,hi3660-tsensor"; 1072a7ab4cb4SKevin Wangtao reg = <0x0 0xfff30000 0x0 0x1000>; 1073a7ab4cb4SKevin Wangtao interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 1074a7ab4cb4SKevin Wangtao #thermal-sensor-cells = <1>; 1075a7ab4cb4SKevin Wangtao }; 107635ca8168SChen Feng }; 107735ca8168SChen Feng}; 1078