135ca8168SChen Feng/* 235ca8168SChen Feng * dts file for Hisilicon Hi3660 SoC 335ca8168SChen Feng * 435ca8168SChen Feng * Copyright (C) 2016, Hisilicon Ltd. 535ca8168SChen Feng */ 635ca8168SChen Feng 735ca8168SChen Feng#include <dt-bindings/interrupt-controller/arm-gic.h> 8a4e36ae0SZhangfei Gao#include <dt-bindings/clock/hi3660-clock.h> 935ca8168SChen Feng 1035ca8168SChen Feng/ { 1135ca8168SChen Feng compatible = "hisilicon,hi3660"; 1235ca8168SChen Feng interrupt-parent = <&gic>; 1335ca8168SChen Feng #address-cells = <2>; 1435ca8168SChen Feng #size-cells = <2>; 1535ca8168SChen Feng 1635ca8168SChen Feng psci { 1735ca8168SChen Feng compatible = "arm,psci-0.2"; 1835ca8168SChen Feng method = "smc"; 1935ca8168SChen Feng }; 2035ca8168SChen Feng 2135ca8168SChen Feng cpus { 2235ca8168SChen Feng #address-cells = <2>; 2335ca8168SChen Feng #size-cells = <0>; 2435ca8168SChen Feng 2535ca8168SChen Feng cpu-map { 2635ca8168SChen Feng cluster0 { 2735ca8168SChen Feng core0 { 2835ca8168SChen Feng cpu = <&cpu0>; 2935ca8168SChen Feng }; 3035ca8168SChen Feng core1 { 3135ca8168SChen Feng cpu = <&cpu1>; 3235ca8168SChen Feng }; 3335ca8168SChen Feng core2 { 3435ca8168SChen Feng cpu = <&cpu2>; 3535ca8168SChen Feng }; 3635ca8168SChen Feng core3 { 3735ca8168SChen Feng cpu = <&cpu3>; 3835ca8168SChen Feng }; 3935ca8168SChen Feng }; 4035ca8168SChen Feng cluster1 { 4135ca8168SChen Feng core0 { 4235ca8168SChen Feng cpu = <&cpu4>; 4335ca8168SChen Feng }; 4435ca8168SChen Feng core1 { 4535ca8168SChen Feng cpu = <&cpu5>; 4635ca8168SChen Feng }; 4735ca8168SChen Feng core2 { 4835ca8168SChen Feng cpu = <&cpu6>; 4935ca8168SChen Feng }; 5035ca8168SChen Feng core3 { 5135ca8168SChen Feng cpu = <&cpu7>; 5235ca8168SChen Feng }; 5335ca8168SChen Feng }; 5435ca8168SChen Feng }; 5535ca8168SChen Feng 5635ca8168SChen Feng cpu0: cpu@0 { 5735ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 5835ca8168SChen Feng device_type = "cpu"; 5935ca8168SChen Feng reg = <0x0 0x0>; 6035ca8168SChen Feng enable-method = "psci"; 6135ca8168SChen Feng }; 6235ca8168SChen Feng 6335ca8168SChen Feng cpu1: cpu@1 { 6435ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 6535ca8168SChen Feng device_type = "cpu"; 6635ca8168SChen Feng reg = <0x0 0x1>; 6735ca8168SChen Feng enable-method = "psci"; 6835ca8168SChen Feng }; 6935ca8168SChen Feng 7035ca8168SChen Feng cpu2: cpu@2 { 7135ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 7235ca8168SChen Feng device_type = "cpu"; 7335ca8168SChen Feng reg = <0x0 0x2>; 7435ca8168SChen Feng enable-method = "psci"; 7535ca8168SChen Feng }; 7635ca8168SChen Feng 7735ca8168SChen Feng cpu3: cpu@3 { 7835ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 7935ca8168SChen Feng device_type = "cpu"; 8035ca8168SChen Feng reg = <0x0 0x3>; 8135ca8168SChen Feng enable-method = "psci"; 8235ca8168SChen Feng }; 8335ca8168SChen Feng 8435ca8168SChen Feng cpu4: cpu@100 { 8535ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 8635ca8168SChen Feng device_type = "cpu"; 8735ca8168SChen Feng reg = <0x0 0x100>; 8835ca8168SChen Feng enable-method = "psci"; 8935ca8168SChen Feng }; 9035ca8168SChen Feng 9135ca8168SChen Feng cpu5: cpu@101 { 9235ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 9335ca8168SChen Feng device_type = "cpu"; 9435ca8168SChen Feng reg = <0x0 0x101>; 9535ca8168SChen Feng enable-method = "psci"; 9635ca8168SChen Feng }; 9735ca8168SChen Feng 9835ca8168SChen Feng cpu6: cpu@102 { 9935ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 10035ca8168SChen Feng device_type = "cpu"; 10135ca8168SChen Feng reg = <0x0 0x102>; 10235ca8168SChen Feng enable-method = "psci"; 10335ca8168SChen Feng }; 10435ca8168SChen Feng 10535ca8168SChen Feng cpu7: cpu@103 { 10635ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 10735ca8168SChen Feng device_type = "cpu"; 10835ca8168SChen Feng reg = <0x0 0x103>; 10935ca8168SChen Feng enable-method = "psci"; 11035ca8168SChen Feng }; 11135ca8168SChen Feng }; 11235ca8168SChen Feng 11335ca8168SChen Feng gic: interrupt-controller@e82b0000 { 11435ca8168SChen Feng compatible = "arm,gic-400"; 11535ca8168SChen Feng reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 11635ca8168SChen Feng <0x0 0xe82b2000 0 0x2000>, /* GICC */ 11735ca8168SChen Feng <0x0 0xe82b4000 0 0x2000>, /* GICH */ 11835ca8168SChen Feng <0x0 0xe82b6000 0 0x2000>; /* GICV */ 11935ca8168SChen Feng #address-cells = <0>; 12035ca8168SChen Feng #interrupt-cells = <3>; 12135ca8168SChen Feng interrupt-controller; 12235ca8168SChen Feng interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 12335ca8168SChen Feng IRQ_TYPE_LEVEL_HIGH)>; 12435ca8168SChen Feng }; 12535ca8168SChen Feng 12635ca8168SChen Feng timer { 12735ca8168SChen Feng compatible = "arm,armv8-timer"; 12835ca8168SChen Feng interrupt-parent = <&gic>; 12935ca8168SChen Feng interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 13035ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 13135ca8168SChen Feng <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 13235ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 13335ca8168SChen Feng <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 13435ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 13535ca8168SChen Feng <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 13635ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>; 13735ca8168SChen Feng }; 13835ca8168SChen Feng 13935ca8168SChen Feng soc { 14035ca8168SChen Feng compatible = "simple-bus"; 14135ca8168SChen Feng #address-cells = <2>; 14235ca8168SChen Feng #size-cells = <2>; 14335ca8168SChen Feng ranges; 14435ca8168SChen Feng 145a4e36ae0SZhangfei Gao crg_ctrl: crg_ctrl@fff35000 { 146a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-crgctrl", "syscon"; 147a4e36ae0SZhangfei Gao reg = <0x0 0xfff35000 0x0 0x1000>; 148a4e36ae0SZhangfei Gao #clock-cells = <1>; 14935ca8168SChen Feng }; 15035ca8168SChen Feng 151a4e36ae0SZhangfei Gao crg_rst: crg_rst_controller { 152a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 153a4e36ae0SZhangfei Gao #reset-cells = <2>; 154a4e36ae0SZhangfei Gao hisi,rst-syscon = <&crg_ctrl>; 155a4e36ae0SZhangfei Gao }; 156a4e36ae0SZhangfei Gao 157a4e36ae0SZhangfei Gao 158a4e36ae0SZhangfei Gao pctrl: pctrl@e8a09000 { 159a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pctrl", "syscon"; 160a4e36ae0SZhangfei Gao reg = <0x0 0xe8a09000 0x0 0x2000>; 161a4e36ae0SZhangfei Gao #clock-cells = <1>; 162a4e36ae0SZhangfei Gao }; 163a4e36ae0SZhangfei Gao 164a4e36ae0SZhangfei Gao pmuctrl: crg_ctrl@fff34000 { 165a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 166a4e36ae0SZhangfei Gao reg = <0x0 0xfff34000 0x0 0x1000>; 167a4e36ae0SZhangfei Gao #clock-cells = <1>; 168a4e36ae0SZhangfei Gao }; 169a4e36ae0SZhangfei Gao 170a4e36ae0SZhangfei Gao sctrl: sctrl@fff0a000 { 171a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-sctrl", "syscon"; 172a4e36ae0SZhangfei Gao reg = <0x0 0xfff0a000 0x0 0x1000>; 173a4e36ae0SZhangfei Gao #clock-cells = <1>; 174a4e36ae0SZhangfei Gao }; 175a4e36ae0SZhangfei Gao 176a4e36ae0SZhangfei Gao iomcu: iomcu@ffd7e000 { 177a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-iomcu", "syscon"; 178a4e36ae0SZhangfei Gao reg = <0x0 0xffd7e000 0x0 0x1000>; 179a4e36ae0SZhangfei Gao #clock-cells = <1>; 180a4e36ae0SZhangfei Gao 181a4e36ae0SZhangfei Gao }; 182a4e36ae0SZhangfei Gao 183a4e36ae0SZhangfei Gao iomcu_rst: reset { 184a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 185a4e36ae0SZhangfei Gao hisi,rst-syscon = <&iomcu>; 186a4e36ae0SZhangfei Gao #reset-cells = <2>; 187a4e36ae0SZhangfei Gao }; 188a4e36ae0SZhangfei Gao 1895f8a3b77SZhangfei Gao i2c0: i2c@ffd71000 { 1905f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 1915f8a3b77SZhangfei Gao reg = <0x0 0xffd71000 0x0 0x1000>; 1925f8a3b77SZhangfei Gao interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1935f8a3b77SZhangfei Gao #address-cells = <1>; 1945f8a3b77SZhangfei Gao #size-cells = <0>; 1955f8a3b77SZhangfei Gao clock-frequency = <400000>; 1965f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 1975f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 3>; 1985f8a3b77SZhangfei Gao pinctrl-names = "default"; 1995f8a3b77SZhangfei Gao pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 2005f8a3b77SZhangfei Gao status = "disabled"; 2015f8a3b77SZhangfei Gao }; 2025f8a3b77SZhangfei Gao 2035f8a3b77SZhangfei Gao i2c1: i2c@ffd72000 { 2045f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 2055f8a3b77SZhangfei Gao reg = <0x0 0xffd72000 0x0 0x1000>; 2065f8a3b77SZhangfei Gao interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2075f8a3b77SZhangfei Gao #address-cells = <1>; 2085f8a3b77SZhangfei Gao #size-cells = <0>; 2095f8a3b77SZhangfei Gao clock-frequency = <400000>; 2105f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 2115f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 4>; 2125f8a3b77SZhangfei Gao pinctrl-names = "default"; 2135f8a3b77SZhangfei Gao pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 2145f8a3b77SZhangfei Gao status = "disabled"; 2155f8a3b77SZhangfei Gao }; 2165f8a3b77SZhangfei Gao 2175f8a3b77SZhangfei Gao i2c3: i2c@fdf0c000 { 2185f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 2195f8a3b77SZhangfei Gao reg = <0x0 0xfdf0c000 0x0 0x1000>; 2205f8a3b77SZhangfei Gao interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2215f8a3b77SZhangfei Gao #address-cells = <1>; 2225f8a3b77SZhangfei Gao #size-cells = <0>; 2235f8a3b77SZhangfei Gao clock-frequency = <400000>; 2245f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 2255f8a3b77SZhangfei Gao resets = <&crg_rst 0x78 7>; 2265f8a3b77SZhangfei Gao pinctrl-names = "default"; 2275f8a3b77SZhangfei Gao pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 2285f8a3b77SZhangfei Gao status = "disabled"; 2295f8a3b77SZhangfei Gao }; 2305f8a3b77SZhangfei Gao 2315f8a3b77SZhangfei Gao i2c7: i2c@fdf0b000 { 2325f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 2335f8a3b77SZhangfei Gao reg = <0x0 0xfdf0b000 0x0 0x1000>; 2345f8a3b77SZhangfei Gao interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 2355f8a3b77SZhangfei Gao #address-cells = <1>; 2365f8a3b77SZhangfei Gao #size-cells = <0>; 2375f8a3b77SZhangfei Gao clock-frequency = <400000>; 2385f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 2395f8a3b77SZhangfei Gao resets = <&crg_rst 0x60 14>; 2405f8a3b77SZhangfei Gao pinctrl-names = "default"; 2415f8a3b77SZhangfei Gao pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 2425f8a3b77SZhangfei Gao status = "disabled"; 2435f8a3b77SZhangfei Gao }; 2445f8a3b77SZhangfei Gao 245a4e36ae0SZhangfei Gao uart5: serial@fdf05000 { 24635ca8168SChen Feng compatible = "arm,pl011", "arm,primecell"; 24735ca8168SChen Feng reg = <0x0 0xfdf05000 0x0 0x1000>; 24835ca8168SChen Feng interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 249a4e36ae0SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 250a4e36ae0SZhangfei Gao <&crg_ctrl HI3660_CLK_GATE_UART5>; 25135ca8168SChen Feng clock-names = "uartclk", "apb_pclk"; 25235ca8168SChen Feng status = "disabled"; 25335ca8168SChen Feng }; 254d94eab86SWang Xiaoyin 255d94eab86SWang Xiaoyin gpio0: gpio@e8a0b000 { 256d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 257d94eab86SWang Xiaoyin reg = <0 0xe8a0b000 0 0x1000>; 258d94eab86SWang Xiaoyin interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 259d94eab86SWang Xiaoyin gpio-controller; 260d94eab86SWang Xiaoyin #gpio-cells = <2>; 261d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 0 7>; 262d94eab86SWang Xiaoyin interrupt-controller; 263d94eab86SWang Xiaoyin #interrupt-cells = <2>; 264d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 265d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 266d94eab86SWang Xiaoyin }; 267d94eab86SWang Xiaoyin 268d94eab86SWang Xiaoyin gpio1: gpio@e8a0c000 { 269d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 270d94eab86SWang Xiaoyin reg = <0 0xe8a0c000 0 0x1000>; 271d94eab86SWang Xiaoyin interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 272d94eab86SWang Xiaoyin gpio-controller; 273d94eab86SWang Xiaoyin #gpio-cells = <2>; 274d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 7 7>; 275d94eab86SWang Xiaoyin interrupt-controller; 276d94eab86SWang Xiaoyin #interrupt-cells = <2>; 277d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 278d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 279d94eab86SWang Xiaoyin }; 280d94eab86SWang Xiaoyin 281d94eab86SWang Xiaoyin gpio2: gpio@e8a0d000 { 282d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 283d94eab86SWang Xiaoyin reg = <0 0xe8a0d000 0 0x1000>; 284d94eab86SWang Xiaoyin interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 285d94eab86SWang Xiaoyin gpio-controller; 286d94eab86SWang Xiaoyin #gpio-cells = <2>; 287d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 14 8>; 288d94eab86SWang Xiaoyin interrupt-controller; 289d94eab86SWang Xiaoyin #interrupt-cells = <2>; 290d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 291d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 292d94eab86SWang Xiaoyin }; 293d94eab86SWang Xiaoyin 294d94eab86SWang Xiaoyin gpio3: gpio@e8a0e000 { 295d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 296d94eab86SWang Xiaoyin reg = <0 0xe8a0e000 0 0x1000>; 297d94eab86SWang Xiaoyin interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 298d94eab86SWang Xiaoyin gpio-controller; 299d94eab86SWang Xiaoyin #gpio-cells = <2>; 300d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 22 8>; 301d94eab86SWang Xiaoyin interrupt-controller; 302d94eab86SWang Xiaoyin #interrupt-cells = <2>; 303d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 304d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 305d94eab86SWang Xiaoyin }; 306d94eab86SWang Xiaoyin 307d94eab86SWang Xiaoyin gpio4: gpio@e8a0f000 { 308d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 309d94eab86SWang Xiaoyin reg = <0 0xe8a0f000 0 0x1000>; 310d94eab86SWang Xiaoyin interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 311d94eab86SWang Xiaoyin gpio-controller; 312d94eab86SWang Xiaoyin #gpio-cells = <2>; 313d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 30 8>; 314d94eab86SWang Xiaoyin interrupt-controller; 315d94eab86SWang Xiaoyin #interrupt-cells = <2>; 316d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 317d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 318d94eab86SWang Xiaoyin }; 319d94eab86SWang Xiaoyin 320d94eab86SWang Xiaoyin gpio5: gpio@e8a10000 { 321d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 322d94eab86SWang Xiaoyin reg = <0 0xe8a10000 0 0x1000>; 323d94eab86SWang Xiaoyin interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 324d94eab86SWang Xiaoyin gpio-controller; 325d94eab86SWang Xiaoyin #gpio-cells = <2>; 326d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 38 8>; 327d94eab86SWang Xiaoyin interrupt-controller; 328d94eab86SWang Xiaoyin #interrupt-cells = <2>; 329d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 330d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 331d94eab86SWang Xiaoyin }; 332d94eab86SWang Xiaoyin 333d94eab86SWang Xiaoyin gpio6: gpio@e8a11000 { 334d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 335d94eab86SWang Xiaoyin reg = <0 0xe8a11000 0 0x1000>; 336d94eab86SWang Xiaoyin interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 337d94eab86SWang Xiaoyin gpio-controller; 338d94eab86SWang Xiaoyin #gpio-cells = <2>; 339d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 46 8>; 340d94eab86SWang Xiaoyin interrupt-controller; 341d94eab86SWang Xiaoyin #interrupt-cells = <2>; 342d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 343d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 344d94eab86SWang Xiaoyin }; 345d94eab86SWang Xiaoyin 346d94eab86SWang Xiaoyin gpio7: gpio@e8a12000 { 347d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 348d94eab86SWang Xiaoyin reg = <0 0xe8a12000 0 0x1000>; 349d94eab86SWang Xiaoyin interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 350d94eab86SWang Xiaoyin gpio-controller; 351d94eab86SWang Xiaoyin #gpio-cells = <2>; 352d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 54 8>; 353d94eab86SWang Xiaoyin interrupt-controller; 354d94eab86SWang Xiaoyin #interrupt-cells = <2>; 355d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 356d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 357d94eab86SWang Xiaoyin }; 358d94eab86SWang Xiaoyin 359d94eab86SWang Xiaoyin gpio8: gpio@e8a13000 { 360d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 361d94eab86SWang Xiaoyin reg = <0 0xe8a13000 0 0x1000>; 362d94eab86SWang Xiaoyin interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 363d94eab86SWang Xiaoyin gpio-controller; 364d94eab86SWang Xiaoyin #gpio-cells = <2>; 365d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 62 8>; 366d94eab86SWang Xiaoyin interrupt-controller; 367d94eab86SWang Xiaoyin #interrupt-cells = <2>; 368d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 369d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 370d94eab86SWang Xiaoyin }; 371d94eab86SWang Xiaoyin 372d94eab86SWang Xiaoyin gpio9: gpio@e8a14000 { 373d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 374d94eab86SWang Xiaoyin reg = <0 0xe8a14000 0 0x1000>; 375d94eab86SWang Xiaoyin interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 376d94eab86SWang Xiaoyin gpio-controller; 377d94eab86SWang Xiaoyin #gpio-cells = <2>; 378d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 70 8>; 379d94eab86SWang Xiaoyin interrupt-controller; 380d94eab86SWang Xiaoyin #interrupt-cells = <2>; 381d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 382d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 383d94eab86SWang Xiaoyin }; 384d94eab86SWang Xiaoyin 385d94eab86SWang Xiaoyin gpio10: gpio@e8a15000 { 386d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 387d94eab86SWang Xiaoyin reg = <0 0xe8a15000 0 0x1000>; 388d94eab86SWang Xiaoyin interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 389d94eab86SWang Xiaoyin gpio-controller; 390d94eab86SWang Xiaoyin #gpio-cells = <2>; 391d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 78 8>; 392d94eab86SWang Xiaoyin interrupt-controller; 393d94eab86SWang Xiaoyin #interrupt-cells = <2>; 394d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 395d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 396d94eab86SWang Xiaoyin }; 397d94eab86SWang Xiaoyin 398d94eab86SWang Xiaoyin gpio11: gpio@e8a16000 { 399d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 400d94eab86SWang Xiaoyin reg = <0 0xe8a16000 0 0x1000>; 401d94eab86SWang Xiaoyin interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 402d94eab86SWang Xiaoyin gpio-controller; 403d94eab86SWang Xiaoyin #gpio-cells = <2>; 404d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 86 8>; 405d94eab86SWang Xiaoyin interrupt-controller; 406d94eab86SWang Xiaoyin #interrupt-cells = <2>; 407d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 408d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 409d94eab86SWang Xiaoyin }; 410d94eab86SWang Xiaoyin 411d94eab86SWang Xiaoyin gpio12: gpio@e8a17000 { 412d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 413d94eab86SWang Xiaoyin reg = <0 0xe8a17000 0 0x1000>; 414d94eab86SWang Xiaoyin interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 415d94eab86SWang Xiaoyin gpio-controller; 416d94eab86SWang Xiaoyin #gpio-cells = <2>; 417d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 418d94eab86SWang Xiaoyin interrupt-controller; 419d94eab86SWang Xiaoyin #interrupt-cells = <2>; 420d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 421d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 422d94eab86SWang Xiaoyin }; 423d94eab86SWang Xiaoyin 424d94eab86SWang Xiaoyin gpio13: gpio@e8a18000 { 425d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 426d94eab86SWang Xiaoyin reg = <0 0xe8a18000 0 0x1000>; 427d94eab86SWang Xiaoyin interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 428d94eab86SWang Xiaoyin gpio-controller; 429d94eab86SWang Xiaoyin #gpio-cells = <2>; 430d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 102 8>; 431d94eab86SWang Xiaoyin interrupt-controller; 432d94eab86SWang Xiaoyin #interrupt-cells = <2>; 433d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 434d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 435d94eab86SWang Xiaoyin }; 436d94eab86SWang Xiaoyin 437d94eab86SWang Xiaoyin gpio14: gpio@e8a19000 { 438d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 439d94eab86SWang Xiaoyin reg = <0 0xe8a19000 0 0x1000>; 440d94eab86SWang Xiaoyin interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 441d94eab86SWang Xiaoyin gpio-controller; 442d94eab86SWang Xiaoyin #gpio-cells = <2>; 443d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 110 8>; 444d94eab86SWang Xiaoyin interrupt-controller; 445d94eab86SWang Xiaoyin #interrupt-cells = <2>; 446d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 447d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 448d94eab86SWang Xiaoyin }; 449d94eab86SWang Xiaoyin 450d94eab86SWang Xiaoyin gpio15: gpio@e8a1a000 { 451d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 452d94eab86SWang Xiaoyin reg = <0 0xe8a1a000 0 0x1000>; 453d94eab86SWang Xiaoyin interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 454d94eab86SWang Xiaoyin gpio-controller; 455d94eab86SWang Xiaoyin #gpio-cells = <2>; 456d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 118 6>; 457d94eab86SWang Xiaoyin interrupt-controller; 458d94eab86SWang Xiaoyin #interrupt-cells = <2>; 459d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 460d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 461d94eab86SWang Xiaoyin }; 462d94eab86SWang Xiaoyin 463d94eab86SWang Xiaoyin gpio16: gpio@e8a1b000 { 464d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 465d94eab86SWang Xiaoyin reg = <0 0xe8a1b000 0 0x1000>; 466d94eab86SWang Xiaoyin interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 467d94eab86SWang Xiaoyin gpio-controller; 468d94eab86SWang Xiaoyin #gpio-cells = <2>; 469d94eab86SWang Xiaoyin interrupt-controller; 470d94eab86SWang Xiaoyin #interrupt-cells = <2>; 471d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 472d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 473d94eab86SWang Xiaoyin }; 474d94eab86SWang Xiaoyin 475d94eab86SWang Xiaoyin gpio17: gpio@e8a1c000 { 476d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 477d94eab86SWang Xiaoyin reg = <0 0xe8a1c000 0 0x1000>; 478d94eab86SWang Xiaoyin interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 479d94eab86SWang Xiaoyin gpio-controller; 480d94eab86SWang Xiaoyin #gpio-cells = <2>; 481d94eab86SWang Xiaoyin interrupt-controller; 482d94eab86SWang Xiaoyin #interrupt-cells = <2>; 483d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 484d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 485d94eab86SWang Xiaoyin }; 486d94eab86SWang Xiaoyin 487d94eab86SWang Xiaoyin gpio18: gpio@ff3b4000 { 488d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 489d94eab86SWang Xiaoyin reg = <0 0xff3b4000 0 0x1000>; 490d94eab86SWang Xiaoyin interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 491d94eab86SWang Xiaoyin gpio-controller; 492d94eab86SWang Xiaoyin #gpio-cells = <2>; 493d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 0 8>; 494d94eab86SWang Xiaoyin interrupt-controller; 495d94eab86SWang Xiaoyin #interrupt-cells = <2>; 496d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 497d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 498d94eab86SWang Xiaoyin }; 499d94eab86SWang Xiaoyin 500d94eab86SWang Xiaoyin gpio19: gpio@ff3b5000 { 501d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 502d94eab86SWang Xiaoyin reg = <0 0xff3b5000 0 0x1000>; 503d94eab86SWang Xiaoyin interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 504d94eab86SWang Xiaoyin gpio-controller; 505d94eab86SWang Xiaoyin #gpio-cells = <2>; 506d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 8 4>; 507d94eab86SWang Xiaoyin interrupt-controller; 508d94eab86SWang Xiaoyin #interrupt-cells = <2>; 509d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 510d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 511d94eab86SWang Xiaoyin }; 512d94eab86SWang Xiaoyin 513d94eab86SWang Xiaoyin gpio20: gpio@e8a1f000 { 514d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 515d94eab86SWang Xiaoyin reg = <0 0xe8a1f000 0 0x1000>; 516d94eab86SWang Xiaoyin interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 517d94eab86SWang Xiaoyin gpio-controller; 518d94eab86SWang Xiaoyin #gpio-cells = <2>; 519d94eab86SWang Xiaoyin gpio-ranges = <&pmx1 0 0 6>; 520d94eab86SWang Xiaoyin interrupt-controller; 521d94eab86SWang Xiaoyin #interrupt-cells = <2>; 522d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 523d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 524d94eab86SWang Xiaoyin }; 525d94eab86SWang Xiaoyin 526d94eab86SWang Xiaoyin gpio21: gpio@e8a20000 { 527d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 528d94eab86SWang Xiaoyin reg = <0 0xe8a20000 0 0x1000>; 529d94eab86SWang Xiaoyin interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 530d94eab86SWang Xiaoyin gpio-controller; 531d94eab86SWang Xiaoyin #gpio-cells = <2>; 532d94eab86SWang Xiaoyin interrupt-controller; 533d94eab86SWang Xiaoyin #interrupt-cells = <2>; 534d94eab86SWang Xiaoyin gpio-ranges = <&pmx3 0 0 6>; 535d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 536d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 537d94eab86SWang Xiaoyin }; 538d94eab86SWang Xiaoyin 539d94eab86SWang Xiaoyin gpio22: gpio@fff0b000 { 540d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 541d94eab86SWang Xiaoyin reg = <0 0xfff0b000 0 0x1000>; 542d94eab86SWang Xiaoyin interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 543d94eab86SWang Xiaoyin gpio-controller; 544d94eab86SWang Xiaoyin #gpio-cells = <2>; 545d94eab86SWang Xiaoyin /* GPIO176 */ 546d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 2 0 6>; 547d94eab86SWang Xiaoyin interrupt-controller; 548d94eab86SWang Xiaoyin #interrupt-cells = <2>; 549d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 550d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 551d94eab86SWang Xiaoyin }; 552d94eab86SWang Xiaoyin 553d94eab86SWang Xiaoyin gpio23: gpio@fff0c000 { 554d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 555d94eab86SWang Xiaoyin reg = <0 0xfff0c000 0 0x1000>; 556d94eab86SWang Xiaoyin interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 557d94eab86SWang Xiaoyin gpio-controller; 558d94eab86SWang Xiaoyin #gpio-cells = <2>; 559d94eab86SWang Xiaoyin /* GPIO184 */ 560d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 6 7>; 561d94eab86SWang Xiaoyin interrupt-controller; 562d94eab86SWang Xiaoyin #interrupt-cells = <2>; 563d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 564d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 565d94eab86SWang Xiaoyin }; 566d94eab86SWang Xiaoyin 567d94eab86SWang Xiaoyin gpio24: gpio@fff0d000 { 568d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 569d94eab86SWang Xiaoyin reg = <0 0xfff0d000 0 0x1000>; 570d94eab86SWang Xiaoyin interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 571d94eab86SWang Xiaoyin gpio-controller; 572d94eab86SWang Xiaoyin #gpio-cells = <2>; 573d94eab86SWang Xiaoyin /* GPIO192 */ 574d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 13 8>; 575d94eab86SWang Xiaoyin interrupt-controller; 576d94eab86SWang Xiaoyin #interrupt-cells = <2>; 577d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 578d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 579d94eab86SWang Xiaoyin }; 580d94eab86SWang Xiaoyin 581d94eab86SWang Xiaoyin gpio25: gpio@fff0e000 { 582d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 583d94eab86SWang Xiaoyin reg = <0 0xfff0e000 0 0x1000>; 584d94eab86SWang Xiaoyin interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 585d94eab86SWang Xiaoyin gpio-controller; 586d94eab86SWang Xiaoyin #gpio-cells = <2>; 587d94eab86SWang Xiaoyin /* GPIO200 */ 588d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 589d94eab86SWang Xiaoyin interrupt-controller; 590d94eab86SWang Xiaoyin #interrupt-cells = <2>; 591d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 592d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 593d94eab86SWang Xiaoyin }; 594d94eab86SWang Xiaoyin 595d94eab86SWang Xiaoyin gpio26: gpio@fff0f000 { 596d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 597d94eab86SWang Xiaoyin reg = <0 0xfff0f000 0 0x1000>; 598d94eab86SWang Xiaoyin interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 599d94eab86SWang Xiaoyin gpio-controller; 600d94eab86SWang Xiaoyin #gpio-cells = <2>; 601d94eab86SWang Xiaoyin /* GPIO208 */ 602d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 28 8>; 603d94eab86SWang Xiaoyin interrupt-controller; 604d94eab86SWang Xiaoyin #interrupt-cells = <2>; 605d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 606d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 607d94eab86SWang Xiaoyin }; 608d94eab86SWang Xiaoyin 609d94eab86SWang Xiaoyin gpio27: gpio@fff10000 { 610d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 611d94eab86SWang Xiaoyin reg = <0 0xfff10000 0 0x1000>; 612d94eab86SWang Xiaoyin interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 613d94eab86SWang Xiaoyin gpio-controller; 614d94eab86SWang Xiaoyin #gpio-cells = <2>; 615d94eab86SWang Xiaoyin /* GPIO216 */ 616d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 36 6>; 617d94eab86SWang Xiaoyin interrupt-controller; 618d94eab86SWang Xiaoyin #interrupt-cells = <2>; 619d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 620d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 621d94eab86SWang Xiaoyin }; 622d94eab86SWang Xiaoyin 623d94eab86SWang Xiaoyin gpio28: gpio@fff1d000 { 624d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 625d94eab86SWang Xiaoyin reg = <0 0xfff1d000 0 0x1000>; 626d94eab86SWang Xiaoyin interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 627d94eab86SWang Xiaoyin gpio-controller; 628d94eab86SWang Xiaoyin #gpio-cells = <2>; 629d94eab86SWang Xiaoyin interrupt-controller; 630d94eab86SWang Xiaoyin #interrupt-cells = <2>; 631d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 632d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 633d94eab86SWang Xiaoyin }; 63435ca8168SChen Feng }; 63535ca8168SChen Feng}; 636