1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 235ca8168SChen Feng/* 335ca8168SChen Feng * dts file for Hisilicon Hi3660 SoC 435ca8168SChen Feng * 535ca8168SChen Feng * Copyright (C) 2016, Hisilicon Ltd. 635ca8168SChen Feng */ 735ca8168SChen Feng 835ca8168SChen Feng#include <dt-bindings/interrupt-controller/arm-gic.h> 9a4e36ae0SZhangfei Gao#include <dt-bindings/clock/hi3660-clock.h> 1035ca8168SChen Feng 1135ca8168SChen Feng/ { 1235ca8168SChen Feng compatible = "hisilicon,hi3660"; 1335ca8168SChen Feng interrupt-parent = <&gic>; 1435ca8168SChen Feng #address-cells = <2>; 1535ca8168SChen Feng #size-cells = <2>; 1635ca8168SChen Feng 1735ca8168SChen Feng psci { 1835ca8168SChen Feng compatible = "arm,psci-0.2"; 1935ca8168SChen Feng method = "smc"; 2035ca8168SChen Feng }; 2135ca8168SChen Feng 2235ca8168SChen Feng cpus { 2335ca8168SChen Feng #address-cells = <2>; 2435ca8168SChen Feng #size-cells = <0>; 2535ca8168SChen Feng 2635ca8168SChen Feng cpu-map { 2735ca8168SChen Feng cluster0 { 2835ca8168SChen Feng core0 { 2935ca8168SChen Feng cpu = <&cpu0>; 3035ca8168SChen Feng }; 3135ca8168SChen Feng core1 { 3235ca8168SChen Feng cpu = <&cpu1>; 3335ca8168SChen Feng }; 3435ca8168SChen Feng core2 { 3535ca8168SChen Feng cpu = <&cpu2>; 3635ca8168SChen Feng }; 3735ca8168SChen Feng core3 { 3835ca8168SChen Feng cpu = <&cpu3>; 3935ca8168SChen Feng }; 4035ca8168SChen Feng }; 4135ca8168SChen Feng cluster1 { 4235ca8168SChen Feng core0 { 4335ca8168SChen Feng cpu = <&cpu4>; 4435ca8168SChen Feng }; 4535ca8168SChen Feng core1 { 4635ca8168SChen Feng cpu = <&cpu5>; 4735ca8168SChen Feng }; 4835ca8168SChen Feng core2 { 4935ca8168SChen Feng cpu = <&cpu6>; 5035ca8168SChen Feng }; 5135ca8168SChen Feng core3 { 5235ca8168SChen Feng cpu = <&cpu7>; 5335ca8168SChen Feng }; 5435ca8168SChen Feng }; 5535ca8168SChen Feng }; 5635ca8168SChen Feng 5735ca8168SChen Feng cpu0: cpu@0 { 5835ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 5935ca8168SChen Feng device_type = "cpu"; 6035ca8168SChen Feng reg = <0x0 0x0>; 6135ca8168SChen Feng enable-method = "psci"; 62a6d08344SLeo Yan next-level-cache = <&A53_L2>; 6330fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 6435ca8168SChen Feng }; 6535ca8168SChen Feng 6635ca8168SChen Feng cpu1: cpu@1 { 6735ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 6835ca8168SChen Feng device_type = "cpu"; 6935ca8168SChen Feng reg = <0x0 0x1>; 7035ca8168SChen Feng enable-method = "psci"; 71a6d08344SLeo Yan next-level-cache = <&A53_L2>; 7230fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 7335ca8168SChen Feng }; 7435ca8168SChen Feng 7535ca8168SChen Feng cpu2: cpu@2 { 7635ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 7735ca8168SChen Feng device_type = "cpu"; 7835ca8168SChen Feng reg = <0x0 0x2>; 7935ca8168SChen Feng enable-method = "psci"; 80a6d08344SLeo Yan next-level-cache = <&A53_L2>; 8130fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 8235ca8168SChen Feng }; 8335ca8168SChen Feng 8435ca8168SChen Feng cpu3: cpu@3 { 8535ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 8635ca8168SChen Feng device_type = "cpu"; 8735ca8168SChen Feng reg = <0x0 0x3>; 8835ca8168SChen Feng enable-method = "psci"; 89a6d08344SLeo Yan next-level-cache = <&A53_L2>; 9030fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 9135ca8168SChen Feng }; 9235ca8168SChen Feng 9335ca8168SChen Feng cpu4: cpu@100 { 9435ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 9535ca8168SChen Feng device_type = "cpu"; 9635ca8168SChen Feng reg = <0x0 0x100>; 9735ca8168SChen Feng enable-method = "psci"; 98a6d08344SLeo Yan next-level-cache = <&A73_L2>; 9930fec826SLeo Yan cpu-idle-states = < 10030fec826SLeo Yan &CPU_NAP 10130fec826SLeo Yan &CPU_SLEEP 10230fec826SLeo Yan &CLUSTER_SLEEP_1 10330fec826SLeo Yan >; 10435ca8168SChen Feng }; 10535ca8168SChen Feng 10635ca8168SChen Feng cpu5: cpu@101 { 10735ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 10835ca8168SChen Feng device_type = "cpu"; 10935ca8168SChen Feng reg = <0x0 0x101>; 11035ca8168SChen Feng enable-method = "psci"; 111a6d08344SLeo Yan next-level-cache = <&A73_L2>; 11230fec826SLeo Yan cpu-idle-states = < 11330fec826SLeo Yan &CPU_NAP 11430fec826SLeo Yan &CPU_SLEEP 11530fec826SLeo Yan &CLUSTER_SLEEP_1 11630fec826SLeo Yan >; 11735ca8168SChen Feng }; 11835ca8168SChen Feng 11935ca8168SChen Feng cpu6: cpu@102 { 12035ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 12135ca8168SChen Feng device_type = "cpu"; 12235ca8168SChen Feng reg = <0x0 0x102>; 12335ca8168SChen Feng enable-method = "psci"; 124a6d08344SLeo Yan next-level-cache = <&A73_L2>; 12530fec826SLeo Yan cpu-idle-states = < 12630fec826SLeo Yan &CPU_NAP 12730fec826SLeo Yan &CPU_SLEEP 12830fec826SLeo Yan &CLUSTER_SLEEP_1 12930fec826SLeo Yan >; 13035ca8168SChen Feng }; 13135ca8168SChen Feng 13235ca8168SChen Feng cpu7: cpu@103 { 13335ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 13435ca8168SChen Feng device_type = "cpu"; 13535ca8168SChen Feng reg = <0x0 0x103>; 13635ca8168SChen Feng enable-method = "psci"; 137a6d08344SLeo Yan next-level-cache = <&A73_L2>; 13830fec826SLeo Yan cpu-idle-states = < 13930fec826SLeo Yan &CPU_NAP 14030fec826SLeo Yan &CPU_SLEEP 14130fec826SLeo Yan &CLUSTER_SLEEP_1 14230fec826SLeo Yan >; 14330fec826SLeo Yan }; 14430fec826SLeo Yan 14530fec826SLeo Yan idle-states { 14630fec826SLeo Yan entry-method = "psci"; 14730fec826SLeo Yan 14830fec826SLeo Yan CPU_NAP: cpu-nap { 14930fec826SLeo Yan compatible = "arm,idle-state"; 15030fec826SLeo Yan arm,psci-suspend-param = <0x0000001>; 15130fec826SLeo Yan entry-latency-us = <7>; 15230fec826SLeo Yan exit-latency-us = <2>; 15330fec826SLeo Yan min-residency-us = <15>; 15430fec826SLeo Yan }; 15530fec826SLeo Yan 15630fec826SLeo Yan CPU_SLEEP: cpu-sleep { 15730fec826SLeo Yan compatible = "arm,idle-state"; 15830fec826SLeo Yan local-timer-stop; 15930fec826SLeo Yan arm,psci-suspend-param = <0x0010000>; 16030fec826SLeo Yan entry-latency-us = <40>; 16130fec826SLeo Yan exit-latency-us = <70>; 16230fec826SLeo Yan min-residency-us = <3000>; 16330fec826SLeo Yan }; 16430fec826SLeo Yan 16530fec826SLeo Yan CLUSTER_SLEEP_0: cluster-sleep-0 { 16630fec826SLeo Yan compatible = "arm,idle-state"; 16730fec826SLeo Yan local-timer-stop; 16830fec826SLeo Yan arm,psci-suspend-param = <0x1010000>; 16930fec826SLeo Yan entry-latency-us = <500>; 17030fec826SLeo Yan exit-latency-us = <5000>; 17130fec826SLeo Yan min-residency-us = <20000>; 17230fec826SLeo Yan }; 17330fec826SLeo Yan 17430fec826SLeo Yan CLUSTER_SLEEP_1: cluster-sleep-1 { 17530fec826SLeo Yan compatible = "arm,idle-state"; 17630fec826SLeo Yan local-timer-stop; 17730fec826SLeo Yan arm,psci-suspend-param = <0x1010000>; 17830fec826SLeo Yan entry-latency-us = <1000>; 17930fec826SLeo Yan exit-latency-us = <5000>; 18030fec826SLeo Yan min-residency-us = <20000>; 18130fec826SLeo Yan }; 18235ca8168SChen Feng }; 183a6d08344SLeo Yan 184a6d08344SLeo Yan A53_L2: l2-cache0 { 185a6d08344SLeo Yan compatible = "cache"; 186a6d08344SLeo Yan }; 187a6d08344SLeo Yan 188a6d08344SLeo Yan A73_L2: l2-cache1 { 189a6d08344SLeo Yan compatible = "cache"; 190a6d08344SLeo Yan }; 19135ca8168SChen Feng }; 19235ca8168SChen Feng 19335ca8168SChen Feng gic: interrupt-controller@e82b0000 { 19435ca8168SChen Feng compatible = "arm,gic-400"; 19535ca8168SChen Feng reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 19635ca8168SChen Feng <0x0 0xe82b2000 0 0x2000>, /* GICC */ 19735ca8168SChen Feng <0x0 0xe82b4000 0 0x2000>, /* GICH */ 19835ca8168SChen Feng <0x0 0xe82b6000 0 0x2000>; /* GICV */ 19935ca8168SChen Feng #address-cells = <0>; 20035ca8168SChen Feng #interrupt-cells = <3>; 20135ca8168SChen Feng interrupt-controller; 20235ca8168SChen Feng interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 20335ca8168SChen Feng IRQ_TYPE_LEVEL_HIGH)>; 20435ca8168SChen Feng }; 20535ca8168SChen Feng 206f8054fb8SYiPing Xu pmu { 207f8054fb8SYiPing Xu compatible = "arm,armv8-pmuv3"; 208f8054fb8SYiPing Xu interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 209f8054fb8SYiPing Xu <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 210f8054fb8SYiPing Xu <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 211f8054fb8SYiPing Xu <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 212f8054fb8SYiPing Xu <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 213f8054fb8SYiPing Xu <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 214f8054fb8SYiPing Xu <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 215f8054fb8SYiPing Xu <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 216f8054fb8SYiPing Xu interrupt-affinity = <&cpu0>, 217f8054fb8SYiPing Xu <&cpu1>, 218f8054fb8SYiPing Xu <&cpu2>, 219f8054fb8SYiPing Xu <&cpu3>, 220f8054fb8SYiPing Xu <&cpu4>, 221f8054fb8SYiPing Xu <&cpu5>, 222f8054fb8SYiPing Xu <&cpu6>, 223f8054fb8SYiPing Xu <&cpu7>; 224f8054fb8SYiPing Xu }; 225f8054fb8SYiPing Xu 22635ca8168SChen Feng timer { 22735ca8168SChen Feng compatible = "arm,armv8-timer"; 22835ca8168SChen Feng interrupt-parent = <&gic>; 22935ca8168SChen Feng interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 23035ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 23135ca8168SChen Feng <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 23235ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 23335ca8168SChen Feng <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 23435ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 23535ca8168SChen Feng <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 23635ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>; 23735ca8168SChen Feng }; 23835ca8168SChen Feng 23935ca8168SChen Feng soc { 24035ca8168SChen Feng compatible = "simple-bus"; 24135ca8168SChen Feng #address-cells = <2>; 24235ca8168SChen Feng #size-cells = <2>; 24335ca8168SChen Feng ranges; 24435ca8168SChen Feng 245a4e36ae0SZhangfei Gao crg_ctrl: crg_ctrl@fff35000 { 246a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-crgctrl", "syscon"; 247a4e36ae0SZhangfei Gao reg = <0x0 0xfff35000 0x0 0x1000>; 248a4e36ae0SZhangfei Gao #clock-cells = <1>; 24935ca8168SChen Feng }; 25035ca8168SChen Feng 251a4e36ae0SZhangfei Gao crg_rst: crg_rst_controller { 252a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 253a4e36ae0SZhangfei Gao #reset-cells = <2>; 254a4e36ae0SZhangfei Gao hisi,rst-syscon = <&crg_ctrl>; 255a4e36ae0SZhangfei Gao }; 256a4e36ae0SZhangfei Gao 257a4e36ae0SZhangfei Gao 258a4e36ae0SZhangfei Gao pctrl: pctrl@e8a09000 { 259a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pctrl", "syscon"; 260a4e36ae0SZhangfei Gao reg = <0x0 0xe8a09000 0x0 0x2000>; 261a4e36ae0SZhangfei Gao #clock-cells = <1>; 262a4e36ae0SZhangfei Gao }; 263a4e36ae0SZhangfei Gao 264a4e36ae0SZhangfei Gao pmuctrl: crg_ctrl@fff34000 { 265a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 266a4e36ae0SZhangfei Gao reg = <0x0 0xfff34000 0x0 0x1000>; 267a4e36ae0SZhangfei Gao #clock-cells = <1>; 268a4e36ae0SZhangfei Gao }; 269a4e36ae0SZhangfei Gao 270a4e36ae0SZhangfei Gao sctrl: sctrl@fff0a000 { 271a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-sctrl", "syscon"; 272a4e36ae0SZhangfei Gao reg = <0x0 0xfff0a000 0x0 0x1000>; 273a4e36ae0SZhangfei Gao #clock-cells = <1>; 274a4e36ae0SZhangfei Gao }; 275a4e36ae0SZhangfei Gao 276a4e36ae0SZhangfei Gao iomcu: iomcu@ffd7e000 { 277a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-iomcu", "syscon"; 278a4e36ae0SZhangfei Gao reg = <0x0 0xffd7e000 0x0 0x1000>; 279a4e36ae0SZhangfei Gao #clock-cells = <1>; 280a4e36ae0SZhangfei Gao 281a4e36ae0SZhangfei Gao }; 282a4e36ae0SZhangfei Gao 283a4e36ae0SZhangfei Gao iomcu_rst: reset { 284a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 285a4e36ae0SZhangfei Gao hisi,rst-syscon = <&iomcu>; 286a4e36ae0SZhangfei Gao #reset-cells = <2>; 287a4e36ae0SZhangfei Gao }; 288a4e36ae0SZhangfei Gao 28975196330SLeo Yan dual_timer0: timer@fff14000 { 29075196330SLeo Yan compatible = "arm,sp804", "arm,primecell"; 29175196330SLeo Yan reg = <0x0 0xfff14000 0x0 0x1000>; 29275196330SLeo Yan interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 29375196330SLeo Yan <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 29475196330SLeo Yan clocks = <&crg_ctrl HI3660_OSC32K>, 29575196330SLeo Yan <&crg_ctrl HI3660_OSC32K>, 29675196330SLeo Yan <&crg_ctrl HI3660_OSC32K>; 29775196330SLeo Yan clock-names = "timer1", "timer2", "apb_pclk"; 29875196330SLeo Yan }; 29975196330SLeo Yan 3005f8a3b77SZhangfei Gao i2c0: i2c@ffd71000 { 3015f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 3025f8a3b77SZhangfei Gao reg = <0x0 0xffd71000 0x0 0x1000>; 3035f8a3b77SZhangfei Gao interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 3045f8a3b77SZhangfei Gao #address-cells = <1>; 3055f8a3b77SZhangfei Gao #size-cells = <0>; 3065f8a3b77SZhangfei Gao clock-frequency = <400000>; 3075f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 3085f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 3>; 3095f8a3b77SZhangfei Gao pinctrl-names = "default"; 3105f8a3b77SZhangfei Gao pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 3115f8a3b77SZhangfei Gao status = "disabled"; 3125f8a3b77SZhangfei Gao }; 3135f8a3b77SZhangfei Gao 3145f8a3b77SZhangfei Gao i2c1: i2c@ffd72000 { 3155f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 3165f8a3b77SZhangfei Gao reg = <0x0 0xffd72000 0x0 0x1000>; 3175f8a3b77SZhangfei Gao interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 3185f8a3b77SZhangfei Gao #address-cells = <1>; 3195f8a3b77SZhangfei Gao #size-cells = <0>; 3205f8a3b77SZhangfei Gao clock-frequency = <400000>; 3215f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 3225f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 4>; 3235f8a3b77SZhangfei Gao pinctrl-names = "default"; 3245f8a3b77SZhangfei Gao pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 3255f8a3b77SZhangfei Gao status = "disabled"; 3265f8a3b77SZhangfei Gao }; 3275f8a3b77SZhangfei Gao 3285f8a3b77SZhangfei Gao i2c3: i2c@fdf0c000 { 3295f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 3305f8a3b77SZhangfei Gao reg = <0x0 0xfdf0c000 0x0 0x1000>; 3315f8a3b77SZhangfei Gao interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3325f8a3b77SZhangfei Gao #address-cells = <1>; 3335f8a3b77SZhangfei Gao #size-cells = <0>; 3345f8a3b77SZhangfei Gao clock-frequency = <400000>; 3355f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 3365f8a3b77SZhangfei Gao resets = <&crg_rst 0x78 7>; 3375f8a3b77SZhangfei Gao pinctrl-names = "default"; 3385f8a3b77SZhangfei Gao pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 3395f8a3b77SZhangfei Gao status = "disabled"; 3405f8a3b77SZhangfei Gao }; 3415f8a3b77SZhangfei Gao 3425f8a3b77SZhangfei Gao i2c7: i2c@fdf0b000 { 3435f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 3445f8a3b77SZhangfei Gao reg = <0x0 0xfdf0b000 0x0 0x1000>; 3455f8a3b77SZhangfei Gao interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 3465f8a3b77SZhangfei Gao #address-cells = <1>; 3475f8a3b77SZhangfei Gao #size-cells = <0>; 3485f8a3b77SZhangfei Gao clock-frequency = <400000>; 3495f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 3505f8a3b77SZhangfei Gao resets = <&crg_rst 0x60 14>; 3515f8a3b77SZhangfei Gao pinctrl-names = "default"; 3525f8a3b77SZhangfei Gao pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 3535f8a3b77SZhangfei Gao status = "disabled"; 3545f8a3b77SZhangfei Gao }; 3555f8a3b77SZhangfei Gao 356254b07b2SChen Feng uart0: serial@fdf02000 { 357254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 358254b07b2SChen Feng reg = <0x0 0xfdf02000 0x0 0x1000>; 359254b07b2SChen Feng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 360254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 361254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 362254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 363254b07b2SChen Feng pinctrl-names = "default"; 364254b07b2SChen Feng pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 365254b07b2SChen Feng status = "disabled"; 366254b07b2SChen Feng }; 367254b07b2SChen Feng 368254b07b2SChen Feng uart1: serial@fdf00000 { 369254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 370254b07b2SChen Feng reg = <0x0 0xfdf00000 0x0 0x1000>; 371254b07b2SChen Feng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 372254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 373254b07b2SChen Feng <&crg_ctrl HI3660_CLK_GATE_UART1>; 374254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 375254b07b2SChen Feng pinctrl-names = "default"; 376254b07b2SChen Feng pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 377254b07b2SChen Feng status = "disabled"; 378254b07b2SChen Feng }; 379254b07b2SChen Feng 380254b07b2SChen Feng uart2: serial@fdf03000 { 381254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 382254b07b2SChen Feng reg = <0x0 0xfdf03000 0x0 0x1000>; 383254b07b2SChen Feng interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 384254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 385254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 386254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 387254b07b2SChen Feng pinctrl-names = "default"; 388254b07b2SChen Feng pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 389254b07b2SChen Feng status = "disabled"; 390254b07b2SChen Feng }; 391254b07b2SChen Feng 392254b07b2SChen Feng uart3: serial@ffd74000 { 393254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 394254b07b2SChen Feng reg = <0x0 0xffd74000 0x0 0x1000>; 395254b07b2SChen Feng interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 396254b07b2SChen Feng clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 397254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 398254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 399254b07b2SChen Feng pinctrl-names = "default"; 400254b07b2SChen Feng pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 401254b07b2SChen Feng status = "disabled"; 402254b07b2SChen Feng }; 403254b07b2SChen Feng 404254b07b2SChen Feng uart4: serial@fdf01000 { 405254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 406254b07b2SChen Feng reg = <0x0 0xfdf01000 0x0 0x1000>; 407254b07b2SChen Feng interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 408254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 409254b07b2SChen Feng <&crg_ctrl HI3660_CLK_GATE_UART4>; 410254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 411254b07b2SChen Feng pinctrl-names = "default"; 412254b07b2SChen Feng pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 413254b07b2SChen Feng status = "disabled"; 414254b07b2SChen Feng }; 415254b07b2SChen Feng 416a4e36ae0SZhangfei Gao uart5: serial@fdf05000 { 41735ca8168SChen Feng compatible = "arm,pl011", "arm,primecell"; 41835ca8168SChen Feng reg = <0x0 0xfdf05000 0x0 0x1000>; 41935ca8168SChen Feng interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 420a4e36ae0SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 421a4e36ae0SZhangfei Gao <&crg_ctrl HI3660_CLK_GATE_UART5>; 42235ca8168SChen Feng clock-names = "uartclk", "apb_pclk"; 423254b07b2SChen Feng pinctrl-names = "default"; 424254b07b2SChen Feng pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 425254b07b2SChen Feng status = "disabled"; 426254b07b2SChen Feng }; 427254b07b2SChen Feng 428254b07b2SChen Feng uart6: serial@fff32000 { 429254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 430254b07b2SChen Feng reg = <0x0 0xfff32000 0x0 0x1000>; 431254b07b2SChen Feng interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 432254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_UART6>, 433254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 434254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 435254b07b2SChen Feng pinctrl-names = "default"; 436254b07b2SChen Feng pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 43735ca8168SChen Feng status = "disabled"; 43835ca8168SChen Feng }; 439d94eab86SWang Xiaoyin 4400b507e91SWang Ruyi dma0: dma@fdf30000 { 4410b507e91SWang Ruyi compatible = "hisilicon,k3-dma-1.0"; 4420b507e91SWang Ruyi reg = <0x0 0xfdf30000 0x0 0x1000>; 4430b507e91SWang Ruyi #dma-cells = <1>; 4440b507e91SWang Ruyi dma-channels = <16>; 4450b507e91SWang Ruyi dma-requests = <32>; 4460b507e91SWang Ruyi dma-min-chan = <1>; 4470b507e91SWang Ruyi interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 4480b507e91SWang Ruyi clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; 4490b507e91SWang Ruyi dma-no-cci; 4500b507e91SWang Ruyi dma-type = "hi3660_dma"; 4510b507e91SWang Ruyi }; 4520b507e91SWang Ruyi 4530a0698f6SChen Feng rtc0: rtc@fff04000 { 4540a0698f6SChen Feng compatible = "arm,pl031", "arm,primecell"; 4550a0698f6SChen Feng reg = <0x0 0Xfff04000 0x0 0x1000>; 4560a0698f6SChen Feng interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 4570a0698f6SChen Feng clocks = <&crg_ctrl HI3660_PCLK>; 4580a0698f6SChen Feng clock-names = "apb_pclk"; 4590a0698f6SChen Feng }; 4600a0698f6SChen Feng 461d94eab86SWang Xiaoyin gpio0: gpio@e8a0b000 { 462d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 463d94eab86SWang Xiaoyin reg = <0 0xe8a0b000 0 0x1000>; 464d94eab86SWang Xiaoyin interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 465d94eab86SWang Xiaoyin gpio-controller; 466d94eab86SWang Xiaoyin #gpio-cells = <2>; 467d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 0 7>; 468d94eab86SWang Xiaoyin interrupt-controller; 469d94eab86SWang Xiaoyin #interrupt-cells = <2>; 470d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 471d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 472d94eab86SWang Xiaoyin }; 473d94eab86SWang Xiaoyin 474d94eab86SWang Xiaoyin gpio1: gpio@e8a0c000 { 475d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 476d94eab86SWang Xiaoyin reg = <0 0xe8a0c000 0 0x1000>; 477d94eab86SWang Xiaoyin interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 478d94eab86SWang Xiaoyin gpio-controller; 479d94eab86SWang Xiaoyin #gpio-cells = <2>; 480d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 7 7>; 481d94eab86SWang Xiaoyin interrupt-controller; 482d94eab86SWang Xiaoyin #interrupt-cells = <2>; 483d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 484d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 485d94eab86SWang Xiaoyin }; 486d94eab86SWang Xiaoyin 487d94eab86SWang Xiaoyin gpio2: gpio@e8a0d000 { 488d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 489d94eab86SWang Xiaoyin reg = <0 0xe8a0d000 0 0x1000>; 490d94eab86SWang Xiaoyin interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 491d94eab86SWang Xiaoyin gpio-controller; 492d94eab86SWang Xiaoyin #gpio-cells = <2>; 493d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 14 8>; 494d94eab86SWang Xiaoyin interrupt-controller; 495d94eab86SWang Xiaoyin #interrupt-cells = <2>; 496d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 497d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 498d94eab86SWang Xiaoyin }; 499d94eab86SWang Xiaoyin 500d94eab86SWang Xiaoyin gpio3: gpio@e8a0e000 { 501d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 502d94eab86SWang Xiaoyin reg = <0 0xe8a0e000 0 0x1000>; 503d94eab86SWang Xiaoyin interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 504d94eab86SWang Xiaoyin gpio-controller; 505d94eab86SWang Xiaoyin #gpio-cells = <2>; 506d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 22 8>; 507d94eab86SWang Xiaoyin interrupt-controller; 508d94eab86SWang Xiaoyin #interrupt-cells = <2>; 509d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 510d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 511d94eab86SWang Xiaoyin }; 512d94eab86SWang Xiaoyin 513d94eab86SWang Xiaoyin gpio4: gpio@e8a0f000 { 514d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 515d94eab86SWang Xiaoyin reg = <0 0xe8a0f000 0 0x1000>; 516d94eab86SWang Xiaoyin interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 517d94eab86SWang Xiaoyin gpio-controller; 518d94eab86SWang Xiaoyin #gpio-cells = <2>; 519d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 30 8>; 520d94eab86SWang Xiaoyin interrupt-controller; 521d94eab86SWang Xiaoyin #interrupt-cells = <2>; 522d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 523d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 524d94eab86SWang Xiaoyin }; 525d94eab86SWang Xiaoyin 526d94eab86SWang Xiaoyin gpio5: gpio@e8a10000 { 527d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 528d94eab86SWang Xiaoyin reg = <0 0xe8a10000 0 0x1000>; 529d94eab86SWang Xiaoyin interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 530d94eab86SWang Xiaoyin gpio-controller; 531d94eab86SWang Xiaoyin #gpio-cells = <2>; 532d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 38 8>; 533d94eab86SWang Xiaoyin interrupt-controller; 534d94eab86SWang Xiaoyin #interrupt-cells = <2>; 535d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 536d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 537d94eab86SWang Xiaoyin }; 538d94eab86SWang Xiaoyin 539d94eab86SWang Xiaoyin gpio6: gpio@e8a11000 { 540d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 541d94eab86SWang Xiaoyin reg = <0 0xe8a11000 0 0x1000>; 542d94eab86SWang Xiaoyin interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 543d94eab86SWang Xiaoyin gpio-controller; 544d94eab86SWang Xiaoyin #gpio-cells = <2>; 545d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 46 8>; 546d94eab86SWang Xiaoyin interrupt-controller; 547d94eab86SWang Xiaoyin #interrupt-cells = <2>; 548d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 549d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 550d94eab86SWang Xiaoyin }; 551d94eab86SWang Xiaoyin 552d94eab86SWang Xiaoyin gpio7: gpio@e8a12000 { 553d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 554d94eab86SWang Xiaoyin reg = <0 0xe8a12000 0 0x1000>; 555d94eab86SWang Xiaoyin interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 556d94eab86SWang Xiaoyin gpio-controller; 557d94eab86SWang Xiaoyin #gpio-cells = <2>; 558d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 54 8>; 559d94eab86SWang Xiaoyin interrupt-controller; 560d94eab86SWang Xiaoyin #interrupt-cells = <2>; 561d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 562d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 563d94eab86SWang Xiaoyin }; 564d94eab86SWang Xiaoyin 565d94eab86SWang Xiaoyin gpio8: gpio@e8a13000 { 566d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 567d94eab86SWang Xiaoyin reg = <0 0xe8a13000 0 0x1000>; 568d94eab86SWang Xiaoyin interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 569d94eab86SWang Xiaoyin gpio-controller; 570d94eab86SWang Xiaoyin #gpio-cells = <2>; 571d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 62 8>; 572d94eab86SWang Xiaoyin interrupt-controller; 573d94eab86SWang Xiaoyin #interrupt-cells = <2>; 574d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 575d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 576d94eab86SWang Xiaoyin }; 577d94eab86SWang Xiaoyin 578d94eab86SWang Xiaoyin gpio9: gpio@e8a14000 { 579d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 580d94eab86SWang Xiaoyin reg = <0 0xe8a14000 0 0x1000>; 581d94eab86SWang Xiaoyin interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 582d94eab86SWang Xiaoyin gpio-controller; 583d94eab86SWang Xiaoyin #gpio-cells = <2>; 584d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 70 8>; 585d94eab86SWang Xiaoyin interrupt-controller; 586d94eab86SWang Xiaoyin #interrupt-cells = <2>; 587d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 588d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 589d94eab86SWang Xiaoyin }; 590d94eab86SWang Xiaoyin 591d94eab86SWang Xiaoyin gpio10: gpio@e8a15000 { 592d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 593d94eab86SWang Xiaoyin reg = <0 0xe8a15000 0 0x1000>; 594d94eab86SWang Xiaoyin interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 595d94eab86SWang Xiaoyin gpio-controller; 596d94eab86SWang Xiaoyin #gpio-cells = <2>; 597d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 78 8>; 598d94eab86SWang Xiaoyin interrupt-controller; 599d94eab86SWang Xiaoyin #interrupt-cells = <2>; 600d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 601d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 602d94eab86SWang Xiaoyin }; 603d94eab86SWang Xiaoyin 604d94eab86SWang Xiaoyin gpio11: gpio@e8a16000 { 605d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 606d94eab86SWang Xiaoyin reg = <0 0xe8a16000 0 0x1000>; 607d94eab86SWang Xiaoyin interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 608d94eab86SWang Xiaoyin gpio-controller; 609d94eab86SWang Xiaoyin #gpio-cells = <2>; 610d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 86 8>; 611d94eab86SWang Xiaoyin interrupt-controller; 612d94eab86SWang Xiaoyin #interrupt-cells = <2>; 613d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 614d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 615d94eab86SWang Xiaoyin }; 616d94eab86SWang Xiaoyin 617d94eab86SWang Xiaoyin gpio12: gpio@e8a17000 { 618d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 619d94eab86SWang Xiaoyin reg = <0 0xe8a17000 0 0x1000>; 620d94eab86SWang Xiaoyin interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 621d94eab86SWang Xiaoyin gpio-controller; 622d94eab86SWang Xiaoyin #gpio-cells = <2>; 623d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 624d94eab86SWang Xiaoyin interrupt-controller; 625d94eab86SWang Xiaoyin #interrupt-cells = <2>; 626d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 627d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 628d94eab86SWang Xiaoyin }; 629d94eab86SWang Xiaoyin 630d94eab86SWang Xiaoyin gpio13: gpio@e8a18000 { 631d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 632d94eab86SWang Xiaoyin reg = <0 0xe8a18000 0 0x1000>; 633d94eab86SWang Xiaoyin interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 634d94eab86SWang Xiaoyin gpio-controller; 635d94eab86SWang Xiaoyin #gpio-cells = <2>; 636d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 102 8>; 637d94eab86SWang Xiaoyin interrupt-controller; 638d94eab86SWang Xiaoyin #interrupt-cells = <2>; 639d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 640d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 641d94eab86SWang Xiaoyin }; 642d94eab86SWang Xiaoyin 643d94eab86SWang Xiaoyin gpio14: gpio@e8a19000 { 644d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 645d94eab86SWang Xiaoyin reg = <0 0xe8a19000 0 0x1000>; 646d94eab86SWang Xiaoyin interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 647d94eab86SWang Xiaoyin gpio-controller; 648d94eab86SWang Xiaoyin #gpio-cells = <2>; 649d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 110 8>; 650d94eab86SWang Xiaoyin interrupt-controller; 651d94eab86SWang Xiaoyin #interrupt-cells = <2>; 652d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 653d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 654d94eab86SWang Xiaoyin }; 655d94eab86SWang Xiaoyin 656d94eab86SWang Xiaoyin gpio15: gpio@e8a1a000 { 657d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 658d94eab86SWang Xiaoyin reg = <0 0xe8a1a000 0 0x1000>; 659d94eab86SWang Xiaoyin interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 660d94eab86SWang Xiaoyin gpio-controller; 661d94eab86SWang Xiaoyin #gpio-cells = <2>; 662d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 118 6>; 663d94eab86SWang Xiaoyin interrupt-controller; 664d94eab86SWang Xiaoyin #interrupt-cells = <2>; 665d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 666d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 667d94eab86SWang Xiaoyin }; 668d94eab86SWang Xiaoyin 669d94eab86SWang Xiaoyin gpio16: gpio@e8a1b000 { 670d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 671d94eab86SWang Xiaoyin reg = <0 0xe8a1b000 0 0x1000>; 672d94eab86SWang Xiaoyin interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 673d94eab86SWang Xiaoyin gpio-controller; 674d94eab86SWang Xiaoyin #gpio-cells = <2>; 675d94eab86SWang Xiaoyin interrupt-controller; 676d94eab86SWang Xiaoyin #interrupt-cells = <2>; 677d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 678d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 679d94eab86SWang Xiaoyin }; 680d94eab86SWang Xiaoyin 681d94eab86SWang Xiaoyin gpio17: gpio@e8a1c000 { 682d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 683d94eab86SWang Xiaoyin reg = <0 0xe8a1c000 0 0x1000>; 684d94eab86SWang Xiaoyin interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 685d94eab86SWang Xiaoyin gpio-controller; 686d94eab86SWang Xiaoyin #gpio-cells = <2>; 687d94eab86SWang Xiaoyin interrupt-controller; 688d94eab86SWang Xiaoyin #interrupt-cells = <2>; 689d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 690d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 691d94eab86SWang Xiaoyin }; 692d94eab86SWang Xiaoyin 693d94eab86SWang Xiaoyin gpio18: gpio@ff3b4000 { 694d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 695d94eab86SWang Xiaoyin reg = <0 0xff3b4000 0 0x1000>; 696d94eab86SWang Xiaoyin interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 697d94eab86SWang Xiaoyin gpio-controller; 698d94eab86SWang Xiaoyin #gpio-cells = <2>; 699d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 0 8>; 700d94eab86SWang Xiaoyin interrupt-controller; 701d94eab86SWang Xiaoyin #interrupt-cells = <2>; 702d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 703d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 704d94eab86SWang Xiaoyin }; 705d94eab86SWang Xiaoyin 706d94eab86SWang Xiaoyin gpio19: gpio@ff3b5000 { 707d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 708d94eab86SWang Xiaoyin reg = <0 0xff3b5000 0 0x1000>; 709d94eab86SWang Xiaoyin interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 710d94eab86SWang Xiaoyin gpio-controller; 711d94eab86SWang Xiaoyin #gpio-cells = <2>; 712d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 8 4>; 713d94eab86SWang Xiaoyin interrupt-controller; 714d94eab86SWang Xiaoyin #interrupt-cells = <2>; 715d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 716d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 717d94eab86SWang Xiaoyin }; 718d94eab86SWang Xiaoyin 719d94eab86SWang Xiaoyin gpio20: gpio@e8a1f000 { 720d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 721d94eab86SWang Xiaoyin reg = <0 0xe8a1f000 0 0x1000>; 722d94eab86SWang Xiaoyin interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 723d94eab86SWang Xiaoyin gpio-controller; 724d94eab86SWang Xiaoyin #gpio-cells = <2>; 725d94eab86SWang Xiaoyin gpio-ranges = <&pmx1 0 0 6>; 726d94eab86SWang Xiaoyin interrupt-controller; 727d94eab86SWang Xiaoyin #interrupt-cells = <2>; 728d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 729d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 730d94eab86SWang Xiaoyin }; 731d94eab86SWang Xiaoyin 732d94eab86SWang Xiaoyin gpio21: gpio@e8a20000 { 733d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 734d94eab86SWang Xiaoyin reg = <0 0xe8a20000 0 0x1000>; 735d94eab86SWang Xiaoyin interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 736d94eab86SWang Xiaoyin gpio-controller; 737d94eab86SWang Xiaoyin #gpio-cells = <2>; 738d94eab86SWang Xiaoyin interrupt-controller; 739d94eab86SWang Xiaoyin #interrupt-cells = <2>; 740d94eab86SWang Xiaoyin gpio-ranges = <&pmx3 0 0 6>; 741d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 742d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 743d94eab86SWang Xiaoyin }; 744d94eab86SWang Xiaoyin 745d94eab86SWang Xiaoyin gpio22: gpio@fff0b000 { 746d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 747d94eab86SWang Xiaoyin reg = <0 0xfff0b000 0 0x1000>; 748d94eab86SWang Xiaoyin interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 749d94eab86SWang Xiaoyin gpio-controller; 750d94eab86SWang Xiaoyin #gpio-cells = <2>; 751d94eab86SWang Xiaoyin /* GPIO176 */ 752d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 2 0 6>; 753d94eab86SWang Xiaoyin interrupt-controller; 754d94eab86SWang Xiaoyin #interrupt-cells = <2>; 755d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 756d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 757d94eab86SWang Xiaoyin }; 758d94eab86SWang Xiaoyin 759d94eab86SWang Xiaoyin gpio23: gpio@fff0c000 { 760d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 761d94eab86SWang Xiaoyin reg = <0 0xfff0c000 0 0x1000>; 762d94eab86SWang Xiaoyin interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 763d94eab86SWang Xiaoyin gpio-controller; 764d94eab86SWang Xiaoyin #gpio-cells = <2>; 765d94eab86SWang Xiaoyin /* GPIO184 */ 766d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 6 7>; 767d94eab86SWang Xiaoyin interrupt-controller; 768d94eab86SWang Xiaoyin #interrupt-cells = <2>; 769d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 770d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 771d94eab86SWang Xiaoyin }; 772d94eab86SWang Xiaoyin 773d94eab86SWang Xiaoyin gpio24: gpio@fff0d000 { 774d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 775d94eab86SWang Xiaoyin reg = <0 0xfff0d000 0 0x1000>; 776d94eab86SWang Xiaoyin interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 777d94eab86SWang Xiaoyin gpio-controller; 778d94eab86SWang Xiaoyin #gpio-cells = <2>; 779d94eab86SWang Xiaoyin /* GPIO192 */ 780d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 13 8>; 781d94eab86SWang Xiaoyin interrupt-controller; 782d94eab86SWang Xiaoyin #interrupt-cells = <2>; 783d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 784d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 785d94eab86SWang Xiaoyin }; 786d94eab86SWang Xiaoyin 787d94eab86SWang Xiaoyin gpio25: gpio@fff0e000 { 788d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 789d94eab86SWang Xiaoyin reg = <0 0xfff0e000 0 0x1000>; 790d94eab86SWang Xiaoyin interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 791d94eab86SWang Xiaoyin gpio-controller; 792d94eab86SWang Xiaoyin #gpio-cells = <2>; 793d94eab86SWang Xiaoyin /* GPIO200 */ 794d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 795d94eab86SWang Xiaoyin interrupt-controller; 796d94eab86SWang Xiaoyin #interrupt-cells = <2>; 797d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 798d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 799d94eab86SWang Xiaoyin }; 800d94eab86SWang Xiaoyin 801d94eab86SWang Xiaoyin gpio26: gpio@fff0f000 { 802d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 803d94eab86SWang Xiaoyin reg = <0 0xfff0f000 0 0x1000>; 804d94eab86SWang Xiaoyin interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 805d94eab86SWang Xiaoyin gpio-controller; 806d94eab86SWang Xiaoyin #gpio-cells = <2>; 807d94eab86SWang Xiaoyin /* GPIO208 */ 808d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 28 8>; 809d94eab86SWang Xiaoyin interrupt-controller; 810d94eab86SWang Xiaoyin #interrupt-cells = <2>; 811d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 812d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 813d94eab86SWang Xiaoyin }; 814d94eab86SWang Xiaoyin 815d94eab86SWang Xiaoyin gpio27: gpio@fff10000 { 816d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 817d94eab86SWang Xiaoyin reg = <0 0xfff10000 0 0x1000>; 818d94eab86SWang Xiaoyin interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 819d94eab86SWang Xiaoyin gpio-controller; 820d94eab86SWang Xiaoyin #gpio-cells = <2>; 821d94eab86SWang Xiaoyin /* GPIO216 */ 822d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 36 6>; 823d94eab86SWang Xiaoyin interrupt-controller; 824d94eab86SWang Xiaoyin #interrupt-cells = <2>; 825d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 826d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 827d94eab86SWang Xiaoyin }; 828d94eab86SWang Xiaoyin 829d94eab86SWang Xiaoyin gpio28: gpio@fff1d000 { 830d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 831d94eab86SWang Xiaoyin reg = <0 0xfff1d000 0 0x1000>; 832d94eab86SWang Xiaoyin interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 833d94eab86SWang Xiaoyin gpio-controller; 834d94eab86SWang Xiaoyin #gpio-cells = <2>; 835d94eab86SWang Xiaoyin interrupt-controller; 836d94eab86SWang Xiaoyin #interrupt-cells = <2>; 837d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 838d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 839d94eab86SWang Xiaoyin }; 84038810497SWang Xiaoyin 84138810497SWang Xiaoyin spi2: spi@ffd68000 { 84238810497SWang Xiaoyin compatible = "arm,pl022", "arm,primecell"; 84338810497SWang Xiaoyin reg = <0x0 0xffd68000 0x0 0x1000>; 84438810497SWang Xiaoyin #address-cells = <1>; 84538810497SWang Xiaoyin #size-cells = <0>; 84638810497SWang Xiaoyin interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 84738810497SWang Xiaoyin clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; 84838810497SWang Xiaoyin clock-names = "apb_pclk"; 84938810497SWang Xiaoyin pinctrl-names = "default"; 85038810497SWang Xiaoyin pinctrl-0 = <&spi2_pmx_func>; 85138810497SWang Xiaoyin num-cs = <1>; 85238810497SWang Xiaoyin cs-gpios = <&gpio27 2 0>; 85338810497SWang Xiaoyin status = "disabled"; 85438810497SWang Xiaoyin }; 85538810497SWang Xiaoyin 85638810497SWang Xiaoyin spi3: spi@ff3b3000 { 85738810497SWang Xiaoyin compatible = "arm,pl022", "arm,primecell"; 85838810497SWang Xiaoyin reg = <0x0 0xff3b3000 0x0 0x1000>; 85938810497SWang Xiaoyin #address-cells = <1>; 86038810497SWang Xiaoyin #size-cells = <0>; 86138810497SWang Xiaoyin interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 86238810497SWang Xiaoyin clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; 86338810497SWang Xiaoyin clock-names = "apb_pclk"; 86438810497SWang Xiaoyin pinctrl-names = "default"; 86538810497SWang Xiaoyin pinctrl-0 = <&spi3_pmx_func>; 86638810497SWang Xiaoyin num-cs = <1>; 86738810497SWang Xiaoyin cs-gpios = <&gpio18 5 0>; 86838810497SWang Xiaoyin status = "disabled"; 86938810497SWang Xiaoyin }; 87096909778SXiaowei Song 87196909778SXiaowei Song pcie@f4000000 { 87296909778SXiaowei Song compatible = "hisilicon,kirin960-pcie"; 87396909778SXiaowei Song reg = <0x0 0xf4000000 0x0 0x1000>, 87496909778SXiaowei Song <0x0 0xff3fe000 0x0 0x1000>, 87596909778SXiaowei Song <0x0 0xf3f20000 0x0 0x40000>, 87696909778SXiaowei Song <0x0 0xf5000000 0x0 0x2000>; 87796909778SXiaowei Song reg-names = "dbi", "apb", "phy", "config"; 87896909778SXiaowei Song bus-range = <0x0 0x1>; 87996909778SXiaowei Song #address-cells = <3>; 88096909778SXiaowei Song #size-cells = <2>; 88196909778SXiaowei Song device_type = "pci"; 88296909778SXiaowei Song ranges = <0x02000000 0x0 0x00000000 88396909778SXiaowei Song 0x0 0xf6000000 88496909778SXiaowei Song 0x0 0x02000000>; 88596909778SXiaowei Song num-lanes = <1>; 88696909778SXiaowei Song #interrupt-cells = <1>; 88796909778SXiaowei Song interrupt-map-mask = <0xf800 0 0 7>; 88896909778SXiaowei Song interrupt-map = <0x0 0 0 1 88996909778SXiaowei Song &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 89096909778SXiaowei Song <0x0 0 0 2 89196909778SXiaowei Song &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 89296909778SXiaowei Song <0x0 0 0 3 89396909778SXiaowei Song &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 89496909778SXiaowei Song <0x0 0 0 4 89596909778SXiaowei Song &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 89696909778SXiaowei Song clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 89796909778SXiaowei Song <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 89896909778SXiaowei Song <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 89996909778SXiaowei Song <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 90096909778SXiaowei Song <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 90196909778SXiaowei Song clock-names = "pcie_phy_ref", "pcie_aux", 90296909778SXiaowei Song "pcie_apb_phy", "pcie_apb_sys", 90396909778SXiaowei Song "pcie_aclk"; 90496909778SXiaowei Song reset-gpios = <&gpio11 1 0 >; 90596909778SXiaowei Song }; 906804d7d7aSLi Wei 907804d7d7aSLi Wei /* SD */ 908804d7d7aSLi Wei dwmmc1: dwmmc1@ff37f000 { 909804d7d7aSLi Wei #address-cells = <1>; 910804d7d7aSLi Wei #size-cells = <0>; 911804d7d7aSLi Wei cd-inverted; 912804d7d7aSLi Wei compatible = "hisilicon,hi3660-dw-mshc"; 913804d7d7aSLi Wei num-slots = <1>; 914804d7d7aSLi Wei bus-width = <0x4>; 915804d7d7aSLi Wei disable-wp; 916804d7d7aSLi Wei cap-sd-highspeed; 917804d7d7aSLi Wei supports-highspeed; 918804d7d7aSLi Wei card-detect-delay = <200>; 919804d7d7aSLi Wei reg = <0x0 0xff37f000 0x0 0x1000>; 920804d7d7aSLi Wei interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 921804d7d7aSLi Wei clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, 922804d7d7aSLi Wei <&crg_ctrl HI3660_HCLK_GATE_SD>; 923804d7d7aSLi Wei clock-names = "ciu", "biu"; 924804d7d7aSLi Wei clock-frequency = <3200000>; 925804d7d7aSLi Wei resets = <&crg_rst 0x94 18>; 926996707d7SGuodong Xu reset-names = "reset"; 927804d7d7aSLi Wei cd-gpios = <&gpio25 3 0>; 928804d7d7aSLi Wei hisilicon,peripheral-syscon = <&sctrl>; 929804d7d7aSLi Wei pinctrl-names = "default"; 930804d7d7aSLi Wei pinctrl-0 = <&sd_pmx_func 931804d7d7aSLi Wei &sd_clk_cfg_func 932804d7d7aSLi Wei &sd_cfg_func>; 933804d7d7aSLi Wei sd-uhs-sdr12; 934804d7d7aSLi Wei sd-uhs-sdr25; 935804d7d7aSLi Wei sd-uhs-sdr50; 936804d7d7aSLi Wei sd-uhs-sdr104; 937804d7d7aSLi Wei status = "disabled"; 938804d7d7aSLi Wei 939804d7d7aSLi Wei slot@0 { 940804d7d7aSLi Wei reg = <0x0>; 941804d7d7aSLi Wei bus-width = <4>; 942804d7d7aSLi Wei disable-wp; 943804d7d7aSLi Wei }; 944804d7d7aSLi Wei }; 945804d7d7aSLi Wei 946804d7d7aSLi Wei /* SDIO */ 947804d7d7aSLi Wei dwmmc2: dwmmc2@ff3ff000 { 948804d7d7aSLi Wei compatible = "hisilicon,hi3660-dw-mshc"; 949804d7d7aSLi Wei reg = <0x0 0xff3ff000 0x0 0x1000>; 950804d7d7aSLi Wei interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 951804d7d7aSLi Wei num-slots = <1>; 952804d7d7aSLi Wei clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, 953804d7d7aSLi Wei <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; 954804d7d7aSLi Wei clock-names = "ciu", "biu"; 955804d7d7aSLi Wei resets = <&crg_rst 0x94 20>; 956996707d7SGuodong Xu reset-names = "reset"; 957804d7d7aSLi Wei card-detect-delay = <200>; 958804d7d7aSLi Wei supports-highspeed; 959804d7d7aSLi Wei keep-power-in-suspend; 960804d7d7aSLi Wei pinctrl-names = "default"; 961804d7d7aSLi Wei pinctrl-0 = <&sdio_pmx_func 962804d7d7aSLi Wei &sdio_clk_cfg_func 963804d7d7aSLi Wei &sdio_cfg_func>; 964804d7d7aSLi Wei status = "disabled"; 965804d7d7aSLi Wei }; 966487f00d4SLeo Yan 967487f00d4SLeo Yan watchdog0: watchdog@e8a06000 { 968487f00d4SLeo Yan compatible = "arm,sp805-wdt", "arm,primecell"; 969487f00d4SLeo Yan reg = <0x0 0xe8a06000 0x0 0x1000>; 970487f00d4SLeo Yan interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 971487f00d4SLeo Yan clocks = <&crg_ctrl HI3660_OSC32K>; 972487f00d4SLeo Yan clock-names = "apb_pclk"; 973487f00d4SLeo Yan }; 974487f00d4SLeo Yan 975487f00d4SLeo Yan watchdog1: watchdog@e8a07000 { 976487f00d4SLeo Yan compatible = "arm,sp805-wdt", "arm,primecell"; 977487f00d4SLeo Yan reg = <0x0 0xe8a07000 0x0 0x1000>; 978487f00d4SLeo Yan interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 979487f00d4SLeo Yan clocks = <&crg_ctrl HI3660_OSC32K>; 980487f00d4SLeo Yan clock-names = "apb_pclk"; 981487f00d4SLeo Yan }; 98235ca8168SChen Feng }; 98335ca8168SChen Feng}; 984