135ca8168SChen Feng/* 235ca8168SChen Feng * dts file for Hisilicon Hi3660 SoC 335ca8168SChen Feng * 435ca8168SChen Feng * Copyright (C) 2016, Hisilicon Ltd. 535ca8168SChen Feng */ 635ca8168SChen Feng 735ca8168SChen Feng#include <dt-bindings/interrupt-controller/arm-gic.h> 8a4e36ae0SZhangfei Gao#include <dt-bindings/clock/hi3660-clock.h> 935ca8168SChen Feng 1035ca8168SChen Feng/ { 1135ca8168SChen Feng compatible = "hisilicon,hi3660"; 1235ca8168SChen Feng interrupt-parent = <&gic>; 1335ca8168SChen Feng #address-cells = <2>; 1435ca8168SChen Feng #size-cells = <2>; 1535ca8168SChen Feng 1635ca8168SChen Feng psci { 1735ca8168SChen Feng compatible = "arm,psci-0.2"; 1835ca8168SChen Feng method = "smc"; 1935ca8168SChen Feng }; 2035ca8168SChen Feng 2135ca8168SChen Feng cpus { 2235ca8168SChen Feng #address-cells = <2>; 2335ca8168SChen Feng #size-cells = <0>; 2435ca8168SChen Feng 2535ca8168SChen Feng cpu-map { 2635ca8168SChen Feng cluster0 { 2735ca8168SChen Feng core0 { 2835ca8168SChen Feng cpu = <&cpu0>; 2935ca8168SChen Feng }; 3035ca8168SChen Feng core1 { 3135ca8168SChen Feng cpu = <&cpu1>; 3235ca8168SChen Feng }; 3335ca8168SChen Feng core2 { 3435ca8168SChen Feng cpu = <&cpu2>; 3535ca8168SChen Feng }; 3635ca8168SChen Feng core3 { 3735ca8168SChen Feng cpu = <&cpu3>; 3835ca8168SChen Feng }; 3935ca8168SChen Feng }; 4035ca8168SChen Feng cluster1 { 4135ca8168SChen Feng core0 { 4235ca8168SChen Feng cpu = <&cpu4>; 4335ca8168SChen Feng }; 4435ca8168SChen Feng core1 { 4535ca8168SChen Feng cpu = <&cpu5>; 4635ca8168SChen Feng }; 4735ca8168SChen Feng core2 { 4835ca8168SChen Feng cpu = <&cpu6>; 4935ca8168SChen Feng }; 5035ca8168SChen Feng core3 { 5135ca8168SChen Feng cpu = <&cpu7>; 5235ca8168SChen Feng }; 5335ca8168SChen Feng }; 5435ca8168SChen Feng }; 5535ca8168SChen Feng 5635ca8168SChen Feng cpu0: cpu@0 { 5735ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 5835ca8168SChen Feng device_type = "cpu"; 5935ca8168SChen Feng reg = <0x0 0x0>; 6035ca8168SChen Feng enable-method = "psci"; 6135ca8168SChen Feng }; 6235ca8168SChen Feng 6335ca8168SChen Feng cpu1: cpu@1 { 6435ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 6535ca8168SChen Feng device_type = "cpu"; 6635ca8168SChen Feng reg = <0x0 0x1>; 6735ca8168SChen Feng enable-method = "psci"; 6835ca8168SChen Feng }; 6935ca8168SChen Feng 7035ca8168SChen Feng cpu2: cpu@2 { 7135ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 7235ca8168SChen Feng device_type = "cpu"; 7335ca8168SChen Feng reg = <0x0 0x2>; 7435ca8168SChen Feng enable-method = "psci"; 7535ca8168SChen Feng }; 7635ca8168SChen Feng 7735ca8168SChen Feng cpu3: cpu@3 { 7835ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 7935ca8168SChen Feng device_type = "cpu"; 8035ca8168SChen Feng reg = <0x0 0x3>; 8135ca8168SChen Feng enable-method = "psci"; 8235ca8168SChen Feng }; 8335ca8168SChen Feng 8435ca8168SChen Feng cpu4: cpu@100 { 8535ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 8635ca8168SChen Feng device_type = "cpu"; 8735ca8168SChen Feng reg = <0x0 0x100>; 8835ca8168SChen Feng enable-method = "psci"; 8935ca8168SChen Feng }; 9035ca8168SChen Feng 9135ca8168SChen Feng cpu5: cpu@101 { 9235ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 9335ca8168SChen Feng device_type = "cpu"; 9435ca8168SChen Feng reg = <0x0 0x101>; 9535ca8168SChen Feng enable-method = "psci"; 9635ca8168SChen Feng }; 9735ca8168SChen Feng 9835ca8168SChen Feng cpu6: cpu@102 { 9935ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 10035ca8168SChen Feng device_type = "cpu"; 10135ca8168SChen Feng reg = <0x0 0x102>; 10235ca8168SChen Feng enable-method = "psci"; 10335ca8168SChen Feng }; 10435ca8168SChen Feng 10535ca8168SChen Feng cpu7: cpu@103 { 10635ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 10735ca8168SChen Feng device_type = "cpu"; 10835ca8168SChen Feng reg = <0x0 0x103>; 10935ca8168SChen Feng enable-method = "psci"; 11035ca8168SChen Feng }; 11135ca8168SChen Feng }; 11235ca8168SChen Feng 11335ca8168SChen Feng gic: interrupt-controller@e82b0000 { 11435ca8168SChen Feng compatible = "arm,gic-400"; 11535ca8168SChen Feng reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 11635ca8168SChen Feng <0x0 0xe82b2000 0 0x2000>, /* GICC */ 11735ca8168SChen Feng <0x0 0xe82b4000 0 0x2000>, /* GICH */ 11835ca8168SChen Feng <0x0 0xe82b6000 0 0x2000>; /* GICV */ 11935ca8168SChen Feng #address-cells = <0>; 12035ca8168SChen Feng #interrupt-cells = <3>; 12135ca8168SChen Feng interrupt-controller; 12235ca8168SChen Feng interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 12335ca8168SChen Feng IRQ_TYPE_LEVEL_HIGH)>; 12435ca8168SChen Feng }; 12535ca8168SChen Feng 12635ca8168SChen Feng timer { 12735ca8168SChen Feng compatible = "arm,armv8-timer"; 12835ca8168SChen Feng interrupt-parent = <&gic>; 12935ca8168SChen Feng interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 13035ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 13135ca8168SChen Feng <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 13235ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 13335ca8168SChen Feng <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 13435ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 13535ca8168SChen Feng <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 13635ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>; 13735ca8168SChen Feng }; 13835ca8168SChen Feng 13935ca8168SChen Feng soc { 14035ca8168SChen Feng compatible = "simple-bus"; 14135ca8168SChen Feng #address-cells = <2>; 14235ca8168SChen Feng #size-cells = <2>; 14335ca8168SChen Feng ranges; 14435ca8168SChen Feng 145a4e36ae0SZhangfei Gao crg_ctrl: crg_ctrl@fff35000 { 146a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-crgctrl", "syscon"; 147a4e36ae0SZhangfei Gao reg = <0x0 0xfff35000 0x0 0x1000>; 148a4e36ae0SZhangfei Gao #clock-cells = <1>; 14935ca8168SChen Feng }; 15035ca8168SChen Feng 151a4e36ae0SZhangfei Gao crg_rst: crg_rst_controller { 152a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 153a4e36ae0SZhangfei Gao #reset-cells = <2>; 154a4e36ae0SZhangfei Gao hisi,rst-syscon = <&crg_ctrl>; 155a4e36ae0SZhangfei Gao }; 156a4e36ae0SZhangfei Gao 157a4e36ae0SZhangfei Gao 158a4e36ae0SZhangfei Gao pctrl: pctrl@e8a09000 { 159a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pctrl", "syscon"; 160a4e36ae0SZhangfei Gao reg = <0x0 0xe8a09000 0x0 0x2000>; 161a4e36ae0SZhangfei Gao #clock-cells = <1>; 162a4e36ae0SZhangfei Gao }; 163a4e36ae0SZhangfei Gao 164a4e36ae0SZhangfei Gao pmuctrl: crg_ctrl@fff34000 { 165a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 166a4e36ae0SZhangfei Gao reg = <0x0 0xfff34000 0x0 0x1000>; 167a4e36ae0SZhangfei Gao #clock-cells = <1>; 168a4e36ae0SZhangfei Gao }; 169a4e36ae0SZhangfei Gao 170a4e36ae0SZhangfei Gao sctrl: sctrl@fff0a000 { 171a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-sctrl", "syscon"; 172a4e36ae0SZhangfei Gao reg = <0x0 0xfff0a000 0x0 0x1000>; 173a4e36ae0SZhangfei Gao #clock-cells = <1>; 174a4e36ae0SZhangfei Gao }; 175a4e36ae0SZhangfei Gao 176a4e36ae0SZhangfei Gao iomcu: iomcu@ffd7e000 { 177a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-iomcu", "syscon"; 178a4e36ae0SZhangfei Gao reg = <0x0 0xffd7e000 0x0 0x1000>; 179a4e36ae0SZhangfei Gao #clock-cells = <1>; 180a4e36ae0SZhangfei Gao 181a4e36ae0SZhangfei Gao }; 182a4e36ae0SZhangfei Gao 183a4e36ae0SZhangfei Gao iomcu_rst: reset { 184a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 185a4e36ae0SZhangfei Gao hisi,rst-syscon = <&iomcu>; 186a4e36ae0SZhangfei Gao #reset-cells = <2>; 187a4e36ae0SZhangfei Gao }; 188a4e36ae0SZhangfei Gao 18975196330SLeo Yan dual_timer0: timer@fff14000 { 19075196330SLeo Yan compatible = "arm,sp804", "arm,primecell"; 19175196330SLeo Yan reg = <0x0 0xfff14000 0x0 0x1000>; 19275196330SLeo Yan interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 19375196330SLeo Yan <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 19475196330SLeo Yan clocks = <&crg_ctrl HI3660_OSC32K>, 19575196330SLeo Yan <&crg_ctrl HI3660_OSC32K>, 19675196330SLeo Yan <&crg_ctrl HI3660_OSC32K>; 19775196330SLeo Yan clock-names = "timer1", "timer2", "apb_pclk"; 19875196330SLeo Yan }; 19975196330SLeo Yan 2005f8a3b77SZhangfei Gao i2c0: i2c@ffd71000 { 2015f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 2025f8a3b77SZhangfei Gao reg = <0x0 0xffd71000 0x0 0x1000>; 2035f8a3b77SZhangfei Gao interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2045f8a3b77SZhangfei Gao #address-cells = <1>; 2055f8a3b77SZhangfei Gao #size-cells = <0>; 2065f8a3b77SZhangfei Gao clock-frequency = <400000>; 2075f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 2085f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 3>; 2095f8a3b77SZhangfei Gao pinctrl-names = "default"; 2105f8a3b77SZhangfei Gao pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 2115f8a3b77SZhangfei Gao status = "disabled"; 2125f8a3b77SZhangfei Gao }; 2135f8a3b77SZhangfei Gao 2145f8a3b77SZhangfei Gao i2c1: i2c@ffd72000 { 2155f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 2165f8a3b77SZhangfei Gao reg = <0x0 0xffd72000 0x0 0x1000>; 2175f8a3b77SZhangfei Gao interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2185f8a3b77SZhangfei Gao #address-cells = <1>; 2195f8a3b77SZhangfei Gao #size-cells = <0>; 2205f8a3b77SZhangfei Gao clock-frequency = <400000>; 2215f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 2225f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 4>; 2235f8a3b77SZhangfei Gao pinctrl-names = "default"; 2245f8a3b77SZhangfei Gao pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 2255f8a3b77SZhangfei Gao status = "disabled"; 2265f8a3b77SZhangfei Gao }; 2275f8a3b77SZhangfei Gao 2285f8a3b77SZhangfei Gao i2c3: i2c@fdf0c000 { 2295f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 2305f8a3b77SZhangfei Gao reg = <0x0 0xfdf0c000 0x0 0x1000>; 2315f8a3b77SZhangfei Gao interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2325f8a3b77SZhangfei Gao #address-cells = <1>; 2335f8a3b77SZhangfei Gao #size-cells = <0>; 2345f8a3b77SZhangfei Gao clock-frequency = <400000>; 2355f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 2365f8a3b77SZhangfei Gao resets = <&crg_rst 0x78 7>; 2375f8a3b77SZhangfei Gao pinctrl-names = "default"; 2385f8a3b77SZhangfei Gao pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 2395f8a3b77SZhangfei Gao status = "disabled"; 2405f8a3b77SZhangfei Gao }; 2415f8a3b77SZhangfei Gao 2425f8a3b77SZhangfei Gao i2c7: i2c@fdf0b000 { 2435f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 2445f8a3b77SZhangfei Gao reg = <0x0 0xfdf0b000 0x0 0x1000>; 2455f8a3b77SZhangfei Gao interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 2465f8a3b77SZhangfei Gao #address-cells = <1>; 2475f8a3b77SZhangfei Gao #size-cells = <0>; 2485f8a3b77SZhangfei Gao clock-frequency = <400000>; 2495f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 2505f8a3b77SZhangfei Gao resets = <&crg_rst 0x60 14>; 2515f8a3b77SZhangfei Gao pinctrl-names = "default"; 2525f8a3b77SZhangfei Gao pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 2535f8a3b77SZhangfei Gao status = "disabled"; 2545f8a3b77SZhangfei Gao }; 2555f8a3b77SZhangfei Gao 256254b07b2SChen Feng uart0: serial@fdf02000 { 257254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 258254b07b2SChen Feng reg = <0x0 0xfdf02000 0x0 0x1000>; 259254b07b2SChen Feng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 260254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 261254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 262254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 263254b07b2SChen Feng pinctrl-names = "default"; 264254b07b2SChen Feng pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 265254b07b2SChen Feng status = "disabled"; 266254b07b2SChen Feng }; 267254b07b2SChen Feng 268254b07b2SChen Feng uart1: serial@fdf00000 { 269254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 270254b07b2SChen Feng reg = <0x0 0xfdf00000 0x0 0x1000>; 271254b07b2SChen Feng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 272254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 273254b07b2SChen Feng <&crg_ctrl HI3660_CLK_GATE_UART1>; 274254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 275254b07b2SChen Feng pinctrl-names = "default"; 276254b07b2SChen Feng pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 277254b07b2SChen Feng status = "disabled"; 278254b07b2SChen Feng }; 279254b07b2SChen Feng 280254b07b2SChen Feng uart2: serial@fdf03000 { 281254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 282254b07b2SChen Feng reg = <0x0 0xfdf03000 0x0 0x1000>; 283254b07b2SChen Feng interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 284254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 285254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 286254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 287254b07b2SChen Feng pinctrl-names = "default"; 288254b07b2SChen Feng pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 289254b07b2SChen Feng status = "disabled"; 290254b07b2SChen Feng }; 291254b07b2SChen Feng 292254b07b2SChen Feng uart3: serial@ffd74000 { 293254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 294254b07b2SChen Feng reg = <0x0 0xffd74000 0x0 0x1000>; 295254b07b2SChen Feng interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 296254b07b2SChen Feng clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 297254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 298254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 299254b07b2SChen Feng pinctrl-names = "default"; 300254b07b2SChen Feng pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 301254b07b2SChen Feng status = "disabled"; 302254b07b2SChen Feng }; 303254b07b2SChen Feng 304254b07b2SChen Feng uart4: serial@fdf01000 { 305254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 306254b07b2SChen Feng reg = <0x0 0xfdf01000 0x0 0x1000>; 307254b07b2SChen Feng interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 308254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 309254b07b2SChen Feng <&crg_ctrl HI3660_CLK_GATE_UART4>; 310254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 311254b07b2SChen Feng pinctrl-names = "default"; 312254b07b2SChen Feng pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 313254b07b2SChen Feng status = "disabled"; 314254b07b2SChen Feng }; 315254b07b2SChen Feng 316a4e36ae0SZhangfei Gao uart5: serial@fdf05000 { 31735ca8168SChen Feng compatible = "arm,pl011", "arm,primecell"; 31835ca8168SChen Feng reg = <0x0 0xfdf05000 0x0 0x1000>; 31935ca8168SChen Feng interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 320a4e36ae0SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 321a4e36ae0SZhangfei Gao <&crg_ctrl HI3660_CLK_GATE_UART5>; 32235ca8168SChen Feng clock-names = "uartclk", "apb_pclk"; 323254b07b2SChen Feng pinctrl-names = "default"; 324254b07b2SChen Feng pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 325254b07b2SChen Feng status = "disabled"; 326254b07b2SChen Feng }; 327254b07b2SChen Feng 328254b07b2SChen Feng uart6: serial@fff32000 { 329254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 330254b07b2SChen Feng reg = <0x0 0xfff32000 0x0 0x1000>; 331254b07b2SChen Feng interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 332254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_UART6>, 333254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 334254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 335254b07b2SChen Feng pinctrl-names = "default"; 336254b07b2SChen Feng pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 33735ca8168SChen Feng status = "disabled"; 33835ca8168SChen Feng }; 339d94eab86SWang Xiaoyin 3400a0698f6SChen Feng rtc0: rtc@fff04000 { 3410a0698f6SChen Feng compatible = "arm,pl031", "arm,primecell"; 3420a0698f6SChen Feng reg = <0x0 0Xfff04000 0x0 0x1000>; 3430a0698f6SChen Feng interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 3440a0698f6SChen Feng clocks = <&crg_ctrl HI3660_PCLK>; 3450a0698f6SChen Feng clock-names = "apb_pclk"; 3460a0698f6SChen Feng }; 3470a0698f6SChen Feng 348d94eab86SWang Xiaoyin gpio0: gpio@e8a0b000 { 349d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 350d94eab86SWang Xiaoyin reg = <0 0xe8a0b000 0 0x1000>; 351d94eab86SWang Xiaoyin interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 352d94eab86SWang Xiaoyin gpio-controller; 353d94eab86SWang Xiaoyin #gpio-cells = <2>; 354d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 0 7>; 355d94eab86SWang Xiaoyin interrupt-controller; 356d94eab86SWang Xiaoyin #interrupt-cells = <2>; 357d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 358d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 359d94eab86SWang Xiaoyin }; 360d94eab86SWang Xiaoyin 361d94eab86SWang Xiaoyin gpio1: gpio@e8a0c000 { 362d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 363d94eab86SWang Xiaoyin reg = <0 0xe8a0c000 0 0x1000>; 364d94eab86SWang Xiaoyin interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 365d94eab86SWang Xiaoyin gpio-controller; 366d94eab86SWang Xiaoyin #gpio-cells = <2>; 367d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 7 7>; 368d94eab86SWang Xiaoyin interrupt-controller; 369d94eab86SWang Xiaoyin #interrupt-cells = <2>; 370d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 371d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 372d94eab86SWang Xiaoyin }; 373d94eab86SWang Xiaoyin 374d94eab86SWang Xiaoyin gpio2: gpio@e8a0d000 { 375d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 376d94eab86SWang Xiaoyin reg = <0 0xe8a0d000 0 0x1000>; 377d94eab86SWang Xiaoyin interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 378d94eab86SWang Xiaoyin gpio-controller; 379d94eab86SWang Xiaoyin #gpio-cells = <2>; 380d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 14 8>; 381d94eab86SWang Xiaoyin interrupt-controller; 382d94eab86SWang Xiaoyin #interrupt-cells = <2>; 383d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 384d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 385d94eab86SWang Xiaoyin }; 386d94eab86SWang Xiaoyin 387d94eab86SWang Xiaoyin gpio3: gpio@e8a0e000 { 388d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 389d94eab86SWang Xiaoyin reg = <0 0xe8a0e000 0 0x1000>; 390d94eab86SWang Xiaoyin interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 391d94eab86SWang Xiaoyin gpio-controller; 392d94eab86SWang Xiaoyin #gpio-cells = <2>; 393d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 22 8>; 394d94eab86SWang Xiaoyin interrupt-controller; 395d94eab86SWang Xiaoyin #interrupt-cells = <2>; 396d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 397d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 398d94eab86SWang Xiaoyin }; 399d94eab86SWang Xiaoyin 400d94eab86SWang Xiaoyin gpio4: gpio@e8a0f000 { 401d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 402d94eab86SWang Xiaoyin reg = <0 0xe8a0f000 0 0x1000>; 403d94eab86SWang Xiaoyin interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 404d94eab86SWang Xiaoyin gpio-controller; 405d94eab86SWang Xiaoyin #gpio-cells = <2>; 406d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 30 8>; 407d94eab86SWang Xiaoyin interrupt-controller; 408d94eab86SWang Xiaoyin #interrupt-cells = <2>; 409d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 410d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 411d94eab86SWang Xiaoyin }; 412d94eab86SWang Xiaoyin 413d94eab86SWang Xiaoyin gpio5: gpio@e8a10000 { 414d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 415d94eab86SWang Xiaoyin reg = <0 0xe8a10000 0 0x1000>; 416d94eab86SWang Xiaoyin interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 417d94eab86SWang Xiaoyin gpio-controller; 418d94eab86SWang Xiaoyin #gpio-cells = <2>; 419d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 38 8>; 420d94eab86SWang Xiaoyin interrupt-controller; 421d94eab86SWang Xiaoyin #interrupt-cells = <2>; 422d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 423d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 424d94eab86SWang Xiaoyin }; 425d94eab86SWang Xiaoyin 426d94eab86SWang Xiaoyin gpio6: gpio@e8a11000 { 427d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 428d94eab86SWang Xiaoyin reg = <0 0xe8a11000 0 0x1000>; 429d94eab86SWang Xiaoyin interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 430d94eab86SWang Xiaoyin gpio-controller; 431d94eab86SWang Xiaoyin #gpio-cells = <2>; 432d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 46 8>; 433d94eab86SWang Xiaoyin interrupt-controller; 434d94eab86SWang Xiaoyin #interrupt-cells = <2>; 435d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 436d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 437d94eab86SWang Xiaoyin }; 438d94eab86SWang Xiaoyin 439d94eab86SWang Xiaoyin gpio7: gpio@e8a12000 { 440d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 441d94eab86SWang Xiaoyin reg = <0 0xe8a12000 0 0x1000>; 442d94eab86SWang Xiaoyin interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 443d94eab86SWang Xiaoyin gpio-controller; 444d94eab86SWang Xiaoyin #gpio-cells = <2>; 445d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 54 8>; 446d94eab86SWang Xiaoyin interrupt-controller; 447d94eab86SWang Xiaoyin #interrupt-cells = <2>; 448d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 449d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 450d94eab86SWang Xiaoyin }; 451d94eab86SWang Xiaoyin 452d94eab86SWang Xiaoyin gpio8: gpio@e8a13000 { 453d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 454d94eab86SWang Xiaoyin reg = <0 0xe8a13000 0 0x1000>; 455d94eab86SWang Xiaoyin interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 456d94eab86SWang Xiaoyin gpio-controller; 457d94eab86SWang Xiaoyin #gpio-cells = <2>; 458d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 62 8>; 459d94eab86SWang Xiaoyin interrupt-controller; 460d94eab86SWang Xiaoyin #interrupt-cells = <2>; 461d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 462d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 463d94eab86SWang Xiaoyin }; 464d94eab86SWang Xiaoyin 465d94eab86SWang Xiaoyin gpio9: gpio@e8a14000 { 466d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 467d94eab86SWang Xiaoyin reg = <0 0xe8a14000 0 0x1000>; 468d94eab86SWang Xiaoyin interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 469d94eab86SWang Xiaoyin gpio-controller; 470d94eab86SWang Xiaoyin #gpio-cells = <2>; 471d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 70 8>; 472d94eab86SWang Xiaoyin interrupt-controller; 473d94eab86SWang Xiaoyin #interrupt-cells = <2>; 474d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 475d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 476d94eab86SWang Xiaoyin }; 477d94eab86SWang Xiaoyin 478d94eab86SWang Xiaoyin gpio10: gpio@e8a15000 { 479d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 480d94eab86SWang Xiaoyin reg = <0 0xe8a15000 0 0x1000>; 481d94eab86SWang Xiaoyin interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 482d94eab86SWang Xiaoyin gpio-controller; 483d94eab86SWang Xiaoyin #gpio-cells = <2>; 484d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 78 8>; 485d94eab86SWang Xiaoyin interrupt-controller; 486d94eab86SWang Xiaoyin #interrupt-cells = <2>; 487d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 488d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 489d94eab86SWang Xiaoyin }; 490d94eab86SWang Xiaoyin 491d94eab86SWang Xiaoyin gpio11: gpio@e8a16000 { 492d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 493d94eab86SWang Xiaoyin reg = <0 0xe8a16000 0 0x1000>; 494d94eab86SWang Xiaoyin interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 495d94eab86SWang Xiaoyin gpio-controller; 496d94eab86SWang Xiaoyin #gpio-cells = <2>; 497d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 86 8>; 498d94eab86SWang Xiaoyin interrupt-controller; 499d94eab86SWang Xiaoyin #interrupt-cells = <2>; 500d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 501d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 502d94eab86SWang Xiaoyin }; 503d94eab86SWang Xiaoyin 504d94eab86SWang Xiaoyin gpio12: gpio@e8a17000 { 505d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 506d94eab86SWang Xiaoyin reg = <0 0xe8a17000 0 0x1000>; 507d94eab86SWang Xiaoyin interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 508d94eab86SWang Xiaoyin gpio-controller; 509d94eab86SWang Xiaoyin #gpio-cells = <2>; 510d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 511d94eab86SWang Xiaoyin interrupt-controller; 512d94eab86SWang Xiaoyin #interrupt-cells = <2>; 513d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 514d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 515d94eab86SWang Xiaoyin }; 516d94eab86SWang Xiaoyin 517d94eab86SWang Xiaoyin gpio13: gpio@e8a18000 { 518d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 519d94eab86SWang Xiaoyin reg = <0 0xe8a18000 0 0x1000>; 520d94eab86SWang Xiaoyin interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 521d94eab86SWang Xiaoyin gpio-controller; 522d94eab86SWang Xiaoyin #gpio-cells = <2>; 523d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 102 8>; 524d94eab86SWang Xiaoyin interrupt-controller; 525d94eab86SWang Xiaoyin #interrupt-cells = <2>; 526d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 527d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 528d94eab86SWang Xiaoyin }; 529d94eab86SWang Xiaoyin 530d94eab86SWang Xiaoyin gpio14: gpio@e8a19000 { 531d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 532d94eab86SWang Xiaoyin reg = <0 0xe8a19000 0 0x1000>; 533d94eab86SWang Xiaoyin interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 534d94eab86SWang Xiaoyin gpio-controller; 535d94eab86SWang Xiaoyin #gpio-cells = <2>; 536d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 110 8>; 537d94eab86SWang Xiaoyin interrupt-controller; 538d94eab86SWang Xiaoyin #interrupt-cells = <2>; 539d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 540d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 541d94eab86SWang Xiaoyin }; 542d94eab86SWang Xiaoyin 543d94eab86SWang Xiaoyin gpio15: gpio@e8a1a000 { 544d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 545d94eab86SWang Xiaoyin reg = <0 0xe8a1a000 0 0x1000>; 546d94eab86SWang Xiaoyin interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 547d94eab86SWang Xiaoyin gpio-controller; 548d94eab86SWang Xiaoyin #gpio-cells = <2>; 549d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 118 6>; 550d94eab86SWang Xiaoyin interrupt-controller; 551d94eab86SWang Xiaoyin #interrupt-cells = <2>; 552d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 553d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 554d94eab86SWang Xiaoyin }; 555d94eab86SWang Xiaoyin 556d94eab86SWang Xiaoyin gpio16: gpio@e8a1b000 { 557d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 558d94eab86SWang Xiaoyin reg = <0 0xe8a1b000 0 0x1000>; 559d94eab86SWang Xiaoyin interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 560d94eab86SWang Xiaoyin gpio-controller; 561d94eab86SWang Xiaoyin #gpio-cells = <2>; 562d94eab86SWang Xiaoyin interrupt-controller; 563d94eab86SWang Xiaoyin #interrupt-cells = <2>; 564d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 565d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 566d94eab86SWang Xiaoyin }; 567d94eab86SWang Xiaoyin 568d94eab86SWang Xiaoyin gpio17: gpio@e8a1c000 { 569d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 570d94eab86SWang Xiaoyin reg = <0 0xe8a1c000 0 0x1000>; 571d94eab86SWang Xiaoyin interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 572d94eab86SWang Xiaoyin gpio-controller; 573d94eab86SWang Xiaoyin #gpio-cells = <2>; 574d94eab86SWang Xiaoyin interrupt-controller; 575d94eab86SWang Xiaoyin #interrupt-cells = <2>; 576d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 577d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 578d94eab86SWang Xiaoyin }; 579d94eab86SWang Xiaoyin 580d94eab86SWang Xiaoyin gpio18: gpio@ff3b4000 { 581d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 582d94eab86SWang Xiaoyin reg = <0 0xff3b4000 0 0x1000>; 583d94eab86SWang Xiaoyin interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 584d94eab86SWang Xiaoyin gpio-controller; 585d94eab86SWang Xiaoyin #gpio-cells = <2>; 586d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 0 8>; 587d94eab86SWang Xiaoyin interrupt-controller; 588d94eab86SWang Xiaoyin #interrupt-cells = <2>; 589d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 590d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 591d94eab86SWang Xiaoyin }; 592d94eab86SWang Xiaoyin 593d94eab86SWang Xiaoyin gpio19: gpio@ff3b5000 { 594d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 595d94eab86SWang Xiaoyin reg = <0 0xff3b5000 0 0x1000>; 596d94eab86SWang Xiaoyin interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 597d94eab86SWang Xiaoyin gpio-controller; 598d94eab86SWang Xiaoyin #gpio-cells = <2>; 599d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 8 4>; 600d94eab86SWang Xiaoyin interrupt-controller; 601d94eab86SWang Xiaoyin #interrupt-cells = <2>; 602d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 603d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 604d94eab86SWang Xiaoyin }; 605d94eab86SWang Xiaoyin 606d94eab86SWang Xiaoyin gpio20: gpio@e8a1f000 { 607d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 608d94eab86SWang Xiaoyin reg = <0 0xe8a1f000 0 0x1000>; 609d94eab86SWang Xiaoyin interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 610d94eab86SWang Xiaoyin gpio-controller; 611d94eab86SWang Xiaoyin #gpio-cells = <2>; 612d94eab86SWang Xiaoyin gpio-ranges = <&pmx1 0 0 6>; 613d94eab86SWang Xiaoyin interrupt-controller; 614d94eab86SWang Xiaoyin #interrupt-cells = <2>; 615d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 616d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 617d94eab86SWang Xiaoyin }; 618d94eab86SWang Xiaoyin 619d94eab86SWang Xiaoyin gpio21: gpio@e8a20000 { 620d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 621d94eab86SWang Xiaoyin reg = <0 0xe8a20000 0 0x1000>; 622d94eab86SWang Xiaoyin interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 623d94eab86SWang Xiaoyin gpio-controller; 624d94eab86SWang Xiaoyin #gpio-cells = <2>; 625d94eab86SWang Xiaoyin interrupt-controller; 626d94eab86SWang Xiaoyin #interrupt-cells = <2>; 627d94eab86SWang Xiaoyin gpio-ranges = <&pmx3 0 0 6>; 628d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 629d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 630d94eab86SWang Xiaoyin }; 631d94eab86SWang Xiaoyin 632d94eab86SWang Xiaoyin gpio22: gpio@fff0b000 { 633d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 634d94eab86SWang Xiaoyin reg = <0 0xfff0b000 0 0x1000>; 635d94eab86SWang Xiaoyin interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 636d94eab86SWang Xiaoyin gpio-controller; 637d94eab86SWang Xiaoyin #gpio-cells = <2>; 638d94eab86SWang Xiaoyin /* GPIO176 */ 639d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 2 0 6>; 640d94eab86SWang Xiaoyin interrupt-controller; 641d94eab86SWang Xiaoyin #interrupt-cells = <2>; 642d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 643d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 644d94eab86SWang Xiaoyin }; 645d94eab86SWang Xiaoyin 646d94eab86SWang Xiaoyin gpio23: gpio@fff0c000 { 647d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 648d94eab86SWang Xiaoyin reg = <0 0xfff0c000 0 0x1000>; 649d94eab86SWang Xiaoyin interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 650d94eab86SWang Xiaoyin gpio-controller; 651d94eab86SWang Xiaoyin #gpio-cells = <2>; 652d94eab86SWang Xiaoyin /* GPIO184 */ 653d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 6 7>; 654d94eab86SWang Xiaoyin interrupt-controller; 655d94eab86SWang Xiaoyin #interrupt-cells = <2>; 656d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 657d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 658d94eab86SWang Xiaoyin }; 659d94eab86SWang Xiaoyin 660d94eab86SWang Xiaoyin gpio24: gpio@fff0d000 { 661d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 662d94eab86SWang Xiaoyin reg = <0 0xfff0d000 0 0x1000>; 663d94eab86SWang Xiaoyin interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 664d94eab86SWang Xiaoyin gpio-controller; 665d94eab86SWang Xiaoyin #gpio-cells = <2>; 666d94eab86SWang Xiaoyin /* GPIO192 */ 667d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 13 8>; 668d94eab86SWang Xiaoyin interrupt-controller; 669d94eab86SWang Xiaoyin #interrupt-cells = <2>; 670d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 671d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 672d94eab86SWang Xiaoyin }; 673d94eab86SWang Xiaoyin 674d94eab86SWang Xiaoyin gpio25: gpio@fff0e000 { 675d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 676d94eab86SWang Xiaoyin reg = <0 0xfff0e000 0 0x1000>; 677d94eab86SWang Xiaoyin interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 678d94eab86SWang Xiaoyin gpio-controller; 679d94eab86SWang Xiaoyin #gpio-cells = <2>; 680d94eab86SWang Xiaoyin /* GPIO200 */ 681d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 682d94eab86SWang Xiaoyin interrupt-controller; 683d94eab86SWang Xiaoyin #interrupt-cells = <2>; 684d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 685d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 686d94eab86SWang Xiaoyin }; 687d94eab86SWang Xiaoyin 688d94eab86SWang Xiaoyin gpio26: gpio@fff0f000 { 689d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 690d94eab86SWang Xiaoyin reg = <0 0xfff0f000 0 0x1000>; 691d94eab86SWang Xiaoyin interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 692d94eab86SWang Xiaoyin gpio-controller; 693d94eab86SWang Xiaoyin #gpio-cells = <2>; 694d94eab86SWang Xiaoyin /* GPIO208 */ 695d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 28 8>; 696d94eab86SWang Xiaoyin interrupt-controller; 697d94eab86SWang Xiaoyin #interrupt-cells = <2>; 698d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 699d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 700d94eab86SWang Xiaoyin }; 701d94eab86SWang Xiaoyin 702d94eab86SWang Xiaoyin gpio27: gpio@fff10000 { 703d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 704d94eab86SWang Xiaoyin reg = <0 0xfff10000 0 0x1000>; 705d94eab86SWang Xiaoyin interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 706d94eab86SWang Xiaoyin gpio-controller; 707d94eab86SWang Xiaoyin #gpio-cells = <2>; 708d94eab86SWang Xiaoyin /* GPIO216 */ 709d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 36 6>; 710d94eab86SWang Xiaoyin interrupt-controller; 711d94eab86SWang Xiaoyin #interrupt-cells = <2>; 712d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 713d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 714d94eab86SWang Xiaoyin }; 715d94eab86SWang Xiaoyin 716d94eab86SWang Xiaoyin gpio28: gpio@fff1d000 { 717d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 718d94eab86SWang Xiaoyin reg = <0 0xfff1d000 0 0x1000>; 719d94eab86SWang Xiaoyin interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 720d94eab86SWang Xiaoyin gpio-controller; 721d94eab86SWang Xiaoyin #gpio-cells = <2>; 722d94eab86SWang Xiaoyin interrupt-controller; 723d94eab86SWang Xiaoyin #interrupt-cells = <2>; 724d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 725d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 726d94eab86SWang Xiaoyin }; 72738810497SWang Xiaoyin 72838810497SWang Xiaoyin spi2: spi@ffd68000 { 72938810497SWang Xiaoyin compatible = "arm,pl022", "arm,primecell"; 73038810497SWang Xiaoyin reg = <0x0 0xffd68000 0x0 0x1000>; 73138810497SWang Xiaoyin #address-cells = <1>; 73238810497SWang Xiaoyin #size-cells = <0>; 73338810497SWang Xiaoyin interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 73438810497SWang Xiaoyin clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; 73538810497SWang Xiaoyin clock-names = "apb_pclk"; 73638810497SWang Xiaoyin pinctrl-names = "default"; 73738810497SWang Xiaoyin pinctrl-0 = <&spi2_pmx_func>; 73838810497SWang Xiaoyin num-cs = <1>; 73938810497SWang Xiaoyin cs-gpios = <&gpio27 2 0>; 74038810497SWang Xiaoyin status = "disabled"; 74138810497SWang Xiaoyin }; 74238810497SWang Xiaoyin 74338810497SWang Xiaoyin spi3: spi@ff3b3000 { 74438810497SWang Xiaoyin compatible = "arm,pl022", "arm,primecell"; 74538810497SWang Xiaoyin reg = <0x0 0xff3b3000 0x0 0x1000>; 74638810497SWang Xiaoyin #address-cells = <1>; 74738810497SWang Xiaoyin #size-cells = <0>; 74838810497SWang Xiaoyin interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 74938810497SWang Xiaoyin clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; 75038810497SWang Xiaoyin clock-names = "apb_pclk"; 75138810497SWang Xiaoyin pinctrl-names = "default"; 75238810497SWang Xiaoyin pinctrl-0 = <&spi3_pmx_func>; 75338810497SWang Xiaoyin num-cs = <1>; 75438810497SWang Xiaoyin cs-gpios = <&gpio18 5 0>; 75538810497SWang Xiaoyin status = "disabled"; 75638810497SWang Xiaoyin }; 75735ca8168SChen Feng }; 75835ca8168SChen Feng}; 759