135ca8168SChen Feng/* 235ca8168SChen Feng * dts file for Hisilicon Hi3660 SoC 335ca8168SChen Feng * 435ca8168SChen Feng * Copyright (C) 2016, Hisilicon Ltd. 535ca8168SChen Feng */ 635ca8168SChen Feng 735ca8168SChen Feng#include <dt-bindings/interrupt-controller/arm-gic.h> 8a4e36ae0SZhangfei Gao#include <dt-bindings/clock/hi3660-clock.h> 935ca8168SChen Feng 1035ca8168SChen Feng/ { 1135ca8168SChen Feng compatible = "hisilicon,hi3660"; 1235ca8168SChen Feng interrupt-parent = <&gic>; 1335ca8168SChen Feng #address-cells = <2>; 1435ca8168SChen Feng #size-cells = <2>; 1535ca8168SChen Feng 1635ca8168SChen Feng psci { 1735ca8168SChen Feng compatible = "arm,psci-0.2"; 1835ca8168SChen Feng method = "smc"; 1935ca8168SChen Feng }; 2035ca8168SChen Feng 2135ca8168SChen Feng cpus { 2235ca8168SChen Feng #address-cells = <2>; 2335ca8168SChen Feng #size-cells = <0>; 2435ca8168SChen Feng 2535ca8168SChen Feng cpu-map { 2635ca8168SChen Feng cluster0 { 2735ca8168SChen Feng core0 { 2835ca8168SChen Feng cpu = <&cpu0>; 2935ca8168SChen Feng }; 3035ca8168SChen Feng core1 { 3135ca8168SChen Feng cpu = <&cpu1>; 3235ca8168SChen Feng }; 3335ca8168SChen Feng core2 { 3435ca8168SChen Feng cpu = <&cpu2>; 3535ca8168SChen Feng }; 3635ca8168SChen Feng core3 { 3735ca8168SChen Feng cpu = <&cpu3>; 3835ca8168SChen Feng }; 3935ca8168SChen Feng }; 4035ca8168SChen Feng cluster1 { 4135ca8168SChen Feng core0 { 4235ca8168SChen Feng cpu = <&cpu4>; 4335ca8168SChen Feng }; 4435ca8168SChen Feng core1 { 4535ca8168SChen Feng cpu = <&cpu5>; 4635ca8168SChen Feng }; 4735ca8168SChen Feng core2 { 4835ca8168SChen Feng cpu = <&cpu6>; 4935ca8168SChen Feng }; 5035ca8168SChen Feng core3 { 5135ca8168SChen Feng cpu = <&cpu7>; 5235ca8168SChen Feng }; 5335ca8168SChen Feng }; 5435ca8168SChen Feng }; 5535ca8168SChen Feng 5635ca8168SChen Feng cpu0: cpu@0 { 5735ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 5835ca8168SChen Feng device_type = "cpu"; 5935ca8168SChen Feng reg = <0x0 0x0>; 6035ca8168SChen Feng enable-method = "psci"; 6135ca8168SChen Feng }; 6235ca8168SChen Feng 6335ca8168SChen Feng cpu1: cpu@1 { 6435ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 6535ca8168SChen Feng device_type = "cpu"; 6635ca8168SChen Feng reg = <0x0 0x1>; 6735ca8168SChen Feng enable-method = "psci"; 6835ca8168SChen Feng }; 6935ca8168SChen Feng 7035ca8168SChen Feng cpu2: cpu@2 { 7135ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 7235ca8168SChen Feng device_type = "cpu"; 7335ca8168SChen Feng reg = <0x0 0x2>; 7435ca8168SChen Feng enable-method = "psci"; 7535ca8168SChen Feng }; 7635ca8168SChen Feng 7735ca8168SChen Feng cpu3: cpu@3 { 7835ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 7935ca8168SChen Feng device_type = "cpu"; 8035ca8168SChen Feng reg = <0x0 0x3>; 8135ca8168SChen Feng enable-method = "psci"; 8235ca8168SChen Feng }; 8335ca8168SChen Feng 8435ca8168SChen Feng cpu4: cpu@100 { 8535ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 8635ca8168SChen Feng device_type = "cpu"; 8735ca8168SChen Feng reg = <0x0 0x100>; 8835ca8168SChen Feng enable-method = "psci"; 8935ca8168SChen Feng }; 9035ca8168SChen Feng 9135ca8168SChen Feng cpu5: cpu@101 { 9235ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 9335ca8168SChen Feng device_type = "cpu"; 9435ca8168SChen Feng reg = <0x0 0x101>; 9535ca8168SChen Feng enable-method = "psci"; 9635ca8168SChen Feng }; 9735ca8168SChen Feng 9835ca8168SChen Feng cpu6: cpu@102 { 9935ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 10035ca8168SChen Feng device_type = "cpu"; 10135ca8168SChen Feng reg = <0x0 0x102>; 10235ca8168SChen Feng enable-method = "psci"; 10335ca8168SChen Feng }; 10435ca8168SChen Feng 10535ca8168SChen Feng cpu7: cpu@103 { 10635ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 10735ca8168SChen Feng device_type = "cpu"; 10835ca8168SChen Feng reg = <0x0 0x103>; 10935ca8168SChen Feng enable-method = "psci"; 11035ca8168SChen Feng }; 11135ca8168SChen Feng }; 11235ca8168SChen Feng 11335ca8168SChen Feng gic: interrupt-controller@e82b0000 { 11435ca8168SChen Feng compatible = "arm,gic-400"; 11535ca8168SChen Feng reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 11635ca8168SChen Feng <0x0 0xe82b2000 0 0x2000>, /* GICC */ 11735ca8168SChen Feng <0x0 0xe82b4000 0 0x2000>, /* GICH */ 11835ca8168SChen Feng <0x0 0xe82b6000 0 0x2000>; /* GICV */ 11935ca8168SChen Feng #address-cells = <0>; 12035ca8168SChen Feng #interrupt-cells = <3>; 12135ca8168SChen Feng interrupt-controller; 12235ca8168SChen Feng interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 12335ca8168SChen Feng IRQ_TYPE_LEVEL_HIGH)>; 12435ca8168SChen Feng }; 12535ca8168SChen Feng 12635ca8168SChen Feng timer { 12735ca8168SChen Feng compatible = "arm,armv8-timer"; 12835ca8168SChen Feng interrupt-parent = <&gic>; 12935ca8168SChen Feng interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 13035ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 13135ca8168SChen Feng <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 13235ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 13335ca8168SChen Feng <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 13435ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 13535ca8168SChen Feng <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 13635ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>; 13735ca8168SChen Feng }; 13835ca8168SChen Feng 13935ca8168SChen Feng soc { 14035ca8168SChen Feng compatible = "simple-bus"; 14135ca8168SChen Feng #address-cells = <2>; 14235ca8168SChen Feng #size-cells = <2>; 14335ca8168SChen Feng ranges; 14435ca8168SChen Feng 145a4e36ae0SZhangfei Gao crg_ctrl: crg_ctrl@fff35000 { 146a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-crgctrl", "syscon"; 147a4e36ae0SZhangfei Gao reg = <0x0 0xfff35000 0x0 0x1000>; 148a4e36ae0SZhangfei Gao #clock-cells = <1>; 14935ca8168SChen Feng }; 15035ca8168SChen Feng 151a4e36ae0SZhangfei Gao crg_rst: crg_rst_controller { 152a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 153a4e36ae0SZhangfei Gao #reset-cells = <2>; 154a4e36ae0SZhangfei Gao hisi,rst-syscon = <&crg_ctrl>; 155a4e36ae0SZhangfei Gao }; 156a4e36ae0SZhangfei Gao 157a4e36ae0SZhangfei Gao 158a4e36ae0SZhangfei Gao pctrl: pctrl@e8a09000 { 159a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pctrl", "syscon"; 160a4e36ae0SZhangfei Gao reg = <0x0 0xe8a09000 0x0 0x2000>; 161a4e36ae0SZhangfei Gao #clock-cells = <1>; 162a4e36ae0SZhangfei Gao }; 163a4e36ae0SZhangfei Gao 164a4e36ae0SZhangfei Gao pmuctrl: crg_ctrl@fff34000 { 165a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 166a4e36ae0SZhangfei Gao reg = <0x0 0xfff34000 0x0 0x1000>; 167a4e36ae0SZhangfei Gao #clock-cells = <1>; 168a4e36ae0SZhangfei Gao }; 169a4e36ae0SZhangfei Gao 170a4e36ae0SZhangfei Gao sctrl: sctrl@fff0a000 { 171a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-sctrl", "syscon"; 172a4e36ae0SZhangfei Gao reg = <0x0 0xfff0a000 0x0 0x1000>; 173a4e36ae0SZhangfei Gao #clock-cells = <1>; 174a4e36ae0SZhangfei Gao }; 175a4e36ae0SZhangfei Gao 176a4e36ae0SZhangfei Gao iomcu: iomcu@ffd7e000 { 177a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-iomcu", "syscon"; 178a4e36ae0SZhangfei Gao reg = <0x0 0xffd7e000 0x0 0x1000>; 179a4e36ae0SZhangfei Gao #clock-cells = <1>; 180a4e36ae0SZhangfei Gao 181a4e36ae0SZhangfei Gao }; 182a4e36ae0SZhangfei Gao 183a4e36ae0SZhangfei Gao iomcu_rst: reset { 184a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 185a4e36ae0SZhangfei Gao hisi,rst-syscon = <&iomcu>; 186a4e36ae0SZhangfei Gao #reset-cells = <2>; 187a4e36ae0SZhangfei Gao }; 188a4e36ae0SZhangfei Gao 1895f8a3b77SZhangfei Gao i2c0: i2c@ffd71000 { 1905f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 1915f8a3b77SZhangfei Gao reg = <0x0 0xffd71000 0x0 0x1000>; 1925f8a3b77SZhangfei Gao interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1935f8a3b77SZhangfei Gao #address-cells = <1>; 1945f8a3b77SZhangfei Gao #size-cells = <0>; 1955f8a3b77SZhangfei Gao clock-frequency = <400000>; 1965f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 1975f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 3>; 1985f8a3b77SZhangfei Gao pinctrl-names = "default"; 1995f8a3b77SZhangfei Gao pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 2005f8a3b77SZhangfei Gao status = "disabled"; 2015f8a3b77SZhangfei Gao }; 2025f8a3b77SZhangfei Gao 2035f8a3b77SZhangfei Gao i2c1: i2c@ffd72000 { 2045f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 2055f8a3b77SZhangfei Gao reg = <0x0 0xffd72000 0x0 0x1000>; 2065f8a3b77SZhangfei Gao interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2075f8a3b77SZhangfei Gao #address-cells = <1>; 2085f8a3b77SZhangfei Gao #size-cells = <0>; 2095f8a3b77SZhangfei Gao clock-frequency = <400000>; 2105f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 2115f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 4>; 2125f8a3b77SZhangfei Gao pinctrl-names = "default"; 2135f8a3b77SZhangfei Gao pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 2145f8a3b77SZhangfei Gao status = "disabled"; 2155f8a3b77SZhangfei Gao }; 2165f8a3b77SZhangfei Gao 2175f8a3b77SZhangfei Gao i2c3: i2c@fdf0c000 { 2185f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 2195f8a3b77SZhangfei Gao reg = <0x0 0xfdf0c000 0x0 0x1000>; 2205f8a3b77SZhangfei Gao interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2215f8a3b77SZhangfei Gao #address-cells = <1>; 2225f8a3b77SZhangfei Gao #size-cells = <0>; 2235f8a3b77SZhangfei Gao clock-frequency = <400000>; 2245f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 2255f8a3b77SZhangfei Gao resets = <&crg_rst 0x78 7>; 2265f8a3b77SZhangfei Gao pinctrl-names = "default"; 2275f8a3b77SZhangfei Gao pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 2285f8a3b77SZhangfei Gao status = "disabled"; 2295f8a3b77SZhangfei Gao }; 2305f8a3b77SZhangfei Gao 2315f8a3b77SZhangfei Gao i2c7: i2c@fdf0b000 { 2325f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 2335f8a3b77SZhangfei Gao reg = <0x0 0xfdf0b000 0x0 0x1000>; 2345f8a3b77SZhangfei Gao interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 2355f8a3b77SZhangfei Gao #address-cells = <1>; 2365f8a3b77SZhangfei Gao #size-cells = <0>; 2375f8a3b77SZhangfei Gao clock-frequency = <400000>; 2385f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 2395f8a3b77SZhangfei Gao resets = <&crg_rst 0x60 14>; 2405f8a3b77SZhangfei Gao pinctrl-names = "default"; 2415f8a3b77SZhangfei Gao pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 2425f8a3b77SZhangfei Gao status = "disabled"; 2435f8a3b77SZhangfei Gao }; 2445f8a3b77SZhangfei Gao 245254b07b2SChen Feng uart0: serial@fdf02000 { 246254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 247254b07b2SChen Feng reg = <0x0 0xfdf02000 0x0 0x1000>; 248254b07b2SChen Feng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 249254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 250254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 251254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 252254b07b2SChen Feng pinctrl-names = "default"; 253254b07b2SChen Feng pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 254254b07b2SChen Feng status = "disabled"; 255254b07b2SChen Feng }; 256254b07b2SChen Feng 257254b07b2SChen Feng uart1: serial@fdf00000 { 258254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 259254b07b2SChen Feng reg = <0x0 0xfdf00000 0x0 0x1000>; 260254b07b2SChen Feng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 261254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 262254b07b2SChen Feng <&crg_ctrl HI3660_CLK_GATE_UART1>; 263254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 264254b07b2SChen Feng pinctrl-names = "default"; 265254b07b2SChen Feng pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 266254b07b2SChen Feng status = "disabled"; 267254b07b2SChen Feng }; 268254b07b2SChen Feng 269254b07b2SChen Feng uart2: serial@fdf03000 { 270254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 271254b07b2SChen Feng reg = <0x0 0xfdf03000 0x0 0x1000>; 272254b07b2SChen Feng interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 273254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 274254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 275254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 276254b07b2SChen Feng pinctrl-names = "default"; 277254b07b2SChen Feng pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 278254b07b2SChen Feng status = "disabled"; 279254b07b2SChen Feng }; 280254b07b2SChen Feng 281254b07b2SChen Feng uart3: serial@ffd74000 { 282254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 283254b07b2SChen Feng reg = <0x0 0xffd74000 0x0 0x1000>; 284254b07b2SChen Feng interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 285254b07b2SChen Feng clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 286254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 287254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 288254b07b2SChen Feng pinctrl-names = "default"; 289254b07b2SChen Feng pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 290254b07b2SChen Feng status = "disabled"; 291254b07b2SChen Feng }; 292254b07b2SChen Feng 293254b07b2SChen Feng uart4: serial@fdf01000 { 294254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 295254b07b2SChen Feng reg = <0x0 0xfdf01000 0x0 0x1000>; 296254b07b2SChen Feng interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 297254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 298254b07b2SChen Feng <&crg_ctrl HI3660_CLK_GATE_UART4>; 299254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 300254b07b2SChen Feng pinctrl-names = "default"; 301254b07b2SChen Feng pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 302254b07b2SChen Feng status = "disabled"; 303254b07b2SChen Feng }; 304254b07b2SChen Feng 305a4e36ae0SZhangfei Gao uart5: serial@fdf05000 { 30635ca8168SChen Feng compatible = "arm,pl011", "arm,primecell"; 30735ca8168SChen Feng reg = <0x0 0xfdf05000 0x0 0x1000>; 30835ca8168SChen Feng interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 309a4e36ae0SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 310a4e36ae0SZhangfei Gao <&crg_ctrl HI3660_CLK_GATE_UART5>; 31135ca8168SChen Feng clock-names = "uartclk", "apb_pclk"; 312254b07b2SChen Feng pinctrl-names = "default"; 313254b07b2SChen Feng pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 314254b07b2SChen Feng status = "disabled"; 315254b07b2SChen Feng }; 316254b07b2SChen Feng 317254b07b2SChen Feng uart6: serial@fff32000 { 318254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 319254b07b2SChen Feng reg = <0x0 0xfff32000 0x0 0x1000>; 320254b07b2SChen Feng interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 321254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_UART6>, 322254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 323254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 324254b07b2SChen Feng pinctrl-names = "default"; 325254b07b2SChen Feng pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 32635ca8168SChen Feng status = "disabled"; 32735ca8168SChen Feng }; 328d94eab86SWang Xiaoyin 3290a0698f6SChen Feng rtc0: rtc@fff04000 { 3300a0698f6SChen Feng compatible = "arm,pl031", "arm,primecell"; 3310a0698f6SChen Feng reg = <0x0 0Xfff04000 0x0 0x1000>; 3320a0698f6SChen Feng interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 3330a0698f6SChen Feng clocks = <&crg_ctrl HI3660_PCLK>; 3340a0698f6SChen Feng clock-names = "apb_pclk"; 3350a0698f6SChen Feng }; 3360a0698f6SChen Feng 337d94eab86SWang Xiaoyin gpio0: gpio@e8a0b000 { 338d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 339d94eab86SWang Xiaoyin reg = <0 0xe8a0b000 0 0x1000>; 340d94eab86SWang Xiaoyin interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 341d94eab86SWang Xiaoyin gpio-controller; 342d94eab86SWang Xiaoyin #gpio-cells = <2>; 343d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 0 7>; 344d94eab86SWang Xiaoyin interrupt-controller; 345d94eab86SWang Xiaoyin #interrupt-cells = <2>; 346d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 347d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 348d94eab86SWang Xiaoyin }; 349d94eab86SWang Xiaoyin 350d94eab86SWang Xiaoyin gpio1: gpio@e8a0c000 { 351d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 352d94eab86SWang Xiaoyin reg = <0 0xe8a0c000 0 0x1000>; 353d94eab86SWang Xiaoyin interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 354d94eab86SWang Xiaoyin gpio-controller; 355d94eab86SWang Xiaoyin #gpio-cells = <2>; 356d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 7 7>; 357d94eab86SWang Xiaoyin interrupt-controller; 358d94eab86SWang Xiaoyin #interrupt-cells = <2>; 359d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 360d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 361d94eab86SWang Xiaoyin }; 362d94eab86SWang Xiaoyin 363d94eab86SWang Xiaoyin gpio2: gpio@e8a0d000 { 364d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 365d94eab86SWang Xiaoyin reg = <0 0xe8a0d000 0 0x1000>; 366d94eab86SWang Xiaoyin interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 367d94eab86SWang Xiaoyin gpio-controller; 368d94eab86SWang Xiaoyin #gpio-cells = <2>; 369d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 14 8>; 370d94eab86SWang Xiaoyin interrupt-controller; 371d94eab86SWang Xiaoyin #interrupt-cells = <2>; 372d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 373d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 374d94eab86SWang Xiaoyin }; 375d94eab86SWang Xiaoyin 376d94eab86SWang Xiaoyin gpio3: gpio@e8a0e000 { 377d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 378d94eab86SWang Xiaoyin reg = <0 0xe8a0e000 0 0x1000>; 379d94eab86SWang Xiaoyin interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 380d94eab86SWang Xiaoyin gpio-controller; 381d94eab86SWang Xiaoyin #gpio-cells = <2>; 382d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 22 8>; 383d94eab86SWang Xiaoyin interrupt-controller; 384d94eab86SWang Xiaoyin #interrupt-cells = <2>; 385d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 386d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 387d94eab86SWang Xiaoyin }; 388d94eab86SWang Xiaoyin 389d94eab86SWang Xiaoyin gpio4: gpio@e8a0f000 { 390d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 391d94eab86SWang Xiaoyin reg = <0 0xe8a0f000 0 0x1000>; 392d94eab86SWang Xiaoyin interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 393d94eab86SWang Xiaoyin gpio-controller; 394d94eab86SWang Xiaoyin #gpio-cells = <2>; 395d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 30 8>; 396d94eab86SWang Xiaoyin interrupt-controller; 397d94eab86SWang Xiaoyin #interrupt-cells = <2>; 398d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 399d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 400d94eab86SWang Xiaoyin }; 401d94eab86SWang Xiaoyin 402d94eab86SWang Xiaoyin gpio5: gpio@e8a10000 { 403d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 404d94eab86SWang Xiaoyin reg = <0 0xe8a10000 0 0x1000>; 405d94eab86SWang Xiaoyin interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 406d94eab86SWang Xiaoyin gpio-controller; 407d94eab86SWang Xiaoyin #gpio-cells = <2>; 408d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 38 8>; 409d94eab86SWang Xiaoyin interrupt-controller; 410d94eab86SWang Xiaoyin #interrupt-cells = <2>; 411d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 412d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 413d94eab86SWang Xiaoyin }; 414d94eab86SWang Xiaoyin 415d94eab86SWang Xiaoyin gpio6: gpio@e8a11000 { 416d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 417d94eab86SWang Xiaoyin reg = <0 0xe8a11000 0 0x1000>; 418d94eab86SWang Xiaoyin interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 419d94eab86SWang Xiaoyin gpio-controller; 420d94eab86SWang Xiaoyin #gpio-cells = <2>; 421d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 46 8>; 422d94eab86SWang Xiaoyin interrupt-controller; 423d94eab86SWang Xiaoyin #interrupt-cells = <2>; 424d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 425d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 426d94eab86SWang Xiaoyin }; 427d94eab86SWang Xiaoyin 428d94eab86SWang Xiaoyin gpio7: gpio@e8a12000 { 429d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 430d94eab86SWang Xiaoyin reg = <0 0xe8a12000 0 0x1000>; 431d94eab86SWang Xiaoyin interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 432d94eab86SWang Xiaoyin gpio-controller; 433d94eab86SWang Xiaoyin #gpio-cells = <2>; 434d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 54 8>; 435d94eab86SWang Xiaoyin interrupt-controller; 436d94eab86SWang Xiaoyin #interrupt-cells = <2>; 437d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 438d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 439d94eab86SWang Xiaoyin }; 440d94eab86SWang Xiaoyin 441d94eab86SWang Xiaoyin gpio8: gpio@e8a13000 { 442d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 443d94eab86SWang Xiaoyin reg = <0 0xe8a13000 0 0x1000>; 444d94eab86SWang Xiaoyin interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 445d94eab86SWang Xiaoyin gpio-controller; 446d94eab86SWang Xiaoyin #gpio-cells = <2>; 447d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 62 8>; 448d94eab86SWang Xiaoyin interrupt-controller; 449d94eab86SWang Xiaoyin #interrupt-cells = <2>; 450d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 451d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 452d94eab86SWang Xiaoyin }; 453d94eab86SWang Xiaoyin 454d94eab86SWang Xiaoyin gpio9: gpio@e8a14000 { 455d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 456d94eab86SWang Xiaoyin reg = <0 0xe8a14000 0 0x1000>; 457d94eab86SWang Xiaoyin interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 458d94eab86SWang Xiaoyin gpio-controller; 459d94eab86SWang Xiaoyin #gpio-cells = <2>; 460d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 70 8>; 461d94eab86SWang Xiaoyin interrupt-controller; 462d94eab86SWang Xiaoyin #interrupt-cells = <2>; 463d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 464d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 465d94eab86SWang Xiaoyin }; 466d94eab86SWang Xiaoyin 467d94eab86SWang Xiaoyin gpio10: gpio@e8a15000 { 468d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 469d94eab86SWang Xiaoyin reg = <0 0xe8a15000 0 0x1000>; 470d94eab86SWang Xiaoyin interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 471d94eab86SWang Xiaoyin gpio-controller; 472d94eab86SWang Xiaoyin #gpio-cells = <2>; 473d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 78 8>; 474d94eab86SWang Xiaoyin interrupt-controller; 475d94eab86SWang Xiaoyin #interrupt-cells = <2>; 476d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 477d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 478d94eab86SWang Xiaoyin }; 479d94eab86SWang Xiaoyin 480d94eab86SWang Xiaoyin gpio11: gpio@e8a16000 { 481d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 482d94eab86SWang Xiaoyin reg = <0 0xe8a16000 0 0x1000>; 483d94eab86SWang Xiaoyin interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 484d94eab86SWang Xiaoyin gpio-controller; 485d94eab86SWang Xiaoyin #gpio-cells = <2>; 486d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 86 8>; 487d94eab86SWang Xiaoyin interrupt-controller; 488d94eab86SWang Xiaoyin #interrupt-cells = <2>; 489d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 490d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 491d94eab86SWang Xiaoyin }; 492d94eab86SWang Xiaoyin 493d94eab86SWang Xiaoyin gpio12: gpio@e8a17000 { 494d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 495d94eab86SWang Xiaoyin reg = <0 0xe8a17000 0 0x1000>; 496d94eab86SWang Xiaoyin interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 497d94eab86SWang Xiaoyin gpio-controller; 498d94eab86SWang Xiaoyin #gpio-cells = <2>; 499d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 500d94eab86SWang Xiaoyin interrupt-controller; 501d94eab86SWang Xiaoyin #interrupt-cells = <2>; 502d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 503d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 504d94eab86SWang Xiaoyin }; 505d94eab86SWang Xiaoyin 506d94eab86SWang Xiaoyin gpio13: gpio@e8a18000 { 507d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 508d94eab86SWang Xiaoyin reg = <0 0xe8a18000 0 0x1000>; 509d94eab86SWang Xiaoyin interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 510d94eab86SWang Xiaoyin gpio-controller; 511d94eab86SWang Xiaoyin #gpio-cells = <2>; 512d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 102 8>; 513d94eab86SWang Xiaoyin interrupt-controller; 514d94eab86SWang Xiaoyin #interrupt-cells = <2>; 515d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 516d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 517d94eab86SWang Xiaoyin }; 518d94eab86SWang Xiaoyin 519d94eab86SWang Xiaoyin gpio14: gpio@e8a19000 { 520d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 521d94eab86SWang Xiaoyin reg = <0 0xe8a19000 0 0x1000>; 522d94eab86SWang Xiaoyin interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 523d94eab86SWang Xiaoyin gpio-controller; 524d94eab86SWang Xiaoyin #gpio-cells = <2>; 525d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 110 8>; 526d94eab86SWang Xiaoyin interrupt-controller; 527d94eab86SWang Xiaoyin #interrupt-cells = <2>; 528d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 529d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 530d94eab86SWang Xiaoyin }; 531d94eab86SWang Xiaoyin 532d94eab86SWang Xiaoyin gpio15: gpio@e8a1a000 { 533d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 534d94eab86SWang Xiaoyin reg = <0 0xe8a1a000 0 0x1000>; 535d94eab86SWang Xiaoyin interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 536d94eab86SWang Xiaoyin gpio-controller; 537d94eab86SWang Xiaoyin #gpio-cells = <2>; 538d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 118 6>; 539d94eab86SWang Xiaoyin interrupt-controller; 540d94eab86SWang Xiaoyin #interrupt-cells = <2>; 541d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 542d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 543d94eab86SWang Xiaoyin }; 544d94eab86SWang Xiaoyin 545d94eab86SWang Xiaoyin gpio16: gpio@e8a1b000 { 546d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 547d94eab86SWang Xiaoyin reg = <0 0xe8a1b000 0 0x1000>; 548d94eab86SWang Xiaoyin interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 549d94eab86SWang Xiaoyin gpio-controller; 550d94eab86SWang Xiaoyin #gpio-cells = <2>; 551d94eab86SWang Xiaoyin interrupt-controller; 552d94eab86SWang Xiaoyin #interrupt-cells = <2>; 553d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 554d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 555d94eab86SWang Xiaoyin }; 556d94eab86SWang Xiaoyin 557d94eab86SWang Xiaoyin gpio17: gpio@e8a1c000 { 558d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 559d94eab86SWang Xiaoyin reg = <0 0xe8a1c000 0 0x1000>; 560d94eab86SWang Xiaoyin interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 561d94eab86SWang Xiaoyin gpio-controller; 562d94eab86SWang Xiaoyin #gpio-cells = <2>; 563d94eab86SWang Xiaoyin interrupt-controller; 564d94eab86SWang Xiaoyin #interrupt-cells = <2>; 565d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 566d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 567d94eab86SWang Xiaoyin }; 568d94eab86SWang Xiaoyin 569d94eab86SWang Xiaoyin gpio18: gpio@ff3b4000 { 570d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 571d94eab86SWang Xiaoyin reg = <0 0xff3b4000 0 0x1000>; 572d94eab86SWang Xiaoyin interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 573d94eab86SWang Xiaoyin gpio-controller; 574d94eab86SWang Xiaoyin #gpio-cells = <2>; 575d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 0 8>; 576d94eab86SWang Xiaoyin interrupt-controller; 577d94eab86SWang Xiaoyin #interrupt-cells = <2>; 578d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 579d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 580d94eab86SWang Xiaoyin }; 581d94eab86SWang Xiaoyin 582d94eab86SWang Xiaoyin gpio19: gpio@ff3b5000 { 583d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 584d94eab86SWang Xiaoyin reg = <0 0xff3b5000 0 0x1000>; 585d94eab86SWang Xiaoyin interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 586d94eab86SWang Xiaoyin gpio-controller; 587d94eab86SWang Xiaoyin #gpio-cells = <2>; 588d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 8 4>; 589d94eab86SWang Xiaoyin interrupt-controller; 590d94eab86SWang Xiaoyin #interrupt-cells = <2>; 591d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 592d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 593d94eab86SWang Xiaoyin }; 594d94eab86SWang Xiaoyin 595d94eab86SWang Xiaoyin gpio20: gpio@e8a1f000 { 596d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 597d94eab86SWang Xiaoyin reg = <0 0xe8a1f000 0 0x1000>; 598d94eab86SWang Xiaoyin interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 599d94eab86SWang Xiaoyin gpio-controller; 600d94eab86SWang Xiaoyin #gpio-cells = <2>; 601d94eab86SWang Xiaoyin gpio-ranges = <&pmx1 0 0 6>; 602d94eab86SWang Xiaoyin interrupt-controller; 603d94eab86SWang Xiaoyin #interrupt-cells = <2>; 604d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 605d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 606d94eab86SWang Xiaoyin }; 607d94eab86SWang Xiaoyin 608d94eab86SWang Xiaoyin gpio21: gpio@e8a20000 { 609d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 610d94eab86SWang Xiaoyin reg = <0 0xe8a20000 0 0x1000>; 611d94eab86SWang Xiaoyin interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 612d94eab86SWang Xiaoyin gpio-controller; 613d94eab86SWang Xiaoyin #gpio-cells = <2>; 614d94eab86SWang Xiaoyin interrupt-controller; 615d94eab86SWang Xiaoyin #interrupt-cells = <2>; 616d94eab86SWang Xiaoyin gpio-ranges = <&pmx3 0 0 6>; 617d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 618d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 619d94eab86SWang Xiaoyin }; 620d94eab86SWang Xiaoyin 621d94eab86SWang Xiaoyin gpio22: gpio@fff0b000 { 622d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 623d94eab86SWang Xiaoyin reg = <0 0xfff0b000 0 0x1000>; 624d94eab86SWang Xiaoyin interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 625d94eab86SWang Xiaoyin gpio-controller; 626d94eab86SWang Xiaoyin #gpio-cells = <2>; 627d94eab86SWang Xiaoyin /* GPIO176 */ 628d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 2 0 6>; 629d94eab86SWang Xiaoyin interrupt-controller; 630d94eab86SWang Xiaoyin #interrupt-cells = <2>; 631d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 632d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 633d94eab86SWang Xiaoyin }; 634d94eab86SWang Xiaoyin 635d94eab86SWang Xiaoyin gpio23: gpio@fff0c000 { 636d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 637d94eab86SWang Xiaoyin reg = <0 0xfff0c000 0 0x1000>; 638d94eab86SWang Xiaoyin interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 639d94eab86SWang Xiaoyin gpio-controller; 640d94eab86SWang Xiaoyin #gpio-cells = <2>; 641d94eab86SWang Xiaoyin /* GPIO184 */ 642d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 6 7>; 643d94eab86SWang Xiaoyin interrupt-controller; 644d94eab86SWang Xiaoyin #interrupt-cells = <2>; 645d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 646d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 647d94eab86SWang Xiaoyin }; 648d94eab86SWang Xiaoyin 649d94eab86SWang Xiaoyin gpio24: gpio@fff0d000 { 650d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 651d94eab86SWang Xiaoyin reg = <0 0xfff0d000 0 0x1000>; 652d94eab86SWang Xiaoyin interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 653d94eab86SWang Xiaoyin gpio-controller; 654d94eab86SWang Xiaoyin #gpio-cells = <2>; 655d94eab86SWang Xiaoyin /* GPIO192 */ 656d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 13 8>; 657d94eab86SWang Xiaoyin interrupt-controller; 658d94eab86SWang Xiaoyin #interrupt-cells = <2>; 659d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 660d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 661d94eab86SWang Xiaoyin }; 662d94eab86SWang Xiaoyin 663d94eab86SWang Xiaoyin gpio25: gpio@fff0e000 { 664d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 665d94eab86SWang Xiaoyin reg = <0 0xfff0e000 0 0x1000>; 666d94eab86SWang Xiaoyin interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 667d94eab86SWang Xiaoyin gpio-controller; 668d94eab86SWang Xiaoyin #gpio-cells = <2>; 669d94eab86SWang Xiaoyin /* GPIO200 */ 670d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 671d94eab86SWang Xiaoyin interrupt-controller; 672d94eab86SWang Xiaoyin #interrupt-cells = <2>; 673d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 674d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 675d94eab86SWang Xiaoyin }; 676d94eab86SWang Xiaoyin 677d94eab86SWang Xiaoyin gpio26: gpio@fff0f000 { 678d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 679d94eab86SWang Xiaoyin reg = <0 0xfff0f000 0 0x1000>; 680d94eab86SWang Xiaoyin interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 681d94eab86SWang Xiaoyin gpio-controller; 682d94eab86SWang Xiaoyin #gpio-cells = <2>; 683d94eab86SWang Xiaoyin /* GPIO208 */ 684d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 28 8>; 685d94eab86SWang Xiaoyin interrupt-controller; 686d94eab86SWang Xiaoyin #interrupt-cells = <2>; 687d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 688d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 689d94eab86SWang Xiaoyin }; 690d94eab86SWang Xiaoyin 691d94eab86SWang Xiaoyin gpio27: gpio@fff10000 { 692d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 693d94eab86SWang Xiaoyin reg = <0 0xfff10000 0 0x1000>; 694d94eab86SWang Xiaoyin interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 695d94eab86SWang Xiaoyin gpio-controller; 696d94eab86SWang Xiaoyin #gpio-cells = <2>; 697d94eab86SWang Xiaoyin /* GPIO216 */ 698d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 36 6>; 699d94eab86SWang Xiaoyin interrupt-controller; 700d94eab86SWang Xiaoyin #interrupt-cells = <2>; 701d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 702d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 703d94eab86SWang Xiaoyin }; 704d94eab86SWang Xiaoyin 705d94eab86SWang Xiaoyin gpio28: gpio@fff1d000 { 706d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 707d94eab86SWang Xiaoyin reg = <0 0xfff1d000 0 0x1000>; 708d94eab86SWang Xiaoyin interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 709d94eab86SWang Xiaoyin gpio-controller; 710d94eab86SWang Xiaoyin #gpio-cells = <2>; 711d94eab86SWang Xiaoyin interrupt-controller; 712d94eab86SWang Xiaoyin #interrupt-cells = <2>; 713d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 714d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 715d94eab86SWang Xiaoyin }; 71638810497SWang Xiaoyin 71738810497SWang Xiaoyin spi2: spi@ffd68000 { 71838810497SWang Xiaoyin compatible = "arm,pl022", "arm,primecell"; 71938810497SWang Xiaoyin reg = <0x0 0xffd68000 0x0 0x1000>; 72038810497SWang Xiaoyin #address-cells = <1>; 72138810497SWang Xiaoyin #size-cells = <0>; 72238810497SWang Xiaoyin interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 72338810497SWang Xiaoyin clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; 72438810497SWang Xiaoyin clock-names = "apb_pclk"; 72538810497SWang Xiaoyin pinctrl-names = "default"; 72638810497SWang Xiaoyin pinctrl-0 = <&spi2_pmx_func>; 72738810497SWang Xiaoyin num-cs = <1>; 72838810497SWang Xiaoyin cs-gpios = <&gpio27 2 0>; 72938810497SWang Xiaoyin status = "disabled"; 73038810497SWang Xiaoyin }; 73138810497SWang Xiaoyin 73238810497SWang Xiaoyin spi3: spi@ff3b3000 { 73338810497SWang Xiaoyin compatible = "arm,pl022", "arm,primecell"; 73438810497SWang Xiaoyin reg = <0x0 0xff3b3000 0x0 0x1000>; 73538810497SWang Xiaoyin #address-cells = <1>; 73638810497SWang Xiaoyin #size-cells = <0>; 73738810497SWang Xiaoyin interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 73838810497SWang Xiaoyin clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; 73938810497SWang Xiaoyin clock-names = "apb_pclk"; 74038810497SWang Xiaoyin pinctrl-names = "default"; 74138810497SWang Xiaoyin pinctrl-0 = <&spi3_pmx_func>; 74238810497SWang Xiaoyin num-cs = <1>; 74338810497SWang Xiaoyin cs-gpios = <&gpio18 5 0>; 74438810497SWang Xiaoyin status = "disabled"; 74538810497SWang Xiaoyin }; 74635ca8168SChen Feng }; 74735ca8168SChen Feng}; 748