135ca8168SChen Feng/* 235ca8168SChen Feng * dts file for Hisilicon Hi3660 SoC 335ca8168SChen Feng * 435ca8168SChen Feng * Copyright (C) 2016, Hisilicon Ltd. 535ca8168SChen Feng */ 635ca8168SChen Feng 735ca8168SChen Feng#include <dt-bindings/interrupt-controller/arm-gic.h> 835ca8168SChen Feng 935ca8168SChen Feng/ { 1035ca8168SChen Feng compatible = "hisilicon,hi3660"; 1135ca8168SChen Feng interrupt-parent = <&gic>; 1235ca8168SChen Feng #address-cells = <2>; 1335ca8168SChen Feng #size-cells = <2>; 1435ca8168SChen Feng 1535ca8168SChen Feng psci { 1635ca8168SChen Feng compatible = "arm,psci-0.2"; 1735ca8168SChen Feng method = "smc"; 1835ca8168SChen Feng }; 1935ca8168SChen Feng 2035ca8168SChen Feng cpus { 2135ca8168SChen Feng #address-cells = <2>; 2235ca8168SChen Feng #size-cells = <0>; 2335ca8168SChen Feng 2435ca8168SChen Feng cpu-map { 2535ca8168SChen Feng cluster0 { 2635ca8168SChen Feng core0 { 2735ca8168SChen Feng cpu = <&cpu0>; 2835ca8168SChen Feng }; 2935ca8168SChen Feng core1 { 3035ca8168SChen Feng cpu = <&cpu1>; 3135ca8168SChen Feng }; 3235ca8168SChen Feng core2 { 3335ca8168SChen Feng cpu = <&cpu2>; 3435ca8168SChen Feng }; 3535ca8168SChen Feng core3 { 3635ca8168SChen Feng cpu = <&cpu3>; 3735ca8168SChen Feng }; 3835ca8168SChen Feng }; 3935ca8168SChen Feng cluster1 { 4035ca8168SChen Feng core0 { 4135ca8168SChen Feng cpu = <&cpu4>; 4235ca8168SChen Feng }; 4335ca8168SChen Feng core1 { 4435ca8168SChen Feng cpu = <&cpu5>; 4535ca8168SChen Feng }; 4635ca8168SChen Feng core2 { 4735ca8168SChen Feng cpu = <&cpu6>; 4835ca8168SChen Feng }; 4935ca8168SChen Feng core3 { 5035ca8168SChen Feng cpu = <&cpu7>; 5135ca8168SChen Feng }; 5235ca8168SChen Feng }; 5335ca8168SChen Feng }; 5435ca8168SChen Feng 5535ca8168SChen Feng cpu0: cpu@0 { 5635ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 5735ca8168SChen Feng device_type = "cpu"; 5835ca8168SChen Feng reg = <0x0 0x0>; 5935ca8168SChen Feng enable-method = "psci"; 6035ca8168SChen Feng }; 6135ca8168SChen Feng 6235ca8168SChen Feng cpu1: cpu@1 { 6335ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 6435ca8168SChen Feng device_type = "cpu"; 6535ca8168SChen Feng reg = <0x0 0x1>; 6635ca8168SChen Feng enable-method = "psci"; 6735ca8168SChen Feng }; 6835ca8168SChen Feng 6935ca8168SChen Feng cpu2: cpu@2 { 7035ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 7135ca8168SChen Feng device_type = "cpu"; 7235ca8168SChen Feng reg = <0x0 0x2>; 7335ca8168SChen Feng enable-method = "psci"; 7435ca8168SChen Feng }; 7535ca8168SChen Feng 7635ca8168SChen Feng cpu3: cpu@3 { 7735ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 7835ca8168SChen Feng device_type = "cpu"; 7935ca8168SChen Feng reg = <0x0 0x3>; 8035ca8168SChen Feng enable-method = "psci"; 8135ca8168SChen Feng }; 8235ca8168SChen Feng 8335ca8168SChen Feng cpu4: cpu@100 { 8435ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 8535ca8168SChen Feng device_type = "cpu"; 8635ca8168SChen Feng reg = <0x0 0x100>; 8735ca8168SChen Feng enable-method = "psci"; 8835ca8168SChen Feng }; 8935ca8168SChen Feng 9035ca8168SChen Feng cpu5: cpu@101 { 9135ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 9235ca8168SChen Feng device_type = "cpu"; 9335ca8168SChen Feng reg = <0x0 0x101>; 9435ca8168SChen Feng enable-method = "psci"; 9535ca8168SChen Feng }; 9635ca8168SChen Feng 9735ca8168SChen Feng cpu6: cpu@102 { 9835ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 9935ca8168SChen Feng device_type = "cpu"; 10035ca8168SChen Feng reg = <0x0 0x102>; 10135ca8168SChen Feng enable-method = "psci"; 10235ca8168SChen Feng }; 10335ca8168SChen Feng 10435ca8168SChen Feng cpu7: cpu@103 { 10535ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 10635ca8168SChen Feng device_type = "cpu"; 10735ca8168SChen Feng reg = <0x0 0x103>; 10835ca8168SChen Feng enable-method = "psci"; 10935ca8168SChen Feng }; 11035ca8168SChen Feng }; 11135ca8168SChen Feng 11235ca8168SChen Feng gic: interrupt-controller@e82b0000 { 11335ca8168SChen Feng compatible = "arm,gic-400"; 11435ca8168SChen Feng reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 11535ca8168SChen Feng <0x0 0xe82b2000 0 0x2000>, /* GICC */ 11635ca8168SChen Feng <0x0 0xe82b4000 0 0x2000>, /* GICH */ 11735ca8168SChen Feng <0x0 0xe82b6000 0 0x2000>; /* GICV */ 11835ca8168SChen Feng #address-cells = <0>; 11935ca8168SChen Feng #interrupt-cells = <3>; 12035ca8168SChen Feng interrupt-controller; 12135ca8168SChen Feng interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 12235ca8168SChen Feng IRQ_TYPE_LEVEL_HIGH)>; 12335ca8168SChen Feng }; 12435ca8168SChen Feng 12535ca8168SChen Feng timer { 12635ca8168SChen Feng compatible = "arm,armv8-timer"; 12735ca8168SChen Feng interrupt-parent = <&gic>; 12835ca8168SChen Feng interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 12935ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 13035ca8168SChen Feng <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 13135ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 13235ca8168SChen Feng <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 13335ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 13435ca8168SChen Feng <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 13535ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>; 13635ca8168SChen Feng }; 13735ca8168SChen Feng 13835ca8168SChen Feng soc { 13935ca8168SChen Feng compatible = "simple-bus"; 14035ca8168SChen Feng #address-cells = <2>; 14135ca8168SChen Feng #size-cells = <2>; 14235ca8168SChen Feng ranges; 14335ca8168SChen Feng 14435ca8168SChen Feng fixed_uart5: fixed_19_2M { 14535ca8168SChen Feng compatible = "fixed-clock"; 14635ca8168SChen Feng #clock-cells = <0>; 14735ca8168SChen Feng clock-frequency = <19200000>; 14835ca8168SChen Feng clock-output-names = "fixed:uart5"; 14935ca8168SChen Feng }; 15035ca8168SChen Feng 15135ca8168SChen Feng uart5: uart@fdf05000 { 15235ca8168SChen Feng compatible = "arm,pl011", "arm,primecell"; 15335ca8168SChen Feng reg = <0x0 0xfdf05000 0x0 0x1000>; 15435ca8168SChen Feng interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 15535ca8168SChen Feng clocks = <&fixed_uart5 &fixed_uart5>; 15635ca8168SChen Feng clock-names = "uartclk", "apb_pclk"; 15735ca8168SChen Feng status = "disabled"; 15835ca8168SChen Feng }; 15935ca8168SChen Feng }; 16035ca8168SChen Feng}; 161