135ca8168SChen Feng/* 235ca8168SChen Feng * dts file for Hisilicon Hi3660 SoC 335ca8168SChen Feng * 435ca8168SChen Feng * Copyright (C) 2016, Hisilicon Ltd. 535ca8168SChen Feng */ 635ca8168SChen Feng 735ca8168SChen Feng#include <dt-bindings/interrupt-controller/arm-gic.h> 8a4e36ae0SZhangfei Gao#include <dt-bindings/clock/hi3660-clock.h> 935ca8168SChen Feng 1035ca8168SChen Feng/ { 1135ca8168SChen Feng compatible = "hisilicon,hi3660"; 1235ca8168SChen Feng interrupt-parent = <&gic>; 1335ca8168SChen Feng #address-cells = <2>; 1435ca8168SChen Feng #size-cells = <2>; 1535ca8168SChen Feng 1635ca8168SChen Feng psci { 1735ca8168SChen Feng compatible = "arm,psci-0.2"; 1835ca8168SChen Feng method = "smc"; 1935ca8168SChen Feng }; 2035ca8168SChen Feng 2135ca8168SChen Feng cpus { 2235ca8168SChen Feng #address-cells = <2>; 2335ca8168SChen Feng #size-cells = <0>; 2435ca8168SChen Feng 2535ca8168SChen Feng cpu-map { 2635ca8168SChen Feng cluster0 { 2735ca8168SChen Feng core0 { 2835ca8168SChen Feng cpu = <&cpu0>; 2935ca8168SChen Feng }; 3035ca8168SChen Feng core1 { 3135ca8168SChen Feng cpu = <&cpu1>; 3235ca8168SChen Feng }; 3335ca8168SChen Feng core2 { 3435ca8168SChen Feng cpu = <&cpu2>; 3535ca8168SChen Feng }; 3635ca8168SChen Feng core3 { 3735ca8168SChen Feng cpu = <&cpu3>; 3835ca8168SChen Feng }; 3935ca8168SChen Feng }; 4035ca8168SChen Feng cluster1 { 4135ca8168SChen Feng core0 { 4235ca8168SChen Feng cpu = <&cpu4>; 4335ca8168SChen Feng }; 4435ca8168SChen Feng core1 { 4535ca8168SChen Feng cpu = <&cpu5>; 4635ca8168SChen Feng }; 4735ca8168SChen Feng core2 { 4835ca8168SChen Feng cpu = <&cpu6>; 4935ca8168SChen Feng }; 5035ca8168SChen Feng core3 { 5135ca8168SChen Feng cpu = <&cpu7>; 5235ca8168SChen Feng }; 5335ca8168SChen Feng }; 5435ca8168SChen Feng }; 5535ca8168SChen Feng 5635ca8168SChen Feng cpu0: cpu@0 { 5735ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 5835ca8168SChen Feng device_type = "cpu"; 5935ca8168SChen Feng reg = <0x0 0x0>; 6035ca8168SChen Feng enable-method = "psci"; 6130fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 6235ca8168SChen Feng }; 6335ca8168SChen Feng 6435ca8168SChen Feng cpu1: cpu@1 { 6535ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 6635ca8168SChen Feng device_type = "cpu"; 6735ca8168SChen Feng reg = <0x0 0x1>; 6835ca8168SChen Feng enable-method = "psci"; 6930fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 7035ca8168SChen Feng }; 7135ca8168SChen Feng 7235ca8168SChen Feng cpu2: cpu@2 { 7335ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 7435ca8168SChen Feng device_type = "cpu"; 7535ca8168SChen Feng reg = <0x0 0x2>; 7635ca8168SChen Feng enable-method = "psci"; 7730fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 7835ca8168SChen Feng }; 7935ca8168SChen Feng 8035ca8168SChen Feng cpu3: cpu@3 { 8135ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 8235ca8168SChen Feng device_type = "cpu"; 8335ca8168SChen Feng reg = <0x0 0x3>; 8435ca8168SChen Feng enable-method = "psci"; 8530fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 8635ca8168SChen Feng }; 8735ca8168SChen Feng 8835ca8168SChen Feng cpu4: cpu@100 { 8935ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 9035ca8168SChen Feng device_type = "cpu"; 9135ca8168SChen Feng reg = <0x0 0x100>; 9235ca8168SChen Feng enable-method = "psci"; 9330fec826SLeo Yan cpu-idle-states = < 9430fec826SLeo Yan &CPU_NAP 9530fec826SLeo Yan &CPU_SLEEP 9630fec826SLeo Yan &CLUSTER_SLEEP_1 9730fec826SLeo Yan >; 9835ca8168SChen Feng }; 9935ca8168SChen Feng 10035ca8168SChen Feng cpu5: cpu@101 { 10135ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 10235ca8168SChen Feng device_type = "cpu"; 10335ca8168SChen Feng reg = <0x0 0x101>; 10435ca8168SChen Feng enable-method = "psci"; 10530fec826SLeo Yan cpu-idle-states = < 10630fec826SLeo Yan &CPU_NAP 10730fec826SLeo Yan &CPU_SLEEP 10830fec826SLeo Yan &CLUSTER_SLEEP_1 10930fec826SLeo Yan >; 11035ca8168SChen Feng }; 11135ca8168SChen Feng 11235ca8168SChen Feng cpu6: cpu@102 { 11335ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 11435ca8168SChen Feng device_type = "cpu"; 11535ca8168SChen Feng reg = <0x0 0x102>; 11635ca8168SChen Feng enable-method = "psci"; 11730fec826SLeo Yan cpu-idle-states = < 11830fec826SLeo Yan &CPU_NAP 11930fec826SLeo Yan &CPU_SLEEP 12030fec826SLeo Yan &CLUSTER_SLEEP_1 12130fec826SLeo Yan >; 12235ca8168SChen Feng }; 12335ca8168SChen Feng 12435ca8168SChen Feng cpu7: cpu@103 { 12535ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 12635ca8168SChen Feng device_type = "cpu"; 12735ca8168SChen Feng reg = <0x0 0x103>; 12835ca8168SChen Feng enable-method = "psci"; 12930fec826SLeo Yan cpu-idle-states = < 13030fec826SLeo Yan &CPU_NAP 13130fec826SLeo Yan &CPU_SLEEP 13230fec826SLeo Yan &CLUSTER_SLEEP_1 13330fec826SLeo Yan >; 13430fec826SLeo Yan }; 13530fec826SLeo Yan 13630fec826SLeo Yan idle-states { 13730fec826SLeo Yan entry-method = "psci"; 13830fec826SLeo Yan 13930fec826SLeo Yan CPU_NAP: cpu-nap { 14030fec826SLeo Yan compatible = "arm,idle-state"; 14130fec826SLeo Yan arm,psci-suspend-param = <0x0000001>; 14230fec826SLeo Yan entry-latency-us = <7>; 14330fec826SLeo Yan exit-latency-us = <2>; 14430fec826SLeo Yan min-residency-us = <15>; 14530fec826SLeo Yan }; 14630fec826SLeo Yan 14730fec826SLeo Yan CPU_SLEEP: cpu-sleep { 14830fec826SLeo Yan compatible = "arm,idle-state"; 14930fec826SLeo Yan local-timer-stop; 15030fec826SLeo Yan arm,psci-suspend-param = <0x0010000>; 15130fec826SLeo Yan entry-latency-us = <40>; 15230fec826SLeo Yan exit-latency-us = <70>; 15330fec826SLeo Yan min-residency-us = <3000>; 15430fec826SLeo Yan }; 15530fec826SLeo Yan 15630fec826SLeo Yan CLUSTER_SLEEP_0: cluster-sleep-0 { 15730fec826SLeo Yan compatible = "arm,idle-state"; 15830fec826SLeo Yan local-timer-stop; 15930fec826SLeo Yan arm,psci-suspend-param = <0x1010000>; 16030fec826SLeo Yan entry-latency-us = <500>; 16130fec826SLeo Yan exit-latency-us = <5000>; 16230fec826SLeo Yan min-residency-us = <20000>; 16330fec826SLeo Yan }; 16430fec826SLeo Yan 16530fec826SLeo Yan CLUSTER_SLEEP_1: cluster-sleep-1 { 16630fec826SLeo Yan compatible = "arm,idle-state"; 16730fec826SLeo Yan local-timer-stop; 16830fec826SLeo Yan arm,psci-suspend-param = <0x1010000>; 16930fec826SLeo Yan entry-latency-us = <1000>; 17030fec826SLeo Yan exit-latency-us = <5000>; 17130fec826SLeo Yan min-residency-us = <20000>; 17230fec826SLeo Yan }; 17335ca8168SChen Feng }; 17435ca8168SChen Feng }; 17535ca8168SChen Feng 17635ca8168SChen Feng gic: interrupt-controller@e82b0000 { 17735ca8168SChen Feng compatible = "arm,gic-400"; 17835ca8168SChen Feng reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 17935ca8168SChen Feng <0x0 0xe82b2000 0 0x2000>, /* GICC */ 18035ca8168SChen Feng <0x0 0xe82b4000 0 0x2000>, /* GICH */ 18135ca8168SChen Feng <0x0 0xe82b6000 0 0x2000>; /* GICV */ 18235ca8168SChen Feng #address-cells = <0>; 18335ca8168SChen Feng #interrupt-cells = <3>; 18435ca8168SChen Feng interrupt-controller; 18535ca8168SChen Feng interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 18635ca8168SChen Feng IRQ_TYPE_LEVEL_HIGH)>; 18735ca8168SChen Feng }; 18835ca8168SChen Feng 18935ca8168SChen Feng timer { 19035ca8168SChen Feng compatible = "arm,armv8-timer"; 19135ca8168SChen Feng interrupt-parent = <&gic>; 19235ca8168SChen Feng interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 19335ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 19435ca8168SChen Feng <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 19535ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 19635ca8168SChen Feng <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 19735ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 19835ca8168SChen Feng <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 19935ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>; 20035ca8168SChen Feng }; 20135ca8168SChen Feng 20235ca8168SChen Feng soc { 20335ca8168SChen Feng compatible = "simple-bus"; 20435ca8168SChen Feng #address-cells = <2>; 20535ca8168SChen Feng #size-cells = <2>; 20635ca8168SChen Feng ranges; 20735ca8168SChen Feng 208a4e36ae0SZhangfei Gao crg_ctrl: crg_ctrl@fff35000 { 209a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-crgctrl", "syscon"; 210a4e36ae0SZhangfei Gao reg = <0x0 0xfff35000 0x0 0x1000>; 211a4e36ae0SZhangfei Gao #clock-cells = <1>; 21235ca8168SChen Feng }; 21335ca8168SChen Feng 214a4e36ae0SZhangfei Gao crg_rst: crg_rst_controller { 215a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 216a4e36ae0SZhangfei Gao #reset-cells = <2>; 217a4e36ae0SZhangfei Gao hisi,rst-syscon = <&crg_ctrl>; 218a4e36ae0SZhangfei Gao }; 219a4e36ae0SZhangfei Gao 220a4e36ae0SZhangfei Gao 221a4e36ae0SZhangfei Gao pctrl: pctrl@e8a09000 { 222a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pctrl", "syscon"; 223a4e36ae0SZhangfei Gao reg = <0x0 0xe8a09000 0x0 0x2000>; 224a4e36ae0SZhangfei Gao #clock-cells = <1>; 225a4e36ae0SZhangfei Gao }; 226a4e36ae0SZhangfei Gao 227a4e36ae0SZhangfei Gao pmuctrl: crg_ctrl@fff34000 { 228a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 229a4e36ae0SZhangfei Gao reg = <0x0 0xfff34000 0x0 0x1000>; 230a4e36ae0SZhangfei Gao #clock-cells = <1>; 231a4e36ae0SZhangfei Gao }; 232a4e36ae0SZhangfei Gao 233a4e36ae0SZhangfei Gao sctrl: sctrl@fff0a000 { 234a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-sctrl", "syscon"; 235a4e36ae0SZhangfei Gao reg = <0x0 0xfff0a000 0x0 0x1000>; 236a4e36ae0SZhangfei Gao #clock-cells = <1>; 237a4e36ae0SZhangfei Gao }; 238a4e36ae0SZhangfei Gao 239a4e36ae0SZhangfei Gao iomcu: iomcu@ffd7e000 { 240a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-iomcu", "syscon"; 241a4e36ae0SZhangfei Gao reg = <0x0 0xffd7e000 0x0 0x1000>; 242a4e36ae0SZhangfei Gao #clock-cells = <1>; 243a4e36ae0SZhangfei Gao 244a4e36ae0SZhangfei Gao }; 245a4e36ae0SZhangfei Gao 246a4e36ae0SZhangfei Gao iomcu_rst: reset { 247a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 248a4e36ae0SZhangfei Gao hisi,rst-syscon = <&iomcu>; 249a4e36ae0SZhangfei Gao #reset-cells = <2>; 250a4e36ae0SZhangfei Gao }; 251a4e36ae0SZhangfei Gao 25275196330SLeo Yan dual_timer0: timer@fff14000 { 25375196330SLeo Yan compatible = "arm,sp804", "arm,primecell"; 25475196330SLeo Yan reg = <0x0 0xfff14000 0x0 0x1000>; 25575196330SLeo Yan interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 25675196330SLeo Yan <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 25775196330SLeo Yan clocks = <&crg_ctrl HI3660_OSC32K>, 25875196330SLeo Yan <&crg_ctrl HI3660_OSC32K>, 25975196330SLeo Yan <&crg_ctrl HI3660_OSC32K>; 26075196330SLeo Yan clock-names = "timer1", "timer2", "apb_pclk"; 26175196330SLeo Yan }; 26275196330SLeo Yan 2635f8a3b77SZhangfei Gao i2c0: i2c@ffd71000 { 2645f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 2655f8a3b77SZhangfei Gao reg = <0x0 0xffd71000 0x0 0x1000>; 2665f8a3b77SZhangfei Gao interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2675f8a3b77SZhangfei Gao #address-cells = <1>; 2685f8a3b77SZhangfei Gao #size-cells = <0>; 2695f8a3b77SZhangfei Gao clock-frequency = <400000>; 2705f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 2715f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 3>; 2725f8a3b77SZhangfei Gao pinctrl-names = "default"; 2735f8a3b77SZhangfei Gao pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 2745f8a3b77SZhangfei Gao status = "disabled"; 2755f8a3b77SZhangfei Gao }; 2765f8a3b77SZhangfei Gao 2775f8a3b77SZhangfei Gao i2c1: i2c@ffd72000 { 2785f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 2795f8a3b77SZhangfei Gao reg = <0x0 0xffd72000 0x0 0x1000>; 2805f8a3b77SZhangfei Gao interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2815f8a3b77SZhangfei Gao #address-cells = <1>; 2825f8a3b77SZhangfei Gao #size-cells = <0>; 2835f8a3b77SZhangfei Gao clock-frequency = <400000>; 2845f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 2855f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 4>; 2865f8a3b77SZhangfei Gao pinctrl-names = "default"; 2875f8a3b77SZhangfei Gao pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 2885f8a3b77SZhangfei Gao status = "disabled"; 2895f8a3b77SZhangfei Gao }; 2905f8a3b77SZhangfei Gao 2915f8a3b77SZhangfei Gao i2c3: i2c@fdf0c000 { 2925f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 2935f8a3b77SZhangfei Gao reg = <0x0 0xfdf0c000 0x0 0x1000>; 2945f8a3b77SZhangfei Gao interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2955f8a3b77SZhangfei Gao #address-cells = <1>; 2965f8a3b77SZhangfei Gao #size-cells = <0>; 2975f8a3b77SZhangfei Gao clock-frequency = <400000>; 2985f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 2995f8a3b77SZhangfei Gao resets = <&crg_rst 0x78 7>; 3005f8a3b77SZhangfei Gao pinctrl-names = "default"; 3015f8a3b77SZhangfei Gao pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 3025f8a3b77SZhangfei Gao status = "disabled"; 3035f8a3b77SZhangfei Gao }; 3045f8a3b77SZhangfei Gao 3055f8a3b77SZhangfei Gao i2c7: i2c@fdf0b000 { 3065f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 3075f8a3b77SZhangfei Gao reg = <0x0 0xfdf0b000 0x0 0x1000>; 3085f8a3b77SZhangfei Gao interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 3095f8a3b77SZhangfei Gao #address-cells = <1>; 3105f8a3b77SZhangfei Gao #size-cells = <0>; 3115f8a3b77SZhangfei Gao clock-frequency = <400000>; 3125f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 3135f8a3b77SZhangfei Gao resets = <&crg_rst 0x60 14>; 3145f8a3b77SZhangfei Gao pinctrl-names = "default"; 3155f8a3b77SZhangfei Gao pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 3165f8a3b77SZhangfei Gao status = "disabled"; 3175f8a3b77SZhangfei Gao }; 3185f8a3b77SZhangfei Gao 319254b07b2SChen Feng uart0: serial@fdf02000 { 320254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 321254b07b2SChen Feng reg = <0x0 0xfdf02000 0x0 0x1000>; 322254b07b2SChen Feng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 323254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 324254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 325254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 326254b07b2SChen Feng pinctrl-names = "default"; 327254b07b2SChen Feng pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 328254b07b2SChen Feng status = "disabled"; 329254b07b2SChen Feng }; 330254b07b2SChen Feng 331254b07b2SChen Feng uart1: serial@fdf00000 { 332254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 333254b07b2SChen Feng reg = <0x0 0xfdf00000 0x0 0x1000>; 334254b07b2SChen Feng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 335254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 336254b07b2SChen Feng <&crg_ctrl HI3660_CLK_GATE_UART1>; 337254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 338254b07b2SChen Feng pinctrl-names = "default"; 339254b07b2SChen Feng pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 340254b07b2SChen Feng status = "disabled"; 341254b07b2SChen Feng }; 342254b07b2SChen Feng 343254b07b2SChen Feng uart2: serial@fdf03000 { 344254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 345254b07b2SChen Feng reg = <0x0 0xfdf03000 0x0 0x1000>; 346254b07b2SChen Feng interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 347254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 348254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 349254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 350254b07b2SChen Feng pinctrl-names = "default"; 351254b07b2SChen Feng pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 352254b07b2SChen Feng status = "disabled"; 353254b07b2SChen Feng }; 354254b07b2SChen Feng 355254b07b2SChen Feng uart3: serial@ffd74000 { 356254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 357254b07b2SChen Feng reg = <0x0 0xffd74000 0x0 0x1000>; 358254b07b2SChen Feng interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 359254b07b2SChen Feng clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 360254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 361254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 362254b07b2SChen Feng pinctrl-names = "default"; 363254b07b2SChen Feng pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 364254b07b2SChen Feng status = "disabled"; 365254b07b2SChen Feng }; 366254b07b2SChen Feng 367254b07b2SChen Feng uart4: serial@fdf01000 { 368254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 369254b07b2SChen Feng reg = <0x0 0xfdf01000 0x0 0x1000>; 370254b07b2SChen Feng interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 371254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 372254b07b2SChen Feng <&crg_ctrl HI3660_CLK_GATE_UART4>; 373254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 374254b07b2SChen Feng pinctrl-names = "default"; 375254b07b2SChen Feng pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 376254b07b2SChen Feng status = "disabled"; 377254b07b2SChen Feng }; 378254b07b2SChen Feng 379a4e36ae0SZhangfei Gao uart5: serial@fdf05000 { 38035ca8168SChen Feng compatible = "arm,pl011", "arm,primecell"; 38135ca8168SChen Feng reg = <0x0 0xfdf05000 0x0 0x1000>; 38235ca8168SChen Feng interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 383a4e36ae0SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 384a4e36ae0SZhangfei Gao <&crg_ctrl HI3660_CLK_GATE_UART5>; 38535ca8168SChen Feng clock-names = "uartclk", "apb_pclk"; 386254b07b2SChen Feng pinctrl-names = "default"; 387254b07b2SChen Feng pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 388254b07b2SChen Feng status = "disabled"; 389254b07b2SChen Feng }; 390254b07b2SChen Feng 391254b07b2SChen Feng uart6: serial@fff32000 { 392254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 393254b07b2SChen Feng reg = <0x0 0xfff32000 0x0 0x1000>; 394254b07b2SChen Feng interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 395254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_UART6>, 396254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 397254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 398254b07b2SChen Feng pinctrl-names = "default"; 399254b07b2SChen Feng pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 40035ca8168SChen Feng status = "disabled"; 40135ca8168SChen Feng }; 402d94eab86SWang Xiaoyin 4030a0698f6SChen Feng rtc0: rtc@fff04000 { 4040a0698f6SChen Feng compatible = "arm,pl031", "arm,primecell"; 4050a0698f6SChen Feng reg = <0x0 0Xfff04000 0x0 0x1000>; 4060a0698f6SChen Feng interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 4070a0698f6SChen Feng clocks = <&crg_ctrl HI3660_PCLK>; 4080a0698f6SChen Feng clock-names = "apb_pclk"; 4090a0698f6SChen Feng }; 4100a0698f6SChen Feng 411d94eab86SWang Xiaoyin gpio0: gpio@e8a0b000 { 412d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 413d94eab86SWang Xiaoyin reg = <0 0xe8a0b000 0 0x1000>; 414d94eab86SWang Xiaoyin interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 415d94eab86SWang Xiaoyin gpio-controller; 416d94eab86SWang Xiaoyin #gpio-cells = <2>; 417d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 0 7>; 418d94eab86SWang Xiaoyin interrupt-controller; 419d94eab86SWang Xiaoyin #interrupt-cells = <2>; 420d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 421d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 422d94eab86SWang Xiaoyin }; 423d94eab86SWang Xiaoyin 424d94eab86SWang Xiaoyin gpio1: gpio@e8a0c000 { 425d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 426d94eab86SWang Xiaoyin reg = <0 0xe8a0c000 0 0x1000>; 427d94eab86SWang Xiaoyin interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 428d94eab86SWang Xiaoyin gpio-controller; 429d94eab86SWang Xiaoyin #gpio-cells = <2>; 430d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 7 7>; 431d94eab86SWang Xiaoyin interrupt-controller; 432d94eab86SWang Xiaoyin #interrupt-cells = <2>; 433d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 434d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 435d94eab86SWang Xiaoyin }; 436d94eab86SWang Xiaoyin 437d94eab86SWang Xiaoyin gpio2: gpio@e8a0d000 { 438d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 439d94eab86SWang Xiaoyin reg = <0 0xe8a0d000 0 0x1000>; 440d94eab86SWang Xiaoyin interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 441d94eab86SWang Xiaoyin gpio-controller; 442d94eab86SWang Xiaoyin #gpio-cells = <2>; 443d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 14 8>; 444d94eab86SWang Xiaoyin interrupt-controller; 445d94eab86SWang Xiaoyin #interrupt-cells = <2>; 446d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 447d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 448d94eab86SWang Xiaoyin }; 449d94eab86SWang Xiaoyin 450d94eab86SWang Xiaoyin gpio3: gpio@e8a0e000 { 451d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 452d94eab86SWang Xiaoyin reg = <0 0xe8a0e000 0 0x1000>; 453d94eab86SWang Xiaoyin interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 454d94eab86SWang Xiaoyin gpio-controller; 455d94eab86SWang Xiaoyin #gpio-cells = <2>; 456d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 22 8>; 457d94eab86SWang Xiaoyin interrupt-controller; 458d94eab86SWang Xiaoyin #interrupt-cells = <2>; 459d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 460d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 461d94eab86SWang Xiaoyin }; 462d94eab86SWang Xiaoyin 463d94eab86SWang Xiaoyin gpio4: gpio@e8a0f000 { 464d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 465d94eab86SWang Xiaoyin reg = <0 0xe8a0f000 0 0x1000>; 466d94eab86SWang Xiaoyin interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 467d94eab86SWang Xiaoyin gpio-controller; 468d94eab86SWang Xiaoyin #gpio-cells = <2>; 469d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 30 8>; 470d94eab86SWang Xiaoyin interrupt-controller; 471d94eab86SWang Xiaoyin #interrupt-cells = <2>; 472d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 473d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 474d94eab86SWang Xiaoyin }; 475d94eab86SWang Xiaoyin 476d94eab86SWang Xiaoyin gpio5: gpio@e8a10000 { 477d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 478d94eab86SWang Xiaoyin reg = <0 0xe8a10000 0 0x1000>; 479d94eab86SWang Xiaoyin interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 480d94eab86SWang Xiaoyin gpio-controller; 481d94eab86SWang Xiaoyin #gpio-cells = <2>; 482d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 38 8>; 483d94eab86SWang Xiaoyin interrupt-controller; 484d94eab86SWang Xiaoyin #interrupt-cells = <2>; 485d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 486d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 487d94eab86SWang Xiaoyin }; 488d94eab86SWang Xiaoyin 489d94eab86SWang Xiaoyin gpio6: gpio@e8a11000 { 490d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 491d94eab86SWang Xiaoyin reg = <0 0xe8a11000 0 0x1000>; 492d94eab86SWang Xiaoyin interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 493d94eab86SWang Xiaoyin gpio-controller; 494d94eab86SWang Xiaoyin #gpio-cells = <2>; 495d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 46 8>; 496d94eab86SWang Xiaoyin interrupt-controller; 497d94eab86SWang Xiaoyin #interrupt-cells = <2>; 498d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 499d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 500d94eab86SWang Xiaoyin }; 501d94eab86SWang Xiaoyin 502d94eab86SWang Xiaoyin gpio7: gpio@e8a12000 { 503d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 504d94eab86SWang Xiaoyin reg = <0 0xe8a12000 0 0x1000>; 505d94eab86SWang Xiaoyin interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 506d94eab86SWang Xiaoyin gpio-controller; 507d94eab86SWang Xiaoyin #gpio-cells = <2>; 508d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 54 8>; 509d94eab86SWang Xiaoyin interrupt-controller; 510d94eab86SWang Xiaoyin #interrupt-cells = <2>; 511d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 512d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 513d94eab86SWang Xiaoyin }; 514d94eab86SWang Xiaoyin 515d94eab86SWang Xiaoyin gpio8: gpio@e8a13000 { 516d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 517d94eab86SWang Xiaoyin reg = <0 0xe8a13000 0 0x1000>; 518d94eab86SWang Xiaoyin interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 519d94eab86SWang Xiaoyin gpio-controller; 520d94eab86SWang Xiaoyin #gpio-cells = <2>; 521d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 62 8>; 522d94eab86SWang Xiaoyin interrupt-controller; 523d94eab86SWang Xiaoyin #interrupt-cells = <2>; 524d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 525d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 526d94eab86SWang Xiaoyin }; 527d94eab86SWang Xiaoyin 528d94eab86SWang Xiaoyin gpio9: gpio@e8a14000 { 529d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 530d94eab86SWang Xiaoyin reg = <0 0xe8a14000 0 0x1000>; 531d94eab86SWang Xiaoyin interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 532d94eab86SWang Xiaoyin gpio-controller; 533d94eab86SWang Xiaoyin #gpio-cells = <2>; 534d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 70 8>; 535d94eab86SWang Xiaoyin interrupt-controller; 536d94eab86SWang Xiaoyin #interrupt-cells = <2>; 537d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 538d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 539d94eab86SWang Xiaoyin }; 540d94eab86SWang Xiaoyin 541d94eab86SWang Xiaoyin gpio10: gpio@e8a15000 { 542d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 543d94eab86SWang Xiaoyin reg = <0 0xe8a15000 0 0x1000>; 544d94eab86SWang Xiaoyin interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 545d94eab86SWang Xiaoyin gpio-controller; 546d94eab86SWang Xiaoyin #gpio-cells = <2>; 547d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 78 8>; 548d94eab86SWang Xiaoyin interrupt-controller; 549d94eab86SWang Xiaoyin #interrupt-cells = <2>; 550d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 551d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 552d94eab86SWang Xiaoyin }; 553d94eab86SWang Xiaoyin 554d94eab86SWang Xiaoyin gpio11: gpio@e8a16000 { 555d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 556d94eab86SWang Xiaoyin reg = <0 0xe8a16000 0 0x1000>; 557d94eab86SWang Xiaoyin interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 558d94eab86SWang Xiaoyin gpio-controller; 559d94eab86SWang Xiaoyin #gpio-cells = <2>; 560d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 86 8>; 561d94eab86SWang Xiaoyin interrupt-controller; 562d94eab86SWang Xiaoyin #interrupt-cells = <2>; 563d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 564d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 565d94eab86SWang Xiaoyin }; 566d94eab86SWang Xiaoyin 567d94eab86SWang Xiaoyin gpio12: gpio@e8a17000 { 568d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 569d94eab86SWang Xiaoyin reg = <0 0xe8a17000 0 0x1000>; 570d94eab86SWang Xiaoyin interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 571d94eab86SWang Xiaoyin gpio-controller; 572d94eab86SWang Xiaoyin #gpio-cells = <2>; 573d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 574d94eab86SWang Xiaoyin interrupt-controller; 575d94eab86SWang Xiaoyin #interrupt-cells = <2>; 576d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 577d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 578d94eab86SWang Xiaoyin }; 579d94eab86SWang Xiaoyin 580d94eab86SWang Xiaoyin gpio13: gpio@e8a18000 { 581d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 582d94eab86SWang Xiaoyin reg = <0 0xe8a18000 0 0x1000>; 583d94eab86SWang Xiaoyin interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 584d94eab86SWang Xiaoyin gpio-controller; 585d94eab86SWang Xiaoyin #gpio-cells = <2>; 586d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 102 8>; 587d94eab86SWang Xiaoyin interrupt-controller; 588d94eab86SWang Xiaoyin #interrupt-cells = <2>; 589d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 590d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 591d94eab86SWang Xiaoyin }; 592d94eab86SWang Xiaoyin 593d94eab86SWang Xiaoyin gpio14: gpio@e8a19000 { 594d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 595d94eab86SWang Xiaoyin reg = <0 0xe8a19000 0 0x1000>; 596d94eab86SWang Xiaoyin interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 597d94eab86SWang Xiaoyin gpio-controller; 598d94eab86SWang Xiaoyin #gpio-cells = <2>; 599d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 110 8>; 600d94eab86SWang Xiaoyin interrupt-controller; 601d94eab86SWang Xiaoyin #interrupt-cells = <2>; 602d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 603d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 604d94eab86SWang Xiaoyin }; 605d94eab86SWang Xiaoyin 606d94eab86SWang Xiaoyin gpio15: gpio@e8a1a000 { 607d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 608d94eab86SWang Xiaoyin reg = <0 0xe8a1a000 0 0x1000>; 609d94eab86SWang Xiaoyin interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 610d94eab86SWang Xiaoyin gpio-controller; 611d94eab86SWang Xiaoyin #gpio-cells = <2>; 612d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 118 6>; 613d94eab86SWang Xiaoyin interrupt-controller; 614d94eab86SWang Xiaoyin #interrupt-cells = <2>; 615d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 616d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 617d94eab86SWang Xiaoyin }; 618d94eab86SWang Xiaoyin 619d94eab86SWang Xiaoyin gpio16: gpio@e8a1b000 { 620d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 621d94eab86SWang Xiaoyin reg = <0 0xe8a1b000 0 0x1000>; 622d94eab86SWang Xiaoyin interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 623d94eab86SWang Xiaoyin gpio-controller; 624d94eab86SWang Xiaoyin #gpio-cells = <2>; 625d94eab86SWang Xiaoyin interrupt-controller; 626d94eab86SWang Xiaoyin #interrupt-cells = <2>; 627d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 628d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 629d94eab86SWang Xiaoyin }; 630d94eab86SWang Xiaoyin 631d94eab86SWang Xiaoyin gpio17: gpio@e8a1c000 { 632d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 633d94eab86SWang Xiaoyin reg = <0 0xe8a1c000 0 0x1000>; 634d94eab86SWang Xiaoyin interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 635d94eab86SWang Xiaoyin gpio-controller; 636d94eab86SWang Xiaoyin #gpio-cells = <2>; 637d94eab86SWang Xiaoyin interrupt-controller; 638d94eab86SWang Xiaoyin #interrupt-cells = <2>; 639d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 640d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 641d94eab86SWang Xiaoyin }; 642d94eab86SWang Xiaoyin 643d94eab86SWang Xiaoyin gpio18: gpio@ff3b4000 { 644d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 645d94eab86SWang Xiaoyin reg = <0 0xff3b4000 0 0x1000>; 646d94eab86SWang Xiaoyin interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 647d94eab86SWang Xiaoyin gpio-controller; 648d94eab86SWang Xiaoyin #gpio-cells = <2>; 649d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 0 8>; 650d94eab86SWang Xiaoyin interrupt-controller; 651d94eab86SWang Xiaoyin #interrupt-cells = <2>; 652d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 653d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 654d94eab86SWang Xiaoyin }; 655d94eab86SWang Xiaoyin 656d94eab86SWang Xiaoyin gpio19: gpio@ff3b5000 { 657d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 658d94eab86SWang Xiaoyin reg = <0 0xff3b5000 0 0x1000>; 659d94eab86SWang Xiaoyin interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 660d94eab86SWang Xiaoyin gpio-controller; 661d94eab86SWang Xiaoyin #gpio-cells = <2>; 662d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 8 4>; 663d94eab86SWang Xiaoyin interrupt-controller; 664d94eab86SWang Xiaoyin #interrupt-cells = <2>; 665d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 666d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 667d94eab86SWang Xiaoyin }; 668d94eab86SWang Xiaoyin 669d94eab86SWang Xiaoyin gpio20: gpio@e8a1f000 { 670d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 671d94eab86SWang Xiaoyin reg = <0 0xe8a1f000 0 0x1000>; 672d94eab86SWang Xiaoyin interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 673d94eab86SWang Xiaoyin gpio-controller; 674d94eab86SWang Xiaoyin #gpio-cells = <2>; 675d94eab86SWang Xiaoyin gpio-ranges = <&pmx1 0 0 6>; 676d94eab86SWang Xiaoyin interrupt-controller; 677d94eab86SWang Xiaoyin #interrupt-cells = <2>; 678d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 679d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 680d94eab86SWang Xiaoyin }; 681d94eab86SWang Xiaoyin 682d94eab86SWang Xiaoyin gpio21: gpio@e8a20000 { 683d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 684d94eab86SWang Xiaoyin reg = <0 0xe8a20000 0 0x1000>; 685d94eab86SWang Xiaoyin interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 686d94eab86SWang Xiaoyin gpio-controller; 687d94eab86SWang Xiaoyin #gpio-cells = <2>; 688d94eab86SWang Xiaoyin interrupt-controller; 689d94eab86SWang Xiaoyin #interrupt-cells = <2>; 690d94eab86SWang Xiaoyin gpio-ranges = <&pmx3 0 0 6>; 691d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 692d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 693d94eab86SWang Xiaoyin }; 694d94eab86SWang Xiaoyin 695d94eab86SWang Xiaoyin gpio22: gpio@fff0b000 { 696d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 697d94eab86SWang Xiaoyin reg = <0 0xfff0b000 0 0x1000>; 698d94eab86SWang Xiaoyin interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 699d94eab86SWang Xiaoyin gpio-controller; 700d94eab86SWang Xiaoyin #gpio-cells = <2>; 701d94eab86SWang Xiaoyin /* GPIO176 */ 702d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 2 0 6>; 703d94eab86SWang Xiaoyin interrupt-controller; 704d94eab86SWang Xiaoyin #interrupt-cells = <2>; 705d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 706d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 707d94eab86SWang Xiaoyin }; 708d94eab86SWang Xiaoyin 709d94eab86SWang Xiaoyin gpio23: gpio@fff0c000 { 710d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 711d94eab86SWang Xiaoyin reg = <0 0xfff0c000 0 0x1000>; 712d94eab86SWang Xiaoyin interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 713d94eab86SWang Xiaoyin gpio-controller; 714d94eab86SWang Xiaoyin #gpio-cells = <2>; 715d94eab86SWang Xiaoyin /* GPIO184 */ 716d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 6 7>; 717d94eab86SWang Xiaoyin interrupt-controller; 718d94eab86SWang Xiaoyin #interrupt-cells = <2>; 719d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 720d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 721d94eab86SWang Xiaoyin }; 722d94eab86SWang Xiaoyin 723d94eab86SWang Xiaoyin gpio24: gpio@fff0d000 { 724d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 725d94eab86SWang Xiaoyin reg = <0 0xfff0d000 0 0x1000>; 726d94eab86SWang Xiaoyin interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 727d94eab86SWang Xiaoyin gpio-controller; 728d94eab86SWang Xiaoyin #gpio-cells = <2>; 729d94eab86SWang Xiaoyin /* GPIO192 */ 730d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 13 8>; 731d94eab86SWang Xiaoyin interrupt-controller; 732d94eab86SWang Xiaoyin #interrupt-cells = <2>; 733d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 734d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 735d94eab86SWang Xiaoyin }; 736d94eab86SWang Xiaoyin 737d94eab86SWang Xiaoyin gpio25: gpio@fff0e000 { 738d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 739d94eab86SWang Xiaoyin reg = <0 0xfff0e000 0 0x1000>; 740d94eab86SWang Xiaoyin interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 741d94eab86SWang Xiaoyin gpio-controller; 742d94eab86SWang Xiaoyin #gpio-cells = <2>; 743d94eab86SWang Xiaoyin /* GPIO200 */ 744d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 745d94eab86SWang Xiaoyin interrupt-controller; 746d94eab86SWang Xiaoyin #interrupt-cells = <2>; 747d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 748d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 749d94eab86SWang Xiaoyin }; 750d94eab86SWang Xiaoyin 751d94eab86SWang Xiaoyin gpio26: gpio@fff0f000 { 752d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 753d94eab86SWang Xiaoyin reg = <0 0xfff0f000 0 0x1000>; 754d94eab86SWang Xiaoyin interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 755d94eab86SWang Xiaoyin gpio-controller; 756d94eab86SWang Xiaoyin #gpio-cells = <2>; 757d94eab86SWang Xiaoyin /* GPIO208 */ 758d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 28 8>; 759d94eab86SWang Xiaoyin interrupt-controller; 760d94eab86SWang Xiaoyin #interrupt-cells = <2>; 761d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 762d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 763d94eab86SWang Xiaoyin }; 764d94eab86SWang Xiaoyin 765d94eab86SWang Xiaoyin gpio27: gpio@fff10000 { 766d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 767d94eab86SWang Xiaoyin reg = <0 0xfff10000 0 0x1000>; 768d94eab86SWang Xiaoyin interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 769d94eab86SWang Xiaoyin gpio-controller; 770d94eab86SWang Xiaoyin #gpio-cells = <2>; 771d94eab86SWang Xiaoyin /* GPIO216 */ 772d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 36 6>; 773d94eab86SWang Xiaoyin interrupt-controller; 774d94eab86SWang Xiaoyin #interrupt-cells = <2>; 775d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 776d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 777d94eab86SWang Xiaoyin }; 778d94eab86SWang Xiaoyin 779d94eab86SWang Xiaoyin gpio28: gpio@fff1d000 { 780d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 781d94eab86SWang Xiaoyin reg = <0 0xfff1d000 0 0x1000>; 782d94eab86SWang Xiaoyin interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 783d94eab86SWang Xiaoyin gpio-controller; 784d94eab86SWang Xiaoyin #gpio-cells = <2>; 785d94eab86SWang Xiaoyin interrupt-controller; 786d94eab86SWang Xiaoyin #interrupt-cells = <2>; 787d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 788d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 789d94eab86SWang Xiaoyin }; 79038810497SWang Xiaoyin 79138810497SWang Xiaoyin spi2: spi@ffd68000 { 79238810497SWang Xiaoyin compatible = "arm,pl022", "arm,primecell"; 79338810497SWang Xiaoyin reg = <0x0 0xffd68000 0x0 0x1000>; 79438810497SWang Xiaoyin #address-cells = <1>; 79538810497SWang Xiaoyin #size-cells = <0>; 79638810497SWang Xiaoyin interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 79738810497SWang Xiaoyin clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; 79838810497SWang Xiaoyin clock-names = "apb_pclk"; 79938810497SWang Xiaoyin pinctrl-names = "default"; 80038810497SWang Xiaoyin pinctrl-0 = <&spi2_pmx_func>; 80138810497SWang Xiaoyin num-cs = <1>; 80238810497SWang Xiaoyin cs-gpios = <&gpio27 2 0>; 80338810497SWang Xiaoyin status = "disabled"; 80438810497SWang Xiaoyin }; 80538810497SWang Xiaoyin 80638810497SWang Xiaoyin spi3: spi@ff3b3000 { 80738810497SWang Xiaoyin compatible = "arm,pl022", "arm,primecell"; 80838810497SWang Xiaoyin reg = <0x0 0xff3b3000 0x0 0x1000>; 80938810497SWang Xiaoyin #address-cells = <1>; 81038810497SWang Xiaoyin #size-cells = <0>; 81138810497SWang Xiaoyin interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 81238810497SWang Xiaoyin clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; 81338810497SWang Xiaoyin clock-names = "apb_pclk"; 81438810497SWang Xiaoyin pinctrl-names = "default"; 81538810497SWang Xiaoyin pinctrl-0 = <&spi3_pmx_func>; 81638810497SWang Xiaoyin num-cs = <1>; 81738810497SWang Xiaoyin cs-gpios = <&gpio18 5 0>; 81838810497SWang Xiaoyin status = "disabled"; 81938810497SWang Xiaoyin }; 82096909778SXiaowei Song 82196909778SXiaowei Song pcie@f4000000 { 82296909778SXiaowei Song compatible = "hisilicon,kirin960-pcie"; 82396909778SXiaowei Song reg = <0x0 0xf4000000 0x0 0x1000>, 82496909778SXiaowei Song <0x0 0xff3fe000 0x0 0x1000>, 82596909778SXiaowei Song <0x0 0xf3f20000 0x0 0x40000>, 82696909778SXiaowei Song <0x0 0xf5000000 0x0 0x2000>; 82796909778SXiaowei Song reg-names = "dbi", "apb", "phy", "config"; 82896909778SXiaowei Song bus-range = <0x0 0x1>; 82996909778SXiaowei Song #address-cells = <3>; 83096909778SXiaowei Song #size-cells = <2>; 83196909778SXiaowei Song device_type = "pci"; 83296909778SXiaowei Song ranges = <0x02000000 0x0 0x00000000 83396909778SXiaowei Song 0x0 0xf6000000 83496909778SXiaowei Song 0x0 0x02000000>; 83596909778SXiaowei Song num-lanes = <1>; 83696909778SXiaowei Song #interrupt-cells = <1>; 83796909778SXiaowei Song interrupt-map-mask = <0xf800 0 0 7>; 83896909778SXiaowei Song interrupt-map = <0x0 0 0 1 83996909778SXiaowei Song &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 84096909778SXiaowei Song <0x0 0 0 2 84196909778SXiaowei Song &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 84296909778SXiaowei Song <0x0 0 0 3 84396909778SXiaowei Song &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 84496909778SXiaowei Song <0x0 0 0 4 84596909778SXiaowei Song &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 84696909778SXiaowei Song clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 84796909778SXiaowei Song <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 84896909778SXiaowei Song <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 84996909778SXiaowei Song <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 85096909778SXiaowei Song <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 85196909778SXiaowei Song clock-names = "pcie_phy_ref", "pcie_aux", 85296909778SXiaowei Song "pcie_apb_phy", "pcie_apb_sys", 85396909778SXiaowei Song "pcie_aclk"; 85496909778SXiaowei Song reset-gpios = <&gpio11 1 0 >; 85596909778SXiaowei Song }; 856804d7d7aSLi Wei 857804d7d7aSLi Wei /* SD */ 858804d7d7aSLi Wei dwmmc1: dwmmc1@ff37f000 { 859804d7d7aSLi Wei #address-cells = <1>; 860804d7d7aSLi Wei #size-cells = <0>; 861804d7d7aSLi Wei cd-inverted; 862804d7d7aSLi Wei compatible = "hisilicon,hi3660-dw-mshc"; 863804d7d7aSLi Wei num-slots = <1>; 864804d7d7aSLi Wei bus-width = <0x4>; 865804d7d7aSLi Wei disable-wp; 866804d7d7aSLi Wei cap-sd-highspeed; 867804d7d7aSLi Wei supports-highspeed; 868804d7d7aSLi Wei card-detect-delay = <200>; 869804d7d7aSLi Wei reg = <0x0 0xff37f000 0x0 0x1000>; 870804d7d7aSLi Wei interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 871804d7d7aSLi Wei clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, 872804d7d7aSLi Wei <&crg_ctrl HI3660_HCLK_GATE_SD>; 873804d7d7aSLi Wei clock-names = "ciu", "biu"; 874804d7d7aSLi Wei clock-frequency = <3200000>; 875804d7d7aSLi Wei resets = <&crg_rst 0x94 18>; 876804d7d7aSLi Wei cd-gpios = <&gpio25 3 0>; 877804d7d7aSLi Wei hisilicon,peripheral-syscon = <&sctrl>; 878804d7d7aSLi Wei pinctrl-names = "default"; 879804d7d7aSLi Wei pinctrl-0 = <&sd_pmx_func 880804d7d7aSLi Wei &sd_clk_cfg_func 881804d7d7aSLi Wei &sd_cfg_func>; 882804d7d7aSLi Wei sd-uhs-sdr12; 883804d7d7aSLi Wei sd-uhs-sdr25; 884804d7d7aSLi Wei sd-uhs-sdr50; 885804d7d7aSLi Wei sd-uhs-sdr104; 886804d7d7aSLi Wei status = "disabled"; 887804d7d7aSLi Wei 888804d7d7aSLi Wei slot@0 { 889804d7d7aSLi Wei reg = <0x0>; 890804d7d7aSLi Wei bus-width = <4>; 891804d7d7aSLi Wei disable-wp; 892804d7d7aSLi Wei }; 893804d7d7aSLi Wei }; 894804d7d7aSLi Wei 895804d7d7aSLi Wei /* SDIO */ 896804d7d7aSLi Wei dwmmc2: dwmmc2@ff3ff000 { 897804d7d7aSLi Wei compatible = "hisilicon,hi3660-dw-mshc"; 898804d7d7aSLi Wei reg = <0x0 0xff3ff000 0x0 0x1000>; 899804d7d7aSLi Wei interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 900804d7d7aSLi Wei num-slots = <1>; 901804d7d7aSLi Wei clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, 902804d7d7aSLi Wei <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; 903804d7d7aSLi Wei clock-names = "ciu", "biu"; 904804d7d7aSLi Wei resets = <&crg_rst 0x94 20>; 905804d7d7aSLi Wei card-detect-delay = <200>; 906804d7d7aSLi Wei supports-highspeed; 907804d7d7aSLi Wei keep-power-in-suspend; 908804d7d7aSLi Wei pinctrl-names = "default"; 909804d7d7aSLi Wei pinctrl-0 = <&sdio_pmx_func 910804d7d7aSLi Wei &sdio_clk_cfg_func 911804d7d7aSLi Wei &sdio_cfg_func>; 912804d7d7aSLi Wei status = "disabled"; 913804d7d7aSLi Wei }; 91435ca8168SChen Feng }; 91535ca8168SChen Feng}; 916