1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 235ca8168SChen Feng/* 335ca8168SChen Feng * dts file for Hisilicon Hi3660 SoC 435ca8168SChen Feng * 535ca8168SChen Feng * Copyright (C) 2016, Hisilicon Ltd. 635ca8168SChen Feng */ 735ca8168SChen Feng 835ca8168SChen Feng#include <dt-bindings/interrupt-controller/arm-gic.h> 9a4e36ae0SZhangfei Gao#include <dt-bindings/clock/hi3660-clock.h> 108d93e94bSTao Wang#include <dt-bindings/thermal/thermal.h> 1135ca8168SChen Feng 1235ca8168SChen Feng/ { 1335ca8168SChen Feng compatible = "hisilicon,hi3660"; 1435ca8168SChen Feng interrupt-parent = <&gic>; 1535ca8168SChen Feng #address-cells = <2>; 1635ca8168SChen Feng #size-cells = <2>; 1735ca8168SChen Feng 1835ca8168SChen Feng psci { 1935ca8168SChen Feng compatible = "arm,psci-0.2"; 2035ca8168SChen Feng method = "smc"; 2135ca8168SChen Feng }; 2235ca8168SChen Feng 2335ca8168SChen Feng cpus { 2435ca8168SChen Feng #address-cells = <2>; 2535ca8168SChen Feng #size-cells = <0>; 2635ca8168SChen Feng 2735ca8168SChen Feng cpu-map { 2835ca8168SChen Feng cluster0 { 2935ca8168SChen Feng core0 { 3035ca8168SChen Feng cpu = <&cpu0>; 3135ca8168SChen Feng }; 3235ca8168SChen Feng core1 { 3335ca8168SChen Feng cpu = <&cpu1>; 3435ca8168SChen Feng }; 3535ca8168SChen Feng core2 { 3635ca8168SChen Feng cpu = <&cpu2>; 3735ca8168SChen Feng }; 3835ca8168SChen Feng core3 { 3935ca8168SChen Feng cpu = <&cpu3>; 4035ca8168SChen Feng }; 4135ca8168SChen Feng }; 4235ca8168SChen Feng cluster1 { 4335ca8168SChen Feng core0 { 4435ca8168SChen Feng cpu = <&cpu4>; 4535ca8168SChen Feng }; 4635ca8168SChen Feng core1 { 4735ca8168SChen Feng cpu = <&cpu5>; 4835ca8168SChen Feng }; 4935ca8168SChen Feng core2 { 5035ca8168SChen Feng cpu = <&cpu6>; 5135ca8168SChen Feng }; 5235ca8168SChen Feng core3 { 5335ca8168SChen Feng cpu = <&cpu7>; 5435ca8168SChen Feng }; 5535ca8168SChen Feng }; 5635ca8168SChen Feng }; 5735ca8168SChen Feng 5835ca8168SChen Feng cpu0: cpu@0 { 5935ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 6035ca8168SChen Feng device_type = "cpu"; 6135ca8168SChen Feng reg = <0x0 0x0>; 6235ca8168SChen Feng enable-method = "psci"; 63a6d08344SLeo Yan next-level-cache = <&A53_L2>; 6430fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 659a9760deSValentin Schneider capacity-dmips-mhz = <592>; 66dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 67dfeae9e5SLeo Yan operating-points-v2 = <&cluster0_opp>; 688d93e94bSTao Wang #cooling-cells = <2>; 698d93e94bSTao Wang dynamic-power-coefficient = <110>; 7035ca8168SChen Feng }; 7135ca8168SChen Feng 7235ca8168SChen Feng cpu1: cpu@1 { 7335ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 7435ca8168SChen Feng device_type = "cpu"; 7535ca8168SChen Feng reg = <0x0 0x1>; 7635ca8168SChen Feng enable-method = "psci"; 77a6d08344SLeo Yan next-level-cache = <&A53_L2>; 7830fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 799a9760deSValentin Schneider capacity-dmips-mhz = <592>; 80dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 81dfeae9e5SLeo Yan operating-points-v2 = <&cluster0_opp>; 8235ca8168SChen Feng }; 8335ca8168SChen Feng 8435ca8168SChen Feng cpu2: cpu@2 { 8535ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 8635ca8168SChen Feng device_type = "cpu"; 8735ca8168SChen Feng reg = <0x0 0x2>; 8835ca8168SChen Feng enable-method = "psci"; 89a6d08344SLeo Yan next-level-cache = <&A53_L2>; 9030fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 919a9760deSValentin Schneider capacity-dmips-mhz = <592>; 92dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 93dfeae9e5SLeo Yan operating-points-v2 = <&cluster0_opp>; 9435ca8168SChen Feng }; 9535ca8168SChen Feng 9635ca8168SChen Feng cpu3: cpu@3 { 9735ca8168SChen Feng compatible = "arm,cortex-a53", "arm,armv8"; 9835ca8168SChen Feng device_type = "cpu"; 9935ca8168SChen Feng reg = <0x0 0x3>; 10035ca8168SChen Feng enable-method = "psci"; 101a6d08344SLeo Yan next-level-cache = <&A53_L2>; 10230fec826SLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 1039a9760deSValentin Schneider capacity-dmips-mhz = <592>; 104dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 105dfeae9e5SLeo Yan operating-points-v2 = <&cluster0_opp>; 10635ca8168SChen Feng }; 10735ca8168SChen Feng 10835ca8168SChen Feng cpu4: cpu@100 { 10935ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 11035ca8168SChen Feng device_type = "cpu"; 11135ca8168SChen Feng reg = <0x0 0x100>; 11235ca8168SChen Feng enable-method = "psci"; 113a6d08344SLeo Yan next-level-cache = <&A73_L2>; 114928c4a5cSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 1159a9760deSValentin Schneider capacity-dmips-mhz = <1024>; 116dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 117dfeae9e5SLeo Yan operating-points-v2 = <&cluster1_opp>; 1188d93e94bSTao Wang #cooling-cells = <2>; 1198d93e94bSTao Wang dynamic-power-coefficient = <550>; 12035ca8168SChen Feng }; 12135ca8168SChen Feng 12235ca8168SChen Feng cpu5: cpu@101 { 12335ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 12435ca8168SChen Feng device_type = "cpu"; 12535ca8168SChen Feng reg = <0x0 0x101>; 12635ca8168SChen Feng enable-method = "psci"; 127a6d08344SLeo Yan next-level-cache = <&A73_L2>; 128928c4a5cSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 1299a9760deSValentin Schneider capacity-dmips-mhz = <1024>; 130dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 131dfeae9e5SLeo Yan operating-points-v2 = <&cluster1_opp>; 13235ca8168SChen Feng }; 13335ca8168SChen Feng 13435ca8168SChen Feng cpu6: cpu@102 { 13535ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 13635ca8168SChen Feng device_type = "cpu"; 13735ca8168SChen Feng reg = <0x0 0x102>; 13835ca8168SChen Feng enable-method = "psci"; 139a6d08344SLeo Yan next-level-cache = <&A73_L2>; 140928c4a5cSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 1419a9760deSValentin Schneider capacity-dmips-mhz = <1024>; 142dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 143dfeae9e5SLeo Yan operating-points-v2 = <&cluster1_opp>; 14435ca8168SChen Feng }; 14535ca8168SChen Feng 14635ca8168SChen Feng cpu7: cpu@103 { 14735ca8168SChen Feng compatible = "arm,cortex-a73", "arm,armv8"; 14835ca8168SChen Feng device_type = "cpu"; 14935ca8168SChen Feng reg = <0x0 0x103>; 15035ca8168SChen Feng enable-method = "psci"; 151a6d08344SLeo Yan next-level-cache = <&A73_L2>; 152928c4a5cSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 1539a9760deSValentin Schneider capacity-dmips-mhz = <1024>; 154dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 155dfeae9e5SLeo Yan operating-points-v2 = <&cluster1_opp>; 15630fec826SLeo Yan }; 15730fec826SLeo Yan 15830fec826SLeo Yan idle-states { 15930fec826SLeo Yan entry-method = "psci"; 16030fec826SLeo Yan 16130fec826SLeo Yan CPU_SLEEP: cpu-sleep { 16230fec826SLeo Yan compatible = "arm,idle-state"; 16330fec826SLeo Yan local-timer-stop; 16430fec826SLeo Yan arm,psci-suspend-param = <0x0010000>; 16530fec826SLeo Yan entry-latency-us = <40>; 16630fec826SLeo Yan exit-latency-us = <70>; 16730fec826SLeo Yan min-residency-us = <3000>; 16830fec826SLeo Yan }; 16930fec826SLeo Yan 17030fec826SLeo Yan CLUSTER_SLEEP_0: cluster-sleep-0 { 17130fec826SLeo Yan compatible = "arm,idle-state"; 17230fec826SLeo Yan local-timer-stop; 17330fec826SLeo Yan arm,psci-suspend-param = <0x1010000>; 17430fec826SLeo Yan entry-latency-us = <500>; 17530fec826SLeo Yan exit-latency-us = <5000>; 17630fec826SLeo Yan min-residency-us = <20000>; 17730fec826SLeo Yan }; 17830fec826SLeo Yan 17930fec826SLeo Yan CLUSTER_SLEEP_1: cluster-sleep-1 { 18030fec826SLeo Yan compatible = "arm,idle-state"; 18130fec826SLeo Yan local-timer-stop; 18230fec826SLeo Yan arm,psci-suspend-param = <0x1010000>; 18330fec826SLeo Yan entry-latency-us = <1000>; 18430fec826SLeo Yan exit-latency-us = <5000>; 18530fec826SLeo Yan min-residency-us = <20000>; 18630fec826SLeo Yan }; 18735ca8168SChen Feng }; 188a6d08344SLeo Yan 189a6d08344SLeo Yan A53_L2: l2-cache0 { 190a6d08344SLeo Yan compatible = "cache"; 191a6d08344SLeo Yan }; 192a6d08344SLeo Yan 193a6d08344SLeo Yan A73_L2: l2-cache1 { 194a6d08344SLeo Yan compatible = "cache"; 195a6d08344SLeo Yan }; 19635ca8168SChen Feng }; 19735ca8168SChen Feng 198dfeae9e5SLeo Yan cluster0_opp: opp_table0 { 199dfeae9e5SLeo Yan compatible = "operating-points-v2"; 200dfeae9e5SLeo Yan opp-shared; 201dfeae9e5SLeo Yan 202dfeae9e5SLeo Yan opp00 { 203dfeae9e5SLeo Yan opp-hz = /bits/ 64 <533000000>; 204dfeae9e5SLeo Yan opp-microvolt = <700000>; 205dfeae9e5SLeo Yan clock-latency-ns = <300000>; 206dfeae9e5SLeo Yan }; 207dfeae9e5SLeo Yan 208dfeae9e5SLeo Yan opp01 { 209dfeae9e5SLeo Yan opp-hz = /bits/ 64 <999000000>; 210dfeae9e5SLeo Yan opp-microvolt = <800000>; 211dfeae9e5SLeo Yan clock-latency-ns = <300000>; 212dfeae9e5SLeo Yan }; 213dfeae9e5SLeo Yan 214dfeae9e5SLeo Yan opp02 { 215dfeae9e5SLeo Yan opp-hz = /bits/ 64 <1402000000>; 216dfeae9e5SLeo Yan opp-microvolt = <900000>; 217dfeae9e5SLeo Yan clock-latency-ns = <300000>; 218dfeae9e5SLeo Yan }; 219dfeae9e5SLeo Yan 220dfeae9e5SLeo Yan opp03 { 221dfeae9e5SLeo Yan opp-hz = /bits/ 64 <1709000000>; 222dfeae9e5SLeo Yan opp-microvolt = <1000000>; 223dfeae9e5SLeo Yan clock-latency-ns = <300000>; 224dfeae9e5SLeo Yan }; 225dfeae9e5SLeo Yan 226dfeae9e5SLeo Yan opp04 { 227dfeae9e5SLeo Yan opp-hz = /bits/ 64 <1844000000>; 228dfeae9e5SLeo Yan opp-microvolt = <1100000>; 229dfeae9e5SLeo Yan clock-latency-ns = <300000>; 230dfeae9e5SLeo Yan }; 231dfeae9e5SLeo Yan }; 232dfeae9e5SLeo Yan 233dfeae9e5SLeo Yan cluster1_opp: opp_table1 { 234dfeae9e5SLeo Yan compatible = "operating-points-v2"; 235dfeae9e5SLeo Yan opp-shared; 236dfeae9e5SLeo Yan 237dfeae9e5SLeo Yan opp10 { 238dfeae9e5SLeo Yan opp-hz = /bits/ 64 <903000000>; 239dfeae9e5SLeo Yan opp-microvolt = <700000>; 240dfeae9e5SLeo Yan clock-latency-ns = <300000>; 241dfeae9e5SLeo Yan }; 242dfeae9e5SLeo Yan 243dfeae9e5SLeo Yan opp11 { 244dfeae9e5SLeo Yan opp-hz = /bits/ 64 <1421000000>; 245dfeae9e5SLeo Yan opp-microvolt = <800000>; 246dfeae9e5SLeo Yan clock-latency-ns = <300000>; 247dfeae9e5SLeo Yan }; 248dfeae9e5SLeo Yan 249dfeae9e5SLeo Yan opp12 { 250dfeae9e5SLeo Yan opp-hz = /bits/ 64 <1805000000>; 251dfeae9e5SLeo Yan opp-microvolt = <900000>; 252dfeae9e5SLeo Yan clock-latency-ns = <300000>; 253dfeae9e5SLeo Yan }; 254dfeae9e5SLeo Yan 255dfeae9e5SLeo Yan opp13 { 256dfeae9e5SLeo Yan opp-hz = /bits/ 64 <2112000000>; 257dfeae9e5SLeo Yan opp-microvolt = <1000000>; 258dfeae9e5SLeo Yan clock-latency-ns = <300000>; 259dfeae9e5SLeo Yan }; 260dfeae9e5SLeo Yan 261dfeae9e5SLeo Yan opp14 { 262dfeae9e5SLeo Yan opp-hz = /bits/ 64 <2362000000>; 263dfeae9e5SLeo Yan opp-microvolt = <1100000>; 264dfeae9e5SLeo Yan clock-latency-ns = <300000>; 265dfeae9e5SLeo Yan }; 266dfeae9e5SLeo Yan }; 267dfeae9e5SLeo Yan 26835ca8168SChen Feng gic: interrupt-controller@e82b0000 { 26935ca8168SChen Feng compatible = "arm,gic-400"; 27035ca8168SChen Feng reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 27135ca8168SChen Feng <0x0 0xe82b2000 0 0x2000>, /* GICC */ 27235ca8168SChen Feng <0x0 0xe82b4000 0 0x2000>, /* GICH */ 27335ca8168SChen Feng <0x0 0xe82b6000 0 0x2000>; /* GICV */ 27435ca8168SChen Feng #address-cells = <0>; 27535ca8168SChen Feng #interrupt-cells = <3>; 27635ca8168SChen Feng interrupt-controller; 27735ca8168SChen Feng interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 27835ca8168SChen Feng IRQ_TYPE_LEVEL_HIGH)>; 27935ca8168SChen Feng }; 28035ca8168SChen Feng 281e07642faSXu YiPing a53-pmu { 282e07642faSXu YiPing compatible = "arm,cortex-a53-pmu"; 283f8054fb8SYiPing Xu interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 284f8054fb8SYiPing Xu <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 285f8054fb8SYiPing Xu <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 286e07642faSXu YiPing <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 287f8054fb8SYiPing Xu interrupt-affinity = <&cpu0>, 288f8054fb8SYiPing Xu <&cpu1>, 289f8054fb8SYiPing Xu <&cpu2>, 290e07642faSXu YiPing <&cpu3>; 291e07642faSXu YiPing }; 292e07642faSXu YiPing 293e07642faSXu YiPing a73-pmu { 294e07642faSXu YiPing compatible = "arm,cortex-a73-pmu"; 295e07642faSXu YiPing interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 296e07642faSXu YiPing <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 297e07642faSXu YiPing <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 298e07642faSXu YiPing <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 299e07642faSXu YiPing interrupt-affinity = <&cpu4>, 300f8054fb8SYiPing Xu <&cpu5>, 301f8054fb8SYiPing Xu <&cpu6>, 302f8054fb8SYiPing Xu <&cpu7>; 303f8054fb8SYiPing Xu }; 304f8054fb8SYiPing Xu 30535ca8168SChen Feng timer { 30635ca8168SChen Feng compatible = "arm,armv8-timer"; 30735ca8168SChen Feng interrupt-parent = <&gic>; 30835ca8168SChen Feng interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 30935ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 31035ca8168SChen Feng <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 31135ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 31235ca8168SChen Feng <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 31335ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 31435ca8168SChen Feng <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 31535ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>; 31635ca8168SChen Feng }; 31735ca8168SChen Feng 31835ca8168SChen Feng soc { 31935ca8168SChen Feng compatible = "simple-bus"; 32035ca8168SChen Feng #address-cells = <2>; 32135ca8168SChen Feng #size-cells = <2>; 32235ca8168SChen Feng ranges; 32335ca8168SChen Feng 324a4e36ae0SZhangfei Gao crg_ctrl: crg_ctrl@fff35000 { 325a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-crgctrl", "syscon"; 326a4e36ae0SZhangfei Gao reg = <0x0 0xfff35000 0x0 0x1000>; 327a4e36ae0SZhangfei Gao #clock-cells = <1>; 32835ca8168SChen Feng }; 32935ca8168SChen Feng 330a4e36ae0SZhangfei Gao crg_rst: crg_rst_controller { 331a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 332a4e36ae0SZhangfei Gao #reset-cells = <2>; 333a4e36ae0SZhangfei Gao hisi,rst-syscon = <&crg_ctrl>; 334a4e36ae0SZhangfei Gao }; 335a4e36ae0SZhangfei Gao 336a4e36ae0SZhangfei Gao 337a4e36ae0SZhangfei Gao pctrl: pctrl@e8a09000 { 338a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pctrl", "syscon"; 339a4e36ae0SZhangfei Gao reg = <0x0 0xe8a09000 0x0 0x2000>; 340a4e36ae0SZhangfei Gao #clock-cells = <1>; 341a4e36ae0SZhangfei Gao }; 342a4e36ae0SZhangfei Gao 343a4e36ae0SZhangfei Gao pmuctrl: crg_ctrl@fff34000 { 344a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 345a4e36ae0SZhangfei Gao reg = <0x0 0xfff34000 0x0 0x1000>; 346a4e36ae0SZhangfei Gao #clock-cells = <1>; 347a4e36ae0SZhangfei Gao }; 348a4e36ae0SZhangfei Gao 349a4e36ae0SZhangfei Gao sctrl: sctrl@fff0a000 { 350a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-sctrl", "syscon"; 351a4e36ae0SZhangfei Gao reg = <0x0 0xfff0a000 0x0 0x1000>; 352a4e36ae0SZhangfei Gao #clock-cells = <1>; 353a4e36ae0SZhangfei Gao }; 354a4e36ae0SZhangfei Gao 355a4e36ae0SZhangfei Gao iomcu: iomcu@ffd7e000 { 356a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-iomcu", "syscon"; 357a4e36ae0SZhangfei Gao reg = <0x0 0xffd7e000 0x0 0x1000>; 358a4e36ae0SZhangfei Gao #clock-cells = <1>; 359a4e36ae0SZhangfei Gao 360a4e36ae0SZhangfei Gao }; 361a4e36ae0SZhangfei Gao 362a4e36ae0SZhangfei Gao iomcu_rst: reset { 363a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 364a4e36ae0SZhangfei Gao hisi,rst-syscon = <&iomcu>; 365a4e36ae0SZhangfei Gao #reset-cells = <2>; 366a4e36ae0SZhangfei Gao }; 367a4e36ae0SZhangfei Gao 368ca905780SKaihua Zhong mailbox: mailbox@e896b000 { 369ca905780SKaihua Zhong compatible = "hisilicon,hi3660-mbox"; 370ca905780SKaihua Zhong reg = <0x0 0xe896b000 0x0 0x1000>; 371ca905780SKaihua Zhong interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 372ca905780SKaihua Zhong <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 373ca905780SKaihua Zhong #mbox-cells = <3>; 374ca905780SKaihua Zhong }; 375ca905780SKaihua Zhong 3766e2c52b3SKaihua Zhong stub_clock: stub_clock@e896b500 { 3776e2c52b3SKaihua Zhong compatible = "hisilicon,hi3660-stub-clk"; 3786e2c52b3SKaihua Zhong reg = <0x0 0xe896b500 0x0 0x0100>; 3796e2c52b3SKaihua Zhong #clock-cells = <1>; 3806e2c52b3SKaihua Zhong mboxes = <&mailbox 13 3 0>; 3816e2c52b3SKaihua Zhong }; 3826e2c52b3SKaihua Zhong 38375196330SLeo Yan dual_timer0: timer@fff14000 { 38475196330SLeo Yan compatible = "arm,sp804", "arm,primecell"; 38575196330SLeo Yan reg = <0x0 0xfff14000 0x0 0x1000>; 38675196330SLeo Yan interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 38775196330SLeo Yan <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 38875196330SLeo Yan clocks = <&crg_ctrl HI3660_OSC32K>, 38975196330SLeo Yan <&crg_ctrl HI3660_OSC32K>, 39075196330SLeo Yan <&crg_ctrl HI3660_OSC32K>; 39175196330SLeo Yan clock-names = "timer1", "timer2", "apb_pclk"; 39275196330SLeo Yan }; 39375196330SLeo Yan 3945f8a3b77SZhangfei Gao i2c0: i2c@ffd71000 { 3955f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 3965f8a3b77SZhangfei Gao reg = <0x0 0xffd71000 0x0 0x1000>; 3975f8a3b77SZhangfei Gao interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 3985f8a3b77SZhangfei Gao #address-cells = <1>; 3995f8a3b77SZhangfei Gao #size-cells = <0>; 4005f8a3b77SZhangfei Gao clock-frequency = <400000>; 4015f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 4025f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 3>; 4035f8a3b77SZhangfei Gao pinctrl-names = "default"; 4045f8a3b77SZhangfei Gao pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 4055f8a3b77SZhangfei Gao status = "disabled"; 4065f8a3b77SZhangfei Gao }; 4075f8a3b77SZhangfei Gao 4085f8a3b77SZhangfei Gao i2c1: i2c@ffd72000 { 4095f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 4105f8a3b77SZhangfei Gao reg = <0x0 0xffd72000 0x0 0x1000>; 4115f8a3b77SZhangfei Gao interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 4125f8a3b77SZhangfei Gao #address-cells = <1>; 4135f8a3b77SZhangfei Gao #size-cells = <0>; 4145f8a3b77SZhangfei Gao clock-frequency = <400000>; 4155f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 4165f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 4>; 4175f8a3b77SZhangfei Gao pinctrl-names = "default"; 4185f8a3b77SZhangfei Gao pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 4195f8a3b77SZhangfei Gao status = "disabled"; 4205f8a3b77SZhangfei Gao }; 4215f8a3b77SZhangfei Gao 4225f8a3b77SZhangfei Gao i2c3: i2c@fdf0c000 { 4235f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 4245f8a3b77SZhangfei Gao reg = <0x0 0xfdf0c000 0x0 0x1000>; 4255f8a3b77SZhangfei Gao interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4265f8a3b77SZhangfei Gao #address-cells = <1>; 4275f8a3b77SZhangfei Gao #size-cells = <0>; 4285f8a3b77SZhangfei Gao clock-frequency = <400000>; 4295f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 4305f8a3b77SZhangfei Gao resets = <&crg_rst 0x78 7>; 4315f8a3b77SZhangfei Gao pinctrl-names = "default"; 4325f8a3b77SZhangfei Gao pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 4335f8a3b77SZhangfei Gao status = "disabled"; 4345f8a3b77SZhangfei Gao }; 4355f8a3b77SZhangfei Gao 4365f8a3b77SZhangfei Gao i2c7: i2c@fdf0b000 { 4375f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 4385f8a3b77SZhangfei Gao reg = <0x0 0xfdf0b000 0x0 0x1000>; 4395f8a3b77SZhangfei Gao interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 4405f8a3b77SZhangfei Gao #address-cells = <1>; 4415f8a3b77SZhangfei Gao #size-cells = <0>; 4425f8a3b77SZhangfei Gao clock-frequency = <400000>; 4435f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 4445f8a3b77SZhangfei Gao resets = <&crg_rst 0x60 14>; 4455f8a3b77SZhangfei Gao pinctrl-names = "default"; 4465f8a3b77SZhangfei Gao pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 4475f8a3b77SZhangfei Gao status = "disabled"; 4485f8a3b77SZhangfei Gao }; 4495f8a3b77SZhangfei Gao 450254b07b2SChen Feng uart0: serial@fdf02000 { 451254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 452254b07b2SChen Feng reg = <0x0 0xfdf02000 0x0 0x1000>; 453254b07b2SChen Feng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 454254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 455254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 456254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 457254b07b2SChen Feng pinctrl-names = "default"; 458254b07b2SChen Feng pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 459254b07b2SChen Feng status = "disabled"; 460254b07b2SChen Feng }; 461254b07b2SChen Feng 462254b07b2SChen Feng uart1: serial@fdf00000 { 463254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 464254b07b2SChen Feng reg = <0x0 0xfdf00000 0x0 0x1000>; 465254b07b2SChen Feng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 466254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 467254b07b2SChen Feng <&crg_ctrl HI3660_CLK_GATE_UART1>; 468254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 469254b07b2SChen Feng pinctrl-names = "default"; 470254b07b2SChen Feng pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 471254b07b2SChen Feng status = "disabled"; 472254b07b2SChen Feng }; 473254b07b2SChen Feng 474254b07b2SChen Feng uart2: serial@fdf03000 { 475254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 476254b07b2SChen Feng reg = <0x0 0xfdf03000 0x0 0x1000>; 477254b07b2SChen Feng interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 478254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 479254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 480254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 481254b07b2SChen Feng pinctrl-names = "default"; 482254b07b2SChen Feng pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 483254b07b2SChen Feng status = "disabled"; 484254b07b2SChen Feng }; 485254b07b2SChen Feng 486254b07b2SChen Feng uart3: serial@ffd74000 { 487254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 488254b07b2SChen Feng reg = <0x0 0xffd74000 0x0 0x1000>; 489254b07b2SChen Feng interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 490254b07b2SChen Feng clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 491254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 492254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 493254b07b2SChen Feng pinctrl-names = "default"; 494254b07b2SChen Feng pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 495254b07b2SChen Feng status = "disabled"; 496254b07b2SChen Feng }; 497254b07b2SChen Feng 498254b07b2SChen Feng uart4: serial@fdf01000 { 499254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 500254b07b2SChen Feng reg = <0x0 0xfdf01000 0x0 0x1000>; 501254b07b2SChen Feng interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 502254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 503254b07b2SChen Feng <&crg_ctrl HI3660_CLK_GATE_UART4>; 504254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 505254b07b2SChen Feng pinctrl-names = "default"; 506254b07b2SChen Feng pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 507254b07b2SChen Feng status = "disabled"; 508254b07b2SChen Feng }; 509254b07b2SChen Feng 510a4e36ae0SZhangfei Gao uart5: serial@fdf05000 { 51135ca8168SChen Feng compatible = "arm,pl011", "arm,primecell"; 51235ca8168SChen Feng reg = <0x0 0xfdf05000 0x0 0x1000>; 51335ca8168SChen Feng interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 514a4e36ae0SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 515a4e36ae0SZhangfei Gao <&crg_ctrl HI3660_CLK_GATE_UART5>; 51635ca8168SChen Feng clock-names = "uartclk", "apb_pclk"; 517254b07b2SChen Feng pinctrl-names = "default"; 518254b07b2SChen Feng pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 519254b07b2SChen Feng status = "disabled"; 520254b07b2SChen Feng }; 521254b07b2SChen Feng 522254b07b2SChen Feng uart6: serial@fff32000 { 523254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 524254b07b2SChen Feng reg = <0x0 0xfff32000 0x0 0x1000>; 525254b07b2SChen Feng interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 526254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_UART6>, 527254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 528254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 529254b07b2SChen Feng pinctrl-names = "default"; 530254b07b2SChen Feng pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 53135ca8168SChen Feng status = "disabled"; 53235ca8168SChen Feng }; 533d94eab86SWang Xiaoyin 5340b507e91SWang Ruyi dma0: dma@fdf30000 { 5350b507e91SWang Ruyi compatible = "hisilicon,k3-dma-1.0"; 5360b507e91SWang Ruyi reg = <0x0 0xfdf30000 0x0 0x1000>; 5370b507e91SWang Ruyi #dma-cells = <1>; 5380b507e91SWang Ruyi dma-channels = <16>; 5390b507e91SWang Ruyi dma-requests = <32>; 5400b507e91SWang Ruyi dma-min-chan = <1>; 5410b507e91SWang Ruyi interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 5420b507e91SWang Ruyi clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; 5430b507e91SWang Ruyi dma-no-cci; 5440b507e91SWang Ruyi dma-type = "hi3660_dma"; 5450b507e91SWang Ruyi }; 5460b507e91SWang Ruyi 5470a0698f6SChen Feng rtc0: rtc@fff04000 { 5480a0698f6SChen Feng compatible = "arm,pl031", "arm,primecell"; 5490a0698f6SChen Feng reg = <0x0 0Xfff04000 0x0 0x1000>; 5500a0698f6SChen Feng interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 5510a0698f6SChen Feng clocks = <&crg_ctrl HI3660_PCLK>; 5520a0698f6SChen Feng clock-names = "apb_pclk"; 5530a0698f6SChen Feng }; 5540a0698f6SChen Feng 555d94eab86SWang Xiaoyin gpio0: gpio@e8a0b000 { 556d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 557d94eab86SWang Xiaoyin reg = <0 0xe8a0b000 0 0x1000>; 558d94eab86SWang Xiaoyin interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 559d94eab86SWang Xiaoyin gpio-controller; 560d94eab86SWang Xiaoyin #gpio-cells = <2>; 561d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 0 7>; 562d94eab86SWang Xiaoyin interrupt-controller; 563d94eab86SWang Xiaoyin #interrupt-cells = <2>; 564d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 565d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 566d94eab86SWang Xiaoyin }; 567d94eab86SWang Xiaoyin 568d94eab86SWang Xiaoyin gpio1: gpio@e8a0c000 { 569d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 570d94eab86SWang Xiaoyin reg = <0 0xe8a0c000 0 0x1000>; 571d94eab86SWang Xiaoyin interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 572d94eab86SWang Xiaoyin gpio-controller; 573d94eab86SWang Xiaoyin #gpio-cells = <2>; 574d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 7 7>; 575d94eab86SWang Xiaoyin interrupt-controller; 576d94eab86SWang Xiaoyin #interrupt-cells = <2>; 577d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 578d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 579d94eab86SWang Xiaoyin }; 580d94eab86SWang Xiaoyin 581d94eab86SWang Xiaoyin gpio2: gpio@e8a0d000 { 582d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 583d94eab86SWang Xiaoyin reg = <0 0xe8a0d000 0 0x1000>; 584d94eab86SWang Xiaoyin interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 585d94eab86SWang Xiaoyin gpio-controller; 586d94eab86SWang Xiaoyin #gpio-cells = <2>; 587d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 14 8>; 588d94eab86SWang Xiaoyin interrupt-controller; 589d94eab86SWang Xiaoyin #interrupt-cells = <2>; 590d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 591d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 592d94eab86SWang Xiaoyin }; 593d94eab86SWang Xiaoyin 594d94eab86SWang Xiaoyin gpio3: gpio@e8a0e000 { 595d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 596d94eab86SWang Xiaoyin reg = <0 0xe8a0e000 0 0x1000>; 597d94eab86SWang Xiaoyin interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 598d94eab86SWang Xiaoyin gpio-controller; 599d94eab86SWang Xiaoyin #gpio-cells = <2>; 600d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 22 8>; 601d94eab86SWang Xiaoyin interrupt-controller; 602d94eab86SWang Xiaoyin #interrupt-cells = <2>; 603d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 604d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 605d94eab86SWang Xiaoyin }; 606d94eab86SWang Xiaoyin 607d94eab86SWang Xiaoyin gpio4: gpio@e8a0f000 { 608d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 609d94eab86SWang Xiaoyin reg = <0 0xe8a0f000 0 0x1000>; 610d94eab86SWang Xiaoyin interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 611d94eab86SWang Xiaoyin gpio-controller; 612d94eab86SWang Xiaoyin #gpio-cells = <2>; 613d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 30 8>; 614d94eab86SWang Xiaoyin interrupt-controller; 615d94eab86SWang Xiaoyin #interrupt-cells = <2>; 616d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 617d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 618d94eab86SWang Xiaoyin }; 619d94eab86SWang Xiaoyin 620d94eab86SWang Xiaoyin gpio5: gpio@e8a10000 { 621d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 622d94eab86SWang Xiaoyin reg = <0 0xe8a10000 0 0x1000>; 623d94eab86SWang Xiaoyin interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 624d94eab86SWang Xiaoyin gpio-controller; 625d94eab86SWang Xiaoyin #gpio-cells = <2>; 626d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 38 8>; 627d94eab86SWang Xiaoyin interrupt-controller; 628d94eab86SWang Xiaoyin #interrupt-cells = <2>; 629d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 630d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 631d94eab86SWang Xiaoyin }; 632d94eab86SWang Xiaoyin 633d94eab86SWang Xiaoyin gpio6: gpio@e8a11000 { 634d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 635d94eab86SWang Xiaoyin reg = <0 0xe8a11000 0 0x1000>; 636d94eab86SWang Xiaoyin interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 637d94eab86SWang Xiaoyin gpio-controller; 638d94eab86SWang Xiaoyin #gpio-cells = <2>; 639d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 46 8>; 640d94eab86SWang Xiaoyin interrupt-controller; 641d94eab86SWang Xiaoyin #interrupt-cells = <2>; 642d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 643d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 644d94eab86SWang Xiaoyin }; 645d94eab86SWang Xiaoyin 646d94eab86SWang Xiaoyin gpio7: gpio@e8a12000 { 647d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 648d94eab86SWang Xiaoyin reg = <0 0xe8a12000 0 0x1000>; 649d94eab86SWang Xiaoyin interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 650d94eab86SWang Xiaoyin gpio-controller; 651d94eab86SWang Xiaoyin #gpio-cells = <2>; 652d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 54 8>; 653d94eab86SWang Xiaoyin interrupt-controller; 654d94eab86SWang Xiaoyin #interrupt-cells = <2>; 655d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 656d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 657d94eab86SWang Xiaoyin }; 658d94eab86SWang Xiaoyin 659d94eab86SWang Xiaoyin gpio8: gpio@e8a13000 { 660d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 661d94eab86SWang Xiaoyin reg = <0 0xe8a13000 0 0x1000>; 662d94eab86SWang Xiaoyin interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 663d94eab86SWang Xiaoyin gpio-controller; 664d94eab86SWang Xiaoyin #gpio-cells = <2>; 665d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 62 8>; 666d94eab86SWang Xiaoyin interrupt-controller; 667d94eab86SWang Xiaoyin #interrupt-cells = <2>; 668d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 669d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 670d94eab86SWang Xiaoyin }; 671d94eab86SWang Xiaoyin 672d94eab86SWang Xiaoyin gpio9: gpio@e8a14000 { 673d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 674d94eab86SWang Xiaoyin reg = <0 0xe8a14000 0 0x1000>; 675d94eab86SWang Xiaoyin interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 676d94eab86SWang Xiaoyin gpio-controller; 677d94eab86SWang Xiaoyin #gpio-cells = <2>; 678d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 70 8>; 679d94eab86SWang Xiaoyin interrupt-controller; 680d94eab86SWang Xiaoyin #interrupt-cells = <2>; 681d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 682d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 683d94eab86SWang Xiaoyin }; 684d94eab86SWang Xiaoyin 685d94eab86SWang Xiaoyin gpio10: gpio@e8a15000 { 686d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 687d94eab86SWang Xiaoyin reg = <0 0xe8a15000 0 0x1000>; 688d94eab86SWang Xiaoyin interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 689d94eab86SWang Xiaoyin gpio-controller; 690d94eab86SWang Xiaoyin #gpio-cells = <2>; 691d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 78 8>; 692d94eab86SWang Xiaoyin interrupt-controller; 693d94eab86SWang Xiaoyin #interrupt-cells = <2>; 694d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 695d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 696d94eab86SWang Xiaoyin }; 697d94eab86SWang Xiaoyin 698d94eab86SWang Xiaoyin gpio11: gpio@e8a16000 { 699d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 700d94eab86SWang Xiaoyin reg = <0 0xe8a16000 0 0x1000>; 701d94eab86SWang Xiaoyin interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 702d94eab86SWang Xiaoyin gpio-controller; 703d94eab86SWang Xiaoyin #gpio-cells = <2>; 704d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 86 8>; 705d94eab86SWang Xiaoyin interrupt-controller; 706d94eab86SWang Xiaoyin #interrupt-cells = <2>; 707d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 708d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 709d94eab86SWang Xiaoyin }; 710d94eab86SWang Xiaoyin 711d94eab86SWang Xiaoyin gpio12: gpio@e8a17000 { 712d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 713d94eab86SWang Xiaoyin reg = <0 0xe8a17000 0 0x1000>; 714d94eab86SWang Xiaoyin interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 715d94eab86SWang Xiaoyin gpio-controller; 716d94eab86SWang Xiaoyin #gpio-cells = <2>; 717d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 718d94eab86SWang Xiaoyin interrupt-controller; 719d94eab86SWang Xiaoyin #interrupt-cells = <2>; 720d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 721d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 722d94eab86SWang Xiaoyin }; 723d94eab86SWang Xiaoyin 724d94eab86SWang Xiaoyin gpio13: gpio@e8a18000 { 725d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 726d94eab86SWang Xiaoyin reg = <0 0xe8a18000 0 0x1000>; 727d94eab86SWang Xiaoyin interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 728d94eab86SWang Xiaoyin gpio-controller; 729d94eab86SWang Xiaoyin #gpio-cells = <2>; 730d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 102 8>; 731d94eab86SWang Xiaoyin interrupt-controller; 732d94eab86SWang Xiaoyin #interrupt-cells = <2>; 733d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 734d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 735d94eab86SWang Xiaoyin }; 736d94eab86SWang Xiaoyin 737d94eab86SWang Xiaoyin gpio14: gpio@e8a19000 { 738d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 739d94eab86SWang Xiaoyin reg = <0 0xe8a19000 0 0x1000>; 740d94eab86SWang Xiaoyin interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 741d94eab86SWang Xiaoyin gpio-controller; 742d94eab86SWang Xiaoyin #gpio-cells = <2>; 743d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 110 8>; 744d94eab86SWang Xiaoyin interrupt-controller; 745d94eab86SWang Xiaoyin #interrupt-cells = <2>; 746d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 747d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 748d94eab86SWang Xiaoyin }; 749d94eab86SWang Xiaoyin 750d94eab86SWang Xiaoyin gpio15: gpio@e8a1a000 { 751d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 752d94eab86SWang Xiaoyin reg = <0 0xe8a1a000 0 0x1000>; 753d94eab86SWang Xiaoyin interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 754d94eab86SWang Xiaoyin gpio-controller; 755d94eab86SWang Xiaoyin #gpio-cells = <2>; 756d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 118 6>; 757d94eab86SWang Xiaoyin interrupt-controller; 758d94eab86SWang Xiaoyin #interrupt-cells = <2>; 759d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 760d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 761d94eab86SWang Xiaoyin }; 762d94eab86SWang Xiaoyin 763d94eab86SWang Xiaoyin gpio16: gpio@e8a1b000 { 764d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 765d94eab86SWang Xiaoyin reg = <0 0xe8a1b000 0 0x1000>; 766d94eab86SWang Xiaoyin interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 767d94eab86SWang Xiaoyin gpio-controller; 768d94eab86SWang Xiaoyin #gpio-cells = <2>; 769d94eab86SWang Xiaoyin interrupt-controller; 770d94eab86SWang Xiaoyin #interrupt-cells = <2>; 771d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 772d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 773d94eab86SWang Xiaoyin }; 774d94eab86SWang Xiaoyin 775d94eab86SWang Xiaoyin gpio17: gpio@e8a1c000 { 776d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 777d94eab86SWang Xiaoyin reg = <0 0xe8a1c000 0 0x1000>; 778d94eab86SWang Xiaoyin interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 779d94eab86SWang Xiaoyin gpio-controller; 780d94eab86SWang Xiaoyin #gpio-cells = <2>; 781d94eab86SWang Xiaoyin interrupt-controller; 782d94eab86SWang Xiaoyin #interrupt-cells = <2>; 783d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 784d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 785d94eab86SWang Xiaoyin }; 786d94eab86SWang Xiaoyin 787d94eab86SWang Xiaoyin gpio18: gpio@ff3b4000 { 788d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 789d94eab86SWang Xiaoyin reg = <0 0xff3b4000 0 0x1000>; 790d94eab86SWang Xiaoyin interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 791d94eab86SWang Xiaoyin gpio-controller; 792d94eab86SWang Xiaoyin #gpio-cells = <2>; 793d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 0 8>; 794d94eab86SWang Xiaoyin interrupt-controller; 795d94eab86SWang Xiaoyin #interrupt-cells = <2>; 796d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 797d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 798d94eab86SWang Xiaoyin }; 799d94eab86SWang Xiaoyin 800d94eab86SWang Xiaoyin gpio19: gpio@ff3b5000 { 801d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 802d94eab86SWang Xiaoyin reg = <0 0xff3b5000 0 0x1000>; 803d94eab86SWang Xiaoyin interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 804d94eab86SWang Xiaoyin gpio-controller; 805d94eab86SWang Xiaoyin #gpio-cells = <2>; 806d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 8 4>; 807d94eab86SWang Xiaoyin interrupt-controller; 808d94eab86SWang Xiaoyin #interrupt-cells = <2>; 809d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 810d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 811d94eab86SWang Xiaoyin }; 812d94eab86SWang Xiaoyin 813d94eab86SWang Xiaoyin gpio20: gpio@e8a1f000 { 814d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 815d94eab86SWang Xiaoyin reg = <0 0xe8a1f000 0 0x1000>; 816d94eab86SWang Xiaoyin interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 817d94eab86SWang Xiaoyin gpio-controller; 818d94eab86SWang Xiaoyin #gpio-cells = <2>; 819d94eab86SWang Xiaoyin gpio-ranges = <&pmx1 0 0 6>; 820d94eab86SWang Xiaoyin interrupt-controller; 821d94eab86SWang Xiaoyin #interrupt-cells = <2>; 822d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 823d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 824d94eab86SWang Xiaoyin }; 825d94eab86SWang Xiaoyin 826d94eab86SWang Xiaoyin gpio21: gpio@e8a20000 { 827d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 828d94eab86SWang Xiaoyin reg = <0 0xe8a20000 0 0x1000>; 829d94eab86SWang Xiaoyin interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 830d94eab86SWang Xiaoyin gpio-controller; 831d94eab86SWang Xiaoyin #gpio-cells = <2>; 832d94eab86SWang Xiaoyin interrupt-controller; 833d94eab86SWang Xiaoyin #interrupt-cells = <2>; 834d94eab86SWang Xiaoyin gpio-ranges = <&pmx3 0 0 6>; 835d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 836d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 837d94eab86SWang Xiaoyin }; 838d94eab86SWang Xiaoyin 839d94eab86SWang Xiaoyin gpio22: gpio@fff0b000 { 840d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 841d94eab86SWang Xiaoyin reg = <0 0xfff0b000 0 0x1000>; 842d94eab86SWang Xiaoyin interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 843d94eab86SWang Xiaoyin gpio-controller; 844d94eab86SWang Xiaoyin #gpio-cells = <2>; 845d94eab86SWang Xiaoyin /* GPIO176 */ 846d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 2 0 6>; 847d94eab86SWang Xiaoyin interrupt-controller; 848d94eab86SWang Xiaoyin #interrupt-cells = <2>; 849d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 850d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 851d94eab86SWang Xiaoyin }; 852d94eab86SWang Xiaoyin 853d94eab86SWang Xiaoyin gpio23: gpio@fff0c000 { 854d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 855d94eab86SWang Xiaoyin reg = <0 0xfff0c000 0 0x1000>; 856d94eab86SWang Xiaoyin interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 857d94eab86SWang Xiaoyin gpio-controller; 858d94eab86SWang Xiaoyin #gpio-cells = <2>; 859d94eab86SWang Xiaoyin /* GPIO184 */ 860d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 6 7>; 861d94eab86SWang Xiaoyin interrupt-controller; 862d94eab86SWang Xiaoyin #interrupt-cells = <2>; 863d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 864d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 865d94eab86SWang Xiaoyin }; 866d94eab86SWang Xiaoyin 867d94eab86SWang Xiaoyin gpio24: gpio@fff0d000 { 868d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 869d94eab86SWang Xiaoyin reg = <0 0xfff0d000 0 0x1000>; 870d94eab86SWang Xiaoyin interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 871d94eab86SWang Xiaoyin gpio-controller; 872d94eab86SWang Xiaoyin #gpio-cells = <2>; 873d94eab86SWang Xiaoyin /* GPIO192 */ 874d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 13 8>; 875d94eab86SWang Xiaoyin interrupt-controller; 876d94eab86SWang Xiaoyin #interrupt-cells = <2>; 877d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 878d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 879d94eab86SWang Xiaoyin }; 880d94eab86SWang Xiaoyin 881d94eab86SWang Xiaoyin gpio25: gpio@fff0e000 { 882d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 883d94eab86SWang Xiaoyin reg = <0 0xfff0e000 0 0x1000>; 884d94eab86SWang Xiaoyin interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 885d94eab86SWang Xiaoyin gpio-controller; 886d94eab86SWang Xiaoyin #gpio-cells = <2>; 887d94eab86SWang Xiaoyin /* GPIO200 */ 888d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 889d94eab86SWang Xiaoyin interrupt-controller; 890d94eab86SWang Xiaoyin #interrupt-cells = <2>; 891d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 892d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 893d94eab86SWang Xiaoyin }; 894d94eab86SWang Xiaoyin 895d94eab86SWang Xiaoyin gpio26: gpio@fff0f000 { 896d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 897d94eab86SWang Xiaoyin reg = <0 0xfff0f000 0 0x1000>; 898d94eab86SWang Xiaoyin interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 899d94eab86SWang Xiaoyin gpio-controller; 900d94eab86SWang Xiaoyin #gpio-cells = <2>; 901d94eab86SWang Xiaoyin /* GPIO208 */ 902d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 28 8>; 903d94eab86SWang Xiaoyin interrupt-controller; 904d94eab86SWang Xiaoyin #interrupt-cells = <2>; 905d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 906d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 907d94eab86SWang Xiaoyin }; 908d94eab86SWang Xiaoyin 909d94eab86SWang Xiaoyin gpio27: gpio@fff10000 { 910d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 911d94eab86SWang Xiaoyin reg = <0 0xfff10000 0 0x1000>; 912d94eab86SWang Xiaoyin interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 913d94eab86SWang Xiaoyin gpio-controller; 914d94eab86SWang Xiaoyin #gpio-cells = <2>; 915d94eab86SWang Xiaoyin /* GPIO216 */ 916d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 36 6>; 917d94eab86SWang Xiaoyin interrupt-controller; 918d94eab86SWang Xiaoyin #interrupt-cells = <2>; 919d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 920d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 921d94eab86SWang Xiaoyin }; 922d94eab86SWang Xiaoyin 923d94eab86SWang Xiaoyin gpio28: gpio@fff1d000 { 924d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 925d94eab86SWang Xiaoyin reg = <0 0xfff1d000 0 0x1000>; 926d94eab86SWang Xiaoyin interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 927d94eab86SWang Xiaoyin gpio-controller; 928d94eab86SWang Xiaoyin #gpio-cells = <2>; 929d94eab86SWang Xiaoyin interrupt-controller; 930d94eab86SWang Xiaoyin #interrupt-cells = <2>; 931d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 932d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 933d94eab86SWang Xiaoyin }; 93438810497SWang Xiaoyin 93538810497SWang Xiaoyin spi2: spi@ffd68000 { 93638810497SWang Xiaoyin compatible = "arm,pl022", "arm,primecell"; 93738810497SWang Xiaoyin reg = <0x0 0xffd68000 0x0 0x1000>; 93838810497SWang Xiaoyin #address-cells = <1>; 93938810497SWang Xiaoyin #size-cells = <0>; 94038810497SWang Xiaoyin interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 94138810497SWang Xiaoyin clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; 94238810497SWang Xiaoyin clock-names = "apb_pclk"; 94338810497SWang Xiaoyin pinctrl-names = "default"; 94438810497SWang Xiaoyin pinctrl-0 = <&spi2_pmx_func>; 94538810497SWang Xiaoyin num-cs = <1>; 94638810497SWang Xiaoyin cs-gpios = <&gpio27 2 0>; 94738810497SWang Xiaoyin status = "disabled"; 94838810497SWang Xiaoyin }; 94938810497SWang Xiaoyin 95038810497SWang Xiaoyin spi3: spi@ff3b3000 { 95138810497SWang Xiaoyin compatible = "arm,pl022", "arm,primecell"; 95238810497SWang Xiaoyin reg = <0x0 0xff3b3000 0x0 0x1000>; 95338810497SWang Xiaoyin #address-cells = <1>; 95438810497SWang Xiaoyin #size-cells = <0>; 95538810497SWang Xiaoyin interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 95638810497SWang Xiaoyin clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; 95738810497SWang Xiaoyin clock-names = "apb_pclk"; 95838810497SWang Xiaoyin pinctrl-names = "default"; 95938810497SWang Xiaoyin pinctrl-0 = <&spi3_pmx_func>; 96038810497SWang Xiaoyin num-cs = <1>; 96138810497SWang Xiaoyin cs-gpios = <&gpio18 5 0>; 96238810497SWang Xiaoyin status = "disabled"; 96338810497SWang Xiaoyin }; 96496909778SXiaowei Song 96596909778SXiaowei Song pcie@f4000000 { 96696909778SXiaowei Song compatible = "hisilicon,kirin960-pcie"; 96796909778SXiaowei Song reg = <0x0 0xf4000000 0x0 0x1000>, 96896909778SXiaowei Song <0x0 0xff3fe000 0x0 0x1000>, 96996909778SXiaowei Song <0x0 0xf3f20000 0x0 0x40000>, 97096909778SXiaowei Song <0x0 0xf5000000 0x0 0x2000>; 97196909778SXiaowei Song reg-names = "dbi", "apb", "phy", "config"; 97296909778SXiaowei Song bus-range = <0x0 0x1>; 97396909778SXiaowei Song #address-cells = <3>; 97496909778SXiaowei Song #size-cells = <2>; 97596909778SXiaowei Song device_type = "pci"; 97696909778SXiaowei Song ranges = <0x02000000 0x0 0x00000000 97796909778SXiaowei Song 0x0 0xf6000000 97896909778SXiaowei Song 0x0 0x02000000>; 97996909778SXiaowei Song num-lanes = <1>; 98096909778SXiaowei Song #interrupt-cells = <1>; 9812bff3594SYao Chen interrupts = <0 283 4>; 9822bff3594SYao Chen interrupt-names = "msi"; 98396909778SXiaowei Song interrupt-map-mask = <0xf800 0 0 7>; 98496909778SXiaowei Song interrupt-map = <0x0 0 0 1 98596909778SXiaowei Song &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 98696909778SXiaowei Song <0x0 0 0 2 98796909778SXiaowei Song &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 98896909778SXiaowei Song <0x0 0 0 3 98996909778SXiaowei Song &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 99096909778SXiaowei Song <0x0 0 0 4 99196909778SXiaowei Song &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 99296909778SXiaowei Song clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 99396909778SXiaowei Song <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 99496909778SXiaowei Song <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 99596909778SXiaowei Song <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 99696909778SXiaowei Song <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 99796909778SXiaowei Song clock-names = "pcie_phy_ref", "pcie_aux", 99896909778SXiaowei Song "pcie_apb_phy", "pcie_apb_sys", 99996909778SXiaowei Song "pcie_aclk"; 100096909778SXiaowei Song reset-gpios = <&gpio11 1 0 >; 100196909778SXiaowei Song }; 1002804d7d7aSLi Wei 1003804d7d7aSLi Wei /* SD */ 1004804d7d7aSLi Wei dwmmc1: dwmmc1@ff37f000 { 1005804d7d7aSLi Wei #address-cells = <1>; 1006804d7d7aSLi Wei #size-cells = <0>; 1007804d7d7aSLi Wei cd-inverted; 1008804d7d7aSLi Wei compatible = "hisilicon,hi3660-dw-mshc"; 1009804d7d7aSLi Wei bus-width = <0x4>; 1010804d7d7aSLi Wei disable-wp; 1011804d7d7aSLi Wei cap-sd-highspeed; 1012804d7d7aSLi Wei supports-highspeed; 1013804d7d7aSLi Wei card-detect-delay = <200>; 1014804d7d7aSLi Wei reg = <0x0 0xff37f000 0x0 0x1000>; 1015804d7d7aSLi Wei interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1016804d7d7aSLi Wei clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, 1017804d7d7aSLi Wei <&crg_ctrl HI3660_HCLK_GATE_SD>; 1018804d7d7aSLi Wei clock-names = "ciu", "biu"; 1019804d7d7aSLi Wei clock-frequency = <3200000>; 1020804d7d7aSLi Wei resets = <&crg_rst 0x94 18>; 1021996707d7SGuodong Xu reset-names = "reset"; 1022804d7d7aSLi Wei cd-gpios = <&gpio25 3 0>; 1023804d7d7aSLi Wei hisilicon,peripheral-syscon = <&sctrl>; 1024804d7d7aSLi Wei pinctrl-names = "default"; 1025804d7d7aSLi Wei pinctrl-0 = <&sd_pmx_func 1026804d7d7aSLi Wei &sd_clk_cfg_func 1027804d7d7aSLi Wei &sd_cfg_func>; 1028804d7d7aSLi Wei sd-uhs-sdr12; 1029804d7d7aSLi Wei sd-uhs-sdr25; 1030804d7d7aSLi Wei sd-uhs-sdr50; 1031804d7d7aSLi Wei sd-uhs-sdr104; 1032804d7d7aSLi Wei status = "disabled"; 1033804d7d7aSLi Wei 1034804d7d7aSLi Wei slot@0 { 1035804d7d7aSLi Wei reg = <0x0>; 1036804d7d7aSLi Wei bus-width = <4>; 1037804d7d7aSLi Wei disable-wp; 1038804d7d7aSLi Wei }; 1039804d7d7aSLi Wei }; 1040804d7d7aSLi Wei 1041804d7d7aSLi Wei /* SDIO */ 1042804d7d7aSLi Wei dwmmc2: dwmmc2@ff3ff000 { 1043804d7d7aSLi Wei compatible = "hisilicon,hi3660-dw-mshc"; 1044804d7d7aSLi Wei reg = <0x0 0xff3ff000 0x0 0x1000>; 1045804d7d7aSLi Wei interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1046804d7d7aSLi Wei clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, 1047804d7d7aSLi Wei <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; 1048804d7d7aSLi Wei clock-names = "ciu", "biu"; 1049804d7d7aSLi Wei resets = <&crg_rst 0x94 20>; 1050996707d7SGuodong Xu reset-names = "reset"; 1051804d7d7aSLi Wei card-detect-delay = <200>; 1052804d7d7aSLi Wei supports-highspeed; 1053804d7d7aSLi Wei keep-power-in-suspend; 1054804d7d7aSLi Wei pinctrl-names = "default"; 1055804d7d7aSLi Wei pinctrl-0 = <&sdio_pmx_func 1056804d7d7aSLi Wei &sdio_clk_cfg_func 1057804d7d7aSLi Wei &sdio_cfg_func>; 1058804d7d7aSLi Wei status = "disabled"; 1059804d7d7aSLi Wei }; 1060487f00d4SLeo Yan 1061487f00d4SLeo Yan watchdog0: watchdog@e8a06000 { 1062487f00d4SLeo Yan compatible = "arm,sp805-wdt", "arm,primecell"; 1063487f00d4SLeo Yan reg = <0x0 0xe8a06000 0x0 0x1000>; 1064487f00d4SLeo Yan interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1065487f00d4SLeo Yan clocks = <&crg_ctrl HI3660_OSC32K>; 1066487f00d4SLeo Yan clock-names = "apb_pclk"; 1067487f00d4SLeo Yan }; 1068487f00d4SLeo Yan 1069487f00d4SLeo Yan watchdog1: watchdog@e8a07000 { 1070487f00d4SLeo Yan compatible = "arm,sp805-wdt", "arm,primecell"; 1071487f00d4SLeo Yan reg = <0x0 0xe8a07000 0x0 0x1000>; 1072487f00d4SLeo Yan interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1073487f00d4SLeo Yan clocks = <&crg_ctrl HI3660_OSC32K>; 1074487f00d4SLeo Yan clock-names = "apb_pclk"; 1075487f00d4SLeo Yan }; 1076a7ab4cb4SKevin Wangtao 1077a7ab4cb4SKevin Wangtao tsensor: tsensor@fff30000 { 1078a7ab4cb4SKevin Wangtao compatible = "hisilicon,hi3660-tsensor"; 1079a7ab4cb4SKevin Wangtao reg = <0x0 0xfff30000 0x0 0x1000>; 1080a7ab4cb4SKevin Wangtao interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 1081a7ab4cb4SKevin Wangtao #thermal-sensor-cells = <1>; 1082a7ab4cb4SKevin Wangtao }; 10838d93e94bSTao Wang 10848d93e94bSTao Wang thermal-zones { 10858d93e94bSTao Wang 10868d93e94bSTao Wang cls0: cls0 { 10878d93e94bSTao Wang polling-delay = <1000>; 10888d93e94bSTao Wang polling-delay-passive = <100>; 10898d93e94bSTao Wang sustainable-power = <4500>; 10908d93e94bSTao Wang 10918d93e94bSTao Wang /* sensor ID */ 10928d93e94bSTao Wang thermal-sensors = <&tsensor 1>; 10938d93e94bSTao Wang 10948d93e94bSTao Wang trips { 10958d93e94bSTao Wang threshold: trip-point@0 { 10968d93e94bSTao Wang temperature = <65000>; 10978d93e94bSTao Wang hysteresis = <1000>; 10988d93e94bSTao Wang type = "passive"; 10998d93e94bSTao Wang }; 11008d93e94bSTao Wang 11018d93e94bSTao Wang target: trip-point@1 { 11028d93e94bSTao Wang temperature = <75000>; 11038d93e94bSTao Wang hysteresis = <1000>; 11048d93e94bSTao Wang type = "passive"; 11058d93e94bSTao Wang }; 11068d93e94bSTao Wang }; 11078d93e94bSTao Wang 11088d93e94bSTao Wang cooling-maps { 11098d93e94bSTao Wang map0 { 11108d93e94bSTao Wang trip = <&target>; 11118d93e94bSTao Wang contribution = <1024>; 11128d93e94bSTao Wang cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 11138d93e94bSTao Wang }; 11148d93e94bSTao Wang map1 { 11158d93e94bSTao Wang trip = <&target>; 11168d93e94bSTao Wang contribution = <512>; 11178d93e94bSTao Wang cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 11188d93e94bSTao Wang }; 11198d93e94bSTao Wang }; 11208d93e94bSTao Wang }; 11218d93e94bSTao Wang }; 112235ca8168SChen Feng }; 112335ca8168SChen Feng}; 1124