1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 235ca8168SChen Feng/* 335ca8168SChen Feng * dts file for Hisilicon Hi3660 SoC 435ca8168SChen Feng * 5e3211e41SHao Fang * Copyright (C) 2016, HiSilicon Ltd. 635ca8168SChen Feng */ 735ca8168SChen Feng 835ca8168SChen Feng#include <dt-bindings/interrupt-controller/arm-gic.h> 9a4e36ae0SZhangfei Gao#include <dt-bindings/clock/hi3660-clock.h> 108d93e94bSTao Wang#include <dt-bindings/thermal/thermal.h> 1135ca8168SChen Feng 1235ca8168SChen Feng/ { 1335ca8168SChen Feng compatible = "hisilicon,hi3660"; 1435ca8168SChen Feng interrupt-parent = <&gic>; 1535ca8168SChen Feng #address-cells = <2>; 1635ca8168SChen Feng #size-cells = <2>; 1735ca8168SChen Feng 1835ca8168SChen Feng psci { 1935ca8168SChen Feng compatible = "arm,psci-0.2"; 2035ca8168SChen Feng method = "smc"; 2135ca8168SChen Feng }; 2235ca8168SChen Feng 2335ca8168SChen Feng cpus { 2435ca8168SChen Feng #address-cells = <2>; 2535ca8168SChen Feng #size-cells = <0>; 2635ca8168SChen Feng 2735ca8168SChen Feng cpu-map { 2835ca8168SChen Feng cluster0 { 2935ca8168SChen Feng core0 { 3035ca8168SChen Feng cpu = <&cpu0>; 3135ca8168SChen Feng }; 3235ca8168SChen Feng core1 { 3335ca8168SChen Feng cpu = <&cpu1>; 3435ca8168SChen Feng }; 3535ca8168SChen Feng core2 { 3635ca8168SChen Feng cpu = <&cpu2>; 3735ca8168SChen Feng }; 3835ca8168SChen Feng core3 { 3935ca8168SChen Feng cpu = <&cpu3>; 4035ca8168SChen Feng }; 4135ca8168SChen Feng }; 4235ca8168SChen Feng cluster1 { 4335ca8168SChen Feng core0 { 4435ca8168SChen Feng cpu = <&cpu4>; 4535ca8168SChen Feng }; 4635ca8168SChen Feng core1 { 4735ca8168SChen Feng cpu = <&cpu5>; 4835ca8168SChen Feng }; 4935ca8168SChen Feng core2 { 5035ca8168SChen Feng cpu = <&cpu6>; 5135ca8168SChen Feng }; 5235ca8168SChen Feng core3 { 5335ca8168SChen Feng cpu = <&cpu7>; 5435ca8168SChen Feng }; 5535ca8168SChen Feng }; 5635ca8168SChen Feng }; 5735ca8168SChen Feng 5835ca8168SChen Feng cpu0: cpu@0 { 5931af04cdSRob Herring compatible = "arm,cortex-a53"; 6035ca8168SChen Feng device_type = "cpu"; 6135ca8168SChen Feng reg = <0x0 0x0>; 6235ca8168SChen Feng enable-method = "psci"; 63a6d08344SLeo Yan next-level-cache = <&A53_L2>; 64a5956defSVincent Guittot cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 659a9760deSValentin Schneider capacity-dmips-mhz = <592>; 66dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 67dfeae9e5SLeo Yan operating-points-v2 = <&cluster0_opp>; 688d93e94bSTao Wang #cooling-cells = <2>; 698d93e94bSTao Wang dynamic-power-coefficient = <110>; 7035ca8168SChen Feng }; 7135ca8168SChen Feng 7235ca8168SChen Feng cpu1: cpu@1 { 7331af04cdSRob Herring compatible = "arm,cortex-a53"; 7435ca8168SChen Feng device_type = "cpu"; 7535ca8168SChen Feng reg = <0x0 0x1>; 7635ca8168SChen Feng enable-method = "psci"; 77a6d08344SLeo Yan next-level-cache = <&A53_L2>; 78a5956defSVincent Guittot cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 799a9760deSValentin Schneider capacity-dmips-mhz = <592>; 80dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 81dfeae9e5SLeo Yan operating-points-v2 = <&cluster0_opp>; 82a7a6e2cbSViresh Kumar #cooling-cells = <2>; 8335ca8168SChen Feng }; 8435ca8168SChen Feng 8535ca8168SChen Feng cpu2: cpu@2 { 8631af04cdSRob Herring compatible = "arm,cortex-a53"; 8735ca8168SChen Feng device_type = "cpu"; 8835ca8168SChen Feng reg = <0x0 0x2>; 8935ca8168SChen Feng enable-method = "psci"; 90a6d08344SLeo Yan next-level-cache = <&A53_L2>; 91a5956defSVincent Guittot cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 929a9760deSValentin Schneider capacity-dmips-mhz = <592>; 93dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 94dfeae9e5SLeo Yan operating-points-v2 = <&cluster0_opp>; 95a7a6e2cbSViresh Kumar #cooling-cells = <2>; 9635ca8168SChen Feng }; 9735ca8168SChen Feng 9835ca8168SChen Feng cpu3: cpu@3 { 9931af04cdSRob Herring compatible = "arm,cortex-a53"; 10035ca8168SChen Feng device_type = "cpu"; 10135ca8168SChen Feng reg = <0x0 0x3>; 10235ca8168SChen Feng enable-method = "psci"; 103a6d08344SLeo Yan next-level-cache = <&A53_L2>; 104a5956defSVincent Guittot cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 1059a9760deSValentin Schneider capacity-dmips-mhz = <592>; 106dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 107dfeae9e5SLeo Yan operating-points-v2 = <&cluster0_opp>; 108a7a6e2cbSViresh Kumar #cooling-cells = <2>; 10935ca8168SChen Feng }; 11035ca8168SChen Feng 11135ca8168SChen Feng cpu4: cpu@100 { 11231af04cdSRob Herring compatible = "arm,cortex-a73"; 11335ca8168SChen Feng device_type = "cpu"; 11435ca8168SChen Feng reg = <0x0 0x100>; 11535ca8168SChen Feng enable-method = "psci"; 116a6d08344SLeo Yan next-level-cache = <&A73_L2>; 117a5956defSVincent Guittot cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; 1189a9760deSValentin Schneider capacity-dmips-mhz = <1024>; 119dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 120dfeae9e5SLeo Yan operating-points-v2 = <&cluster1_opp>; 1218d93e94bSTao Wang #cooling-cells = <2>; 1228d93e94bSTao Wang dynamic-power-coefficient = <550>; 12335ca8168SChen Feng }; 12435ca8168SChen Feng 12535ca8168SChen Feng cpu5: cpu@101 { 12631af04cdSRob Herring compatible = "arm,cortex-a73"; 12735ca8168SChen Feng device_type = "cpu"; 12835ca8168SChen Feng reg = <0x0 0x101>; 12935ca8168SChen Feng enable-method = "psci"; 130a6d08344SLeo Yan next-level-cache = <&A73_L2>; 131a5956defSVincent Guittot cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; 1329a9760deSValentin Schneider capacity-dmips-mhz = <1024>; 133dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 134dfeae9e5SLeo Yan operating-points-v2 = <&cluster1_opp>; 135a7a6e2cbSViresh Kumar #cooling-cells = <2>; 13635ca8168SChen Feng }; 13735ca8168SChen Feng 13835ca8168SChen Feng cpu6: cpu@102 { 13931af04cdSRob Herring compatible = "arm,cortex-a73"; 14035ca8168SChen Feng device_type = "cpu"; 14135ca8168SChen Feng reg = <0x0 0x102>; 14235ca8168SChen Feng enable-method = "psci"; 143a6d08344SLeo Yan next-level-cache = <&A73_L2>; 144a5956defSVincent Guittot cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; 1459a9760deSValentin Schneider capacity-dmips-mhz = <1024>; 146dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 147dfeae9e5SLeo Yan operating-points-v2 = <&cluster1_opp>; 148a7a6e2cbSViresh Kumar #cooling-cells = <2>; 14935ca8168SChen Feng }; 15035ca8168SChen Feng 15135ca8168SChen Feng cpu7: cpu@103 { 15231af04cdSRob Herring compatible = "arm,cortex-a73"; 15335ca8168SChen Feng device_type = "cpu"; 15435ca8168SChen Feng reg = <0x0 0x103>; 15535ca8168SChen Feng enable-method = "psci"; 156a6d08344SLeo Yan next-level-cache = <&A73_L2>; 157a5956defSVincent Guittot cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; 1589a9760deSValentin Schneider capacity-dmips-mhz = <1024>; 159dfeae9e5SLeo Yan clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 160dfeae9e5SLeo Yan operating-points-v2 = <&cluster1_opp>; 161a7a6e2cbSViresh Kumar #cooling-cells = <2>; 16230fec826SLeo Yan }; 16330fec826SLeo Yan 16430fec826SLeo Yan idle-states { 16530fec826SLeo Yan entry-method = "psci"; 16630fec826SLeo Yan 167a5956defSVincent Guittot CPU_SLEEP_0: cpu-sleep-0 { 16830fec826SLeo Yan compatible = "arm,idle-state"; 16930fec826SLeo Yan local-timer-stop; 17030fec826SLeo Yan arm,psci-suspend-param = <0x0010000>; 171a5956defSVincent Guittot entry-latency-us = <400>; 172a5956defSVincent Guittot exit-latency-us = <650>; 173a5956defSVincent Guittot min-residency-us = <1500>; 17430fec826SLeo Yan }; 17530fec826SLeo Yan CLUSTER_SLEEP_0: cluster-sleep-0 { 17630fec826SLeo Yan compatible = "arm,idle-state"; 17730fec826SLeo Yan local-timer-stop; 17830fec826SLeo Yan arm,psci-suspend-param = <0x1010000>; 17930fec826SLeo Yan entry-latency-us = <500>; 180a5956defSVincent Guittot exit-latency-us = <1600>; 181a5956defSVincent Guittot min-residency-us = <3500>; 182a5956defSVincent Guittot }; 183a5956defSVincent Guittot 184a5956defSVincent Guittot 185a5956defSVincent Guittot CPU_SLEEP_1: cpu-sleep-1 { 186a5956defSVincent Guittot compatible = "arm,idle-state"; 187a5956defSVincent Guittot local-timer-stop; 188a5956defSVincent Guittot arm,psci-suspend-param = <0x0010000>; 189a5956defSVincent Guittot entry-latency-us = <400>; 190a5956defSVincent Guittot exit-latency-us = <550>; 191a5956defSVincent Guittot min-residency-us = <1500>; 19230fec826SLeo Yan }; 19330fec826SLeo Yan 19430fec826SLeo Yan CLUSTER_SLEEP_1: cluster-sleep-1 { 19530fec826SLeo Yan compatible = "arm,idle-state"; 19630fec826SLeo Yan local-timer-stop; 19730fec826SLeo Yan arm,psci-suspend-param = <0x1010000>; 198a5956defSVincent Guittot entry-latency-us = <800>; 199a5956defSVincent Guittot exit-latency-us = <2900>; 200a5956defSVincent Guittot min-residency-us = <3500>; 20130fec826SLeo Yan }; 20235ca8168SChen Feng }; 203a6d08344SLeo Yan 204a6d08344SLeo Yan A53_L2: l2-cache0 { 205a6d08344SLeo Yan compatible = "cache"; 206*0de459a3SPierre Gondois cache-level = <2>; 207a6d08344SLeo Yan }; 208a6d08344SLeo Yan 209a6d08344SLeo Yan A73_L2: l2-cache1 { 210a6d08344SLeo Yan compatible = "cache"; 211*0de459a3SPierre Gondois cache-level = <2>; 212a6d08344SLeo Yan }; 21335ca8168SChen Feng }; 21435ca8168SChen Feng 215dcc3f565SKrzysztof Kozlowski cluster0_opp: opp-table-0 { 216dfeae9e5SLeo Yan compatible = "operating-points-v2"; 217dfeae9e5SLeo Yan opp-shared; 218dfeae9e5SLeo Yan 219dfeae9e5SLeo Yan opp00 { 220dfeae9e5SLeo Yan opp-hz = /bits/ 64 <533000000>; 221dfeae9e5SLeo Yan opp-microvolt = <700000>; 222dfeae9e5SLeo Yan clock-latency-ns = <300000>; 223dfeae9e5SLeo Yan }; 224dfeae9e5SLeo Yan 225dfeae9e5SLeo Yan opp01 { 226dfeae9e5SLeo Yan opp-hz = /bits/ 64 <999000000>; 227dfeae9e5SLeo Yan opp-microvolt = <800000>; 228dfeae9e5SLeo Yan clock-latency-ns = <300000>; 229dfeae9e5SLeo Yan }; 230dfeae9e5SLeo Yan 231dfeae9e5SLeo Yan opp02 { 232dfeae9e5SLeo Yan opp-hz = /bits/ 64 <1402000000>; 233dfeae9e5SLeo Yan opp-microvolt = <900000>; 234dfeae9e5SLeo Yan clock-latency-ns = <300000>; 235dfeae9e5SLeo Yan }; 236dfeae9e5SLeo Yan 237dfeae9e5SLeo Yan opp03 { 238dfeae9e5SLeo Yan opp-hz = /bits/ 64 <1709000000>; 239dfeae9e5SLeo Yan opp-microvolt = <1000000>; 240dfeae9e5SLeo Yan clock-latency-ns = <300000>; 241dfeae9e5SLeo Yan }; 242dfeae9e5SLeo Yan 243dfeae9e5SLeo Yan opp04 { 244dfeae9e5SLeo Yan opp-hz = /bits/ 64 <1844000000>; 245dfeae9e5SLeo Yan opp-microvolt = <1100000>; 246dfeae9e5SLeo Yan clock-latency-ns = <300000>; 247dfeae9e5SLeo Yan }; 248dfeae9e5SLeo Yan }; 249dfeae9e5SLeo Yan 250dcc3f565SKrzysztof Kozlowski cluster1_opp: opp-table-1 { 251dfeae9e5SLeo Yan compatible = "operating-points-v2"; 252dfeae9e5SLeo Yan opp-shared; 253dfeae9e5SLeo Yan 254dfeae9e5SLeo Yan opp10 { 255dfeae9e5SLeo Yan opp-hz = /bits/ 64 <903000000>; 256dfeae9e5SLeo Yan opp-microvolt = <700000>; 257dfeae9e5SLeo Yan clock-latency-ns = <300000>; 258dfeae9e5SLeo Yan }; 259dfeae9e5SLeo Yan 260dfeae9e5SLeo Yan opp11 { 261dfeae9e5SLeo Yan opp-hz = /bits/ 64 <1421000000>; 262dfeae9e5SLeo Yan opp-microvolt = <800000>; 263dfeae9e5SLeo Yan clock-latency-ns = <300000>; 264dfeae9e5SLeo Yan }; 265dfeae9e5SLeo Yan 266dfeae9e5SLeo Yan opp12 { 267dfeae9e5SLeo Yan opp-hz = /bits/ 64 <1805000000>; 268dfeae9e5SLeo Yan opp-microvolt = <900000>; 269dfeae9e5SLeo Yan clock-latency-ns = <300000>; 270dfeae9e5SLeo Yan }; 271dfeae9e5SLeo Yan 272dfeae9e5SLeo Yan opp13 { 273dfeae9e5SLeo Yan opp-hz = /bits/ 64 <2112000000>; 274dfeae9e5SLeo Yan opp-microvolt = <1000000>; 275dfeae9e5SLeo Yan clock-latency-ns = <300000>; 276dfeae9e5SLeo Yan }; 277dfeae9e5SLeo Yan 278dfeae9e5SLeo Yan opp14 { 279dfeae9e5SLeo Yan opp-hz = /bits/ 64 <2362000000>; 280dfeae9e5SLeo Yan opp-microvolt = <1100000>; 281dfeae9e5SLeo Yan clock-latency-ns = <300000>; 282dfeae9e5SLeo Yan }; 283dfeae9e5SLeo Yan }; 284dfeae9e5SLeo Yan 28535ca8168SChen Feng gic: interrupt-controller@e82b0000 { 28635ca8168SChen Feng compatible = "arm,gic-400"; 28735ca8168SChen Feng reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 28835ca8168SChen Feng <0x0 0xe82b2000 0 0x2000>, /* GICC */ 28935ca8168SChen Feng <0x0 0xe82b4000 0 0x2000>, /* GICH */ 29035ca8168SChen Feng <0x0 0xe82b6000 0 0x2000>; /* GICV */ 29135ca8168SChen Feng #address-cells = <0>; 29235ca8168SChen Feng #interrupt-cells = <3>; 29335ca8168SChen Feng interrupt-controller; 29435ca8168SChen Feng interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 29535ca8168SChen Feng IRQ_TYPE_LEVEL_HIGH)>; 29635ca8168SChen Feng }; 29735ca8168SChen Feng 298e07642faSXu YiPing a53-pmu { 299e07642faSXu YiPing compatible = "arm,cortex-a53-pmu"; 300f8054fb8SYiPing Xu interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 301f8054fb8SYiPing Xu <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 302f8054fb8SYiPing Xu <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 303e07642faSXu YiPing <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 304f8054fb8SYiPing Xu interrupt-affinity = <&cpu0>, 305f8054fb8SYiPing Xu <&cpu1>, 306f8054fb8SYiPing Xu <&cpu2>, 307e07642faSXu YiPing <&cpu3>; 308e07642faSXu YiPing }; 309e07642faSXu YiPing 310e07642faSXu YiPing a73-pmu { 311e07642faSXu YiPing compatible = "arm,cortex-a73-pmu"; 312e07642faSXu YiPing interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 313e07642faSXu YiPing <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 314e07642faSXu YiPing <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 315e07642faSXu YiPing <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 316e07642faSXu YiPing interrupt-affinity = <&cpu4>, 317f8054fb8SYiPing Xu <&cpu5>, 318f8054fb8SYiPing Xu <&cpu6>, 319f8054fb8SYiPing Xu <&cpu7>; 320f8054fb8SYiPing Xu }; 321f8054fb8SYiPing Xu 32235ca8168SChen Feng timer { 32335ca8168SChen Feng compatible = "arm,armv8-timer"; 32435ca8168SChen Feng interrupt-parent = <&gic>; 32535ca8168SChen Feng interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 32635ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 32735ca8168SChen Feng <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 32835ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 32935ca8168SChen Feng <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 33035ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>, 33135ca8168SChen Feng <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 33235ca8168SChen Feng IRQ_TYPE_LEVEL_LOW)>; 33335ca8168SChen Feng }; 33435ca8168SChen Feng 33535ca8168SChen Feng soc { 33635ca8168SChen Feng compatible = "simple-bus"; 33735ca8168SChen Feng #address-cells = <2>; 33835ca8168SChen Feng #size-cells = <2>; 33935ca8168SChen Feng ranges; 34035ca8168SChen Feng 341a4e36ae0SZhangfei Gao crg_ctrl: crg_ctrl@fff35000 { 342a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-crgctrl", "syscon"; 343a4e36ae0SZhangfei Gao reg = <0x0 0xfff35000 0x0 0x1000>; 344a4e36ae0SZhangfei Gao #clock-cells = <1>; 34535ca8168SChen Feng }; 34635ca8168SChen Feng 347a4e36ae0SZhangfei Gao crg_rst: crg_rst_controller { 348a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 349a4e36ae0SZhangfei Gao #reset-cells = <2>; 350a4e36ae0SZhangfei Gao hisi,rst-syscon = <&crg_ctrl>; 351a4e36ae0SZhangfei Gao }; 352a4e36ae0SZhangfei Gao 353a4e36ae0SZhangfei Gao 354a4e36ae0SZhangfei Gao pctrl: pctrl@e8a09000 { 355a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pctrl", "syscon"; 356a4e36ae0SZhangfei Gao reg = <0x0 0xe8a09000 0x0 0x2000>; 357a4e36ae0SZhangfei Gao #clock-cells = <1>; 358a4e36ae0SZhangfei Gao }; 359a4e36ae0SZhangfei Gao 360a4e36ae0SZhangfei Gao pmuctrl: crg_ctrl@fff34000 { 361a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 362a4e36ae0SZhangfei Gao reg = <0x0 0xfff34000 0x0 0x1000>; 363a4e36ae0SZhangfei Gao #clock-cells = <1>; 364a4e36ae0SZhangfei Gao }; 365a4e36ae0SZhangfei Gao 366a4e36ae0SZhangfei Gao sctrl: sctrl@fff0a000 { 367a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-sctrl", "syscon"; 368a4e36ae0SZhangfei Gao reg = <0x0 0xfff0a000 0x0 0x1000>; 369a4e36ae0SZhangfei Gao #clock-cells = <1>; 370a4e36ae0SZhangfei Gao }; 371a4e36ae0SZhangfei Gao 372a4e36ae0SZhangfei Gao iomcu: iomcu@ffd7e000 { 373a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-iomcu", "syscon"; 374a4e36ae0SZhangfei Gao reg = <0x0 0xffd7e000 0x0 0x1000>; 375a4e36ae0SZhangfei Gao #clock-cells = <1>; 376a4e36ae0SZhangfei Gao 377a4e36ae0SZhangfei Gao }; 378a4e36ae0SZhangfei Gao 379a4e36ae0SZhangfei Gao iomcu_rst: reset { 380a4e36ae0SZhangfei Gao compatible = "hisilicon,hi3660-reset"; 381a4e36ae0SZhangfei Gao hisi,rst-syscon = <&iomcu>; 382a4e36ae0SZhangfei Gao #reset-cells = <2>; 383a4e36ae0SZhangfei Gao }; 384a4e36ae0SZhangfei Gao 385ca905780SKaihua Zhong mailbox: mailbox@e896b000 { 386ca905780SKaihua Zhong compatible = "hisilicon,hi3660-mbox"; 387ca905780SKaihua Zhong reg = <0x0 0xe896b000 0x0 0x1000>; 388ca905780SKaihua Zhong interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 389ca905780SKaihua Zhong <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 390ca905780SKaihua Zhong #mbox-cells = <3>; 391ca905780SKaihua Zhong }; 392ca905780SKaihua Zhong 3936e2c52b3SKaihua Zhong stub_clock: stub_clock@e896b500 { 3946e2c52b3SKaihua Zhong compatible = "hisilicon,hi3660-stub-clk"; 3956e2c52b3SKaihua Zhong reg = <0x0 0xe896b500 0x0 0x0100>; 3966e2c52b3SKaihua Zhong #clock-cells = <1>; 3976e2c52b3SKaihua Zhong mboxes = <&mailbox 13 3 0>; 3986e2c52b3SKaihua Zhong }; 3996e2c52b3SKaihua Zhong 40075196330SLeo Yan dual_timer0: timer@fff14000 { 40175196330SLeo Yan compatible = "arm,sp804", "arm,primecell"; 40275196330SLeo Yan reg = <0x0 0xfff14000 0x0 0x1000>; 40375196330SLeo Yan interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 40475196330SLeo Yan <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 40575196330SLeo Yan clocks = <&crg_ctrl HI3660_OSC32K>, 40675196330SLeo Yan <&crg_ctrl HI3660_OSC32K>, 40775196330SLeo Yan <&crg_ctrl HI3660_OSC32K>; 40875196330SLeo Yan clock-names = "timer1", "timer2", "apb_pclk"; 40975196330SLeo Yan }; 41075196330SLeo Yan 4115f8a3b77SZhangfei Gao i2c0: i2c@ffd71000 { 4125f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 4135f8a3b77SZhangfei Gao reg = <0x0 0xffd71000 0x0 0x1000>; 4145f8a3b77SZhangfei Gao interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 4155f8a3b77SZhangfei Gao #address-cells = <1>; 4165f8a3b77SZhangfei Gao #size-cells = <0>; 4175f8a3b77SZhangfei Gao clock-frequency = <400000>; 4185f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 4195f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 3>; 4205f8a3b77SZhangfei Gao pinctrl-names = "default"; 4215f8a3b77SZhangfei Gao pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 4225f8a3b77SZhangfei Gao status = "disabled"; 4235f8a3b77SZhangfei Gao }; 4245f8a3b77SZhangfei Gao 4255f8a3b77SZhangfei Gao i2c1: i2c@ffd72000 { 4265f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 4275f8a3b77SZhangfei Gao reg = <0x0 0xffd72000 0x0 0x1000>; 4285f8a3b77SZhangfei Gao interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 4295f8a3b77SZhangfei Gao #address-cells = <1>; 4305f8a3b77SZhangfei Gao #size-cells = <0>; 4315f8a3b77SZhangfei Gao clock-frequency = <400000>; 4325f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 4335f8a3b77SZhangfei Gao resets = <&iomcu_rst 0x20 4>; 4345f8a3b77SZhangfei Gao pinctrl-names = "default"; 4355f8a3b77SZhangfei Gao pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 4365f8a3b77SZhangfei Gao status = "disabled"; 4375f8a3b77SZhangfei Gao }; 4385f8a3b77SZhangfei Gao 4395f8a3b77SZhangfei Gao i2c3: i2c@fdf0c000 { 4405f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 4415f8a3b77SZhangfei Gao reg = <0x0 0xfdf0c000 0x0 0x1000>; 4425f8a3b77SZhangfei Gao interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4435f8a3b77SZhangfei Gao #address-cells = <1>; 4445f8a3b77SZhangfei Gao #size-cells = <0>; 4455f8a3b77SZhangfei Gao clock-frequency = <400000>; 4465f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 4475f8a3b77SZhangfei Gao resets = <&crg_rst 0x78 7>; 4485f8a3b77SZhangfei Gao pinctrl-names = "default"; 4495f8a3b77SZhangfei Gao pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 4505f8a3b77SZhangfei Gao status = "disabled"; 4515f8a3b77SZhangfei Gao }; 4525f8a3b77SZhangfei Gao 4535f8a3b77SZhangfei Gao i2c7: i2c@fdf0b000 { 4545f8a3b77SZhangfei Gao compatible = "snps,designware-i2c"; 4555f8a3b77SZhangfei Gao reg = <0x0 0xfdf0b000 0x0 0x1000>; 4565f8a3b77SZhangfei Gao interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 4575f8a3b77SZhangfei Gao #address-cells = <1>; 4585f8a3b77SZhangfei Gao #size-cells = <0>; 4595f8a3b77SZhangfei Gao clock-frequency = <400000>; 4605f8a3b77SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 4615f8a3b77SZhangfei Gao resets = <&crg_rst 0x60 14>; 4625f8a3b77SZhangfei Gao pinctrl-names = "default"; 4635f8a3b77SZhangfei Gao pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 4645f8a3b77SZhangfei Gao status = "disabled"; 4655f8a3b77SZhangfei Gao }; 4665f8a3b77SZhangfei Gao 467254b07b2SChen Feng uart0: serial@fdf02000 { 468254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 469254b07b2SChen Feng reg = <0x0 0xfdf02000 0x0 0x1000>; 470254b07b2SChen Feng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 471254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 472254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 473254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 474254b07b2SChen Feng pinctrl-names = "default"; 475254b07b2SChen Feng pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 476254b07b2SChen Feng status = "disabled"; 477254b07b2SChen Feng }; 478254b07b2SChen Feng 479254b07b2SChen Feng uart1: serial@fdf00000 { 480254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 481254b07b2SChen Feng reg = <0x0 0xfdf00000 0x0 0x1000>; 482254b07b2SChen Feng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 483792cea3fSJohn Stultz dma-names = "rx", "tx"; 484792cea3fSJohn Stultz dmas = <&dma0 2 &dma0 3>; 485254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 486254b07b2SChen Feng <&crg_ctrl HI3660_CLK_GATE_UART1>; 487254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 488254b07b2SChen Feng pinctrl-names = "default"; 489254b07b2SChen Feng pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 490254b07b2SChen Feng status = "disabled"; 491254b07b2SChen Feng }; 492254b07b2SChen Feng 493254b07b2SChen Feng uart2: serial@fdf03000 { 494254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 495254b07b2SChen Feng reg = <0x0 0xfdf03000 0x0 0x1000>; 496254b07b2SChen Feng interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 497792cea3fSJohn Stultz dma-names = "rx", "tx"; 498792cea3fSJohn Stultz dmas = <&dma0 4 &dma0 5>; 499254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 500254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 501254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 502254b07b2SChen Feng pinctrl-names = "default"; 503254b07b2SChen Feng pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 504254b07b2SChen Feng status = "disabled"; 505254b07b2SChen Feng }; 506254b07b2SChen Feng 507254b07b2SChen Feng uart3: serial@ffd74000 { 508254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 509254b07b2SChen Feng reg = <0x0 0xffd74000 0x0 0x1000>; 510254b07b2SChen Feng interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 511254b07b2SChen Feng clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 512254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 513254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 514254b07b2SChen Feng pinctrl-names = "default"; 515254b07b2SChen Feng pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 516254b07b2SChen Feng status = "disabled"; 517254b07b2SChen Feng }; 518254b07b2SChen Feng 519254b07b2SChen Feng uart4: serial@fdf01000 { 520254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 521254b07b2SChen Feng reg = <0x0 0xfdf01000 0x0 0x1000>; 522254b07b2SChen Feng interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 523792cea3fSJohn Stultz dma-names = "rx", "tx"; 524792cea3fSJohn Stultz dmas = <&dma0 6 &dma0 7>; 525254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 526254b07b2SChen Feng <&crg_ctrl HI3660_CLK_GATE_UART4>; 527254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 528254b07b2SChen Feng pinctrl-names = "default"; 529254b07b2SChen Feng pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 530254b07b2SChen Feng status = "disabled"; 531254b07b2SChen Feng }; 532254b07b2SChen Feng 533a4e36ae0SZhangfei Gao uart5: serial@fdf05000 { 53435ca8168SChen Feng compatible = "arm,pl011", "arm,primecell"; 53535ca8168SChen Feng reg = <0x0 0xfdf05000 0x0 0x1000>; 53635ca8168SChen Feng interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 537792cea3fSJohn Stultz dma-names = "rx", "tx"; 538792cea3fSJohn Stultz dmas = <&dma0 8 &dma0 9>; 539a4e36ae0SZhangfei Gao clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 540a4e36ae0SZhangfei Gao <&crg_ctrl HI3660_CLK_GATE_UART5>; 54135ca8168SChen Feng clock-names = "uartclk", "apb_pclk"; 542254b07b2SChen Feng pinctrl-names = "default"; 543254b07b2SChen Feng pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 544254b07b2SChen Feng status = "disabled"; 545254b07b2SChen Feng }; 546254b07b2SChen Feng 547254b07b2SChen Feng uart6: serial@fff32000 { 548254b07b2SChen Feng compatible = "arm,pl011", "arm,primecell"; 549254b07b2SChen Feng reg = <0x0 0xfff32000 0x0 0x1000>; 550254b07b2SChen Feng interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 551254b07b2SChen Feng clocks = <&crg_ctrl HI3660_CLK_UART6>, 552254b07b2SChen Feng <&crg_ctrl HI3660_PCLK>; 553254b07b2SChen Feng clock-names = "uartclk", "apb_pclk"; 554254b07b2SChen Feng pinctrl-names = "default"; 555254b07b2SChen Feng pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 55635ca8168SChen Feng status = "disabled"; 55735ca8168SChen Feng }; 558d94eab86SWang Xiaoyin 5590b507e91SWang Ruyi dma0: dma@fdf30000 { 5600b507e91SWang Ruyi compatible = "hisilicon,k3-dma-1.0"; 5610b507e91SWang Ruyi reg = <0x0 0xfdf30000 0x0 0x1000>; 5620b507e91SWang Ruyi #dma-cells = <1>; 5630b507e91SWang Ruyi dma-channels = <16>; 5640b507e91SWang Ruyi dma-requests = <32>; 5656d09e003SJohn Stultz dma-channel-mask = <0xfffe>; 5660b507e91SWang Ruyi interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 5670b507e91SWang Ruyi clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; 5680b507e91SWang Ruyi dma-no-cci; 5690b507e91SWang Ruyi dma-type = "hi3660_dma"; 5700b507e91SWang Ruyi }; 5710b507e91SWang Ruyi 572c9726326SYoulin Wang asp_dmac: dma-controller@e804b000 { 573c9726326SYoulin Wang compatible = "hisilicon,hisi-pcm-asp-dma-1.0"; 574c9726326SYoulin Wang reg = <0x0 0xe804b000 0x0 0x1000>; 575c9726326SYoulin Wang #dma-cells = <1>; 576c9726326SYoulin Wang dma-channels = <16>; 577c9726326SYoulin Wang dma-requests = <32>; 578c9726326SYoulin Wang interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 579c9726326SYoulin Wang interrupt-names = "asp_dma_irq"; 580c9726326SYoulin Wang }; 581c9726326SYoulin Wang 5820a0698f6SChen Feng rtc0: rtc@fff04000 { 5830a0698f6SChen Feng compatible = "arm,pl031", "arm,primecell"; 5840a0698f6SChen Feng reg = <0x0 0Xfff04000 0x0 0x1000>; 5850a0698f6SChen Feng interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 5860a0698f6SChen Feng clocks = <&crg_ctrl HI3660_PCLK>; 5870a0698f6SChen Feng clock-names = "apb_pclk"; 5880a0698f6SChen Feng }; 5890a0698f6SChen Feng 590d94eab86SWang Xiaoyin gpio0: gpio@e8a0b000 { 591d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 592d94eab86SWang Xiaoyin reg = <0 0xe8a0b000 0 0x1000>; 593d94eab86SWang Xiaoyin interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 594d94eab86SWang Xiaoyin gpio-controller; 595d94eab86SWang Xiaoyin #gpio-cells = <2>; 596d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 0 7>; 597d94eab86SWang Xiaoyin interrupt-controller; 598d94eab86SWang Xiaoyin #interrupt-cells = <2>; 599d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 600d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 601d94eab86SWang Xiaoyin }; 602d94eab86SWang Xiaoyin 603d94eab86SWang Xiaoyin gpio1: gpio@e8a0c000 { 604d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 605d94eab86SWang Xiaoyin reg = <0 0xe8a0c000 0 0x1000>; 606d94eab86SWang Xiaoyin interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 607d94eab86SWang Xiaoyin gpio-controller; 608d94eab86SWang Xiaoyin #gpio-cells = <2>; 609d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 1 7 7>; 610d94eab86SWang Xiaoyin interrupt-controller; 611d94eab86SWang Xiaoyin #interrupt-cells = <2>; 612d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 613d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 614d94eab86SWang Xiaoyin }; 615d94eab86SWang Xiaoyin 616d94eab86SWang Xiaoyin gpio2: gpio@e8a0d000 { 617d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 618d94eab86SWang Xiaoyin reg = <0 0xe8a0d000 0 0x1000>; 619d94eab86SWang Xiaoyin interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 620d94eab86SWang Xiaoyin gpio-controller; 621d94eab86SWang Xiaoyin #gpio-cells = <2>; 622d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 14 8>; 623d94eab86SWang Xiaoyin interrupt-controller; 624d94eab86SWang Xiaoyin #interrupt-cells = <2>; 625d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 626d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 627d94eab86SWang Xiaoyin }; 628d94eab86SWang Xiaoyin 629d94eab86SWang Xiaoyin gpio3: gpio@e8a0e000 { 630d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 631d94eab86SWang Xiaoyin reg = <0 0xe8a0e000 0 0x1000>; 632d94eab86SWang Xiaoyin interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 633d94eab86SWang Xiaoyin gpio-controller; 634d94eab86SWang Xiaoyin #gpio-cells = <2>; 635d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 22 8>; 636d94eab86SWang Xiaoyin interrupt-controller; 637d94eab86SWang Xiaoyin #interrupt-cells = <2>; 638d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 639d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 640d94eab86SWang Xiaoyin }; 641d94eab86SWang Xiaoyin 642d94eab86SWang Xiaoyin gpio4: gpio@e8a0f000 { 643d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 644d94eab86SWang Xiaoyin reg = <0 0xe8a0f000 0 0x1000>; 645d94eab86SWang Xiaoyin interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 646d94eab86SWang Xiaoyin gpio-controller; 647d94eab86SWang Xiaoyin #gpio-cells = <2>; 648d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 30 8>; 649d94eab86SWang Xiaoyin interrupt-controller; 650d94eab86SWang Xiaoyin #interrupt-cells = <2>; 651d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 652d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 653d94eab86SWang Xiaoyin }; 654d94eab86SWang Xiaoyin 655d94eab86SWang Xiaoyin gpio5: gpio@e8a10000 { 656d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 657d94eab86SWang Xiaoyin reg = <0 0xe8a10000 0 0x1000>; 658d94eab86SWang Xiaoyin interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 659d94eab86SWang Xiaoyin gpio-controller; 660d94eab86SWang Xiaoyin #gpio-cells = <2>; 661d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 38 8>; 662d94eab86SWang Xiaoyin interrupt-controller; 663d94eab86SWang Xiaoyin #interrupt-cells = <2>; 664d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 665d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 666d94eab86SWang Xiaoyin }; 667d94eab86SWang Xiaoyin 668d94eab86SWang Xiaoyin gpio6: gpio@e8a11000 { 669d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 670d94eab86SWang Xiaoyin reg = <0 0xe8a11000 0 0x1000>; 671d94eab86SWang Xiaoyin interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 672d94eab86SWang Xiaoyin gpio-controller; 673d94eab86SWang Xiaoyin #gpio-cells = <2>; 674d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 46 8>; 675d94eab86SWang Xiaoyin interrupt-controller; 676d94eab86SWang Xiaoyin #interrupt-cells = <2>; 677d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 678d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 679d94eab86SWang Xiaoyin }; 680d94eab86SWang Xiaoyin 681d94eab86SWang Xiaoyin gpio7: gpio@e8a12000 { 682d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 683d94eab86SWang Xiaoyin reg = <0 0xe8a12000 0 0x1000>; 684d94eab86SWang Xiaoyin interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 685d94eab86SWang Xiaoyin gpio-controller; 686d94eab86SWang Xiaoyin #gpio-cells = <2>; 687d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 54 8>; 688d94eab86SWang Xiaoyin interrupt-controller; 689d94eab86SWang Xiaoyin #interrupt-cells = <2>; 690d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 691d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 692d94eab86SWang Xiaoyin }; 693d94eab86SWang Xiaoyin 694d94eab86SWang Xiaoyin gpio8: gpio@e8a13000 { 695d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 696d94eab86SWang Xiaoyin reg = <0 0xe8a13000 0 0x1000>; 697d94eab86SWang Xiaoyin interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 698d94eab86SWang Xiaoyin gpio-controller; 699d94eab86SWang Xiaoyin #gpio-cells = <2>; 700d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 62 8>; 701d94eab86SWang Xiaoyin interrupt-controller; 702d94eab86SWang Xiaoyin #interrupt-cells = <2>; 703d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 704d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 705d94eab86SWang Xiaoyin }; 706d94eab86SWang Xiaoyin 707d94eab86SWang Xiaoyin gpio9: gpio@e8a14000 { 708d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 709d94eab86SWang Xiaoyin reg = <0 0xe8a14000 0 0x1000>; 710d94eab86SWang Xiaoyin interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 711d94eab86SWang Xiaoyin gpio-controller; 712d94eab86SWang Xiaoyin #gpio-cells = <2>; 713d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 70 8>; 714d94eab86SWang Xiaoyin interrupt-controller; 715d94eab86SWang Xiaoyin #interrupt-cells = <2>; 716d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 717d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 718d94eab86SWang Xiaoyin }; 719d94eab86SWang Xiaoyin 720d94eab86SWang Xiaoyin gpio10: gpio@e8a15000 { 721d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 722d94eab86SWang Xiaoyin reg = <0 0xe8a15000 0 0x1000>; 723d94eab86SWang Xiaoyin interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 724d94eab86SWang Xiaoyin gpio-controller; 725d94eab86SWang Xiaoyin #gpio-cells = <2>; 726d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 78 8>; 727d94eab86SWang Xiaoyin interrupt-controller; 728d94eab86SWang Xiaoyin #interrupt-cells = <2>; 729d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 730d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 731d94eab86SWang Xiaoyin }; 732d94eab86SWang Xiaoyin 733d94eab86SWang Xiaoyin gpio11: gpio@e8a16000 { 734d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 735d94eab86SWang Xiaoyin reg = <0 0xe8a16000 0 0x1000>; 736d94eab86SWang Xiaoyin interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 737d94eab86SWang Xiaoyin gpio-controller; 738d94eab86SWang Xiaoyin #gpio-cells = <2>; 739d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 86 8>; 740d94eab86SWang Xiaoyin interrupt-controller; 741d94eab86SWang Xiaoyin #interrupt-cells = <2>; 742d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 743d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 744d94eab86SWang Xiaoyin }; 745d94eab86SWang Xiaoyin 746d94eab86SWang Xiaoyin gpio12: gpio@e8a17000 { 747d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 748d94eab86SWang Xiaoyin reg = <0 0xe8a17000 0 0x1000>; 749d94eab86SWang Xiaoyin interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 750d94eab86SWang Xiaoyin gpio-controller; 751d94eab86SWang Xiaoyin #gpio-cells = <2>; 752d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 753d94eab86SWang Xiaoyin interrupt-controller; 754d94eab86SWang Xiaoyin #interrupt-cells = <2>; 755d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 756d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 757d94eab86SWang Xiaoyin }; 758d94eab86SWang Xiaoyin 759d94eab86SWang Xiaoyin gpio13: gpio@e8a18000 { 760d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 761d94eab86SWang Xiaoyin reg = <0 0xe8a18000 0 0x1000>; 762d94eab86SWang Xiaoyin interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 763d94eab86SWang Xiaoyin gpio-controller; 764d94eab86SWang Xiaoyin #gpio-cells = <2>; 765d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 102 8>; 766d94eab86SWang Xiaoyin interrupt-controller; 767d94eab86SWang Xiaoyin #interrupt-cells = <2>; 768d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 769d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 770d94eab86SWang Xiaoyin }; 771d94eab86SWang Xiaoyin 772d94eab86SWang Xiaoyin gpio14: gpio@e8a19000 { 773d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 774d94eab86SWang Xiaoyin reg = <0 0xe8a19000 0 0x1000>; 775d94eab86SWang Xiaoyin interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 776d94eab86SWang Xiaoyin gpio-controller; 777d94eab86SWang Xiaoyin #gpio-cells = <2>; 778d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 110 8>; 779d94eab86SWang Xiaoyin interrupt-controller; 780d94eab86SWang Xiaoyin #interrupt-cells = <2>; 781d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 782d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 783d94eab86SWang Xiaoyin }; 784d94eab86SWang Xiaoyin 785d94eab86SWang Xiaoyin gpio15: gpio@e8a1a000 { 786d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 787d94eab86SWang Xiaoyin reg = <0 0xe8a1a000 0 0x1000>; 788d94eab86SWang Xiaoyin interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 789d94eab86SWang Xiaoyin gpio-controller; 790d94eab86SWang Xiaoyin #gpio-cells = <2>; 791d94eab86SWang Xiaoyin gpio-ranges = <&pmx0 0 118 6>; 792d94eab86SWang Xiaoyin interrupt-controller; 793d94eab86SWang Xiaoyin #interrupt-cells = <2>; 794d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 795d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 796d94eab86SWang Xiaoyin }; 797d94eab86SWang Xiaoyin 798d94eab86SWang Xiaoyin gpio16: gpio@e8a1b000 { 799d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 800d94eab86SWang Xiaoyin reg = <0 0xe8a1b000 0 0x1000>; 801d94eab86SWang Xiaoyin interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 802d94eab86SWang Xiaoyin gpio-controller; 803d94eab86SWang Xiaoyin #gpio-cells = <2>; 804d94eab86SWang Xiaoyin interrupt-controller; 805d94eab86SWang Xiaoyin #interrupt-cells = <2>; 806d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 807d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 808d94eab86SWang Xiaoyin }; 809d94eab86SWang Xiaoyin 810d94eab86SWang Xiaoyin gpio17: gpio@e8a1c000 { 811d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 812d94eab86SWang Xiaoyin reg = <0 0xe8a1c000 0 0x1000>; 813d94eab86SWang Xiaoyin interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 814d94eab86SWang Xiaoyin gpio-controller; 815d94eab86SWang Xiaoyin #gpio-cells = <2>; 816d94eab86SWang Xiaoyin interrupt-controller; 817d94eab86SWang Xiaoyin #interrupt-cells = <2>; 818d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 819d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 820d94eab86SWang Xiaoyin }; 821d94eab86SWang Xiaoyin 822d94eab86SWang Xiaoyin gpio18: gpio@ff3b4000 { 823d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 824d94eab86SWang Xiaoyin reg = <0 0xff3b4000 0 0x1000>; 825d94eab86SWang Xiaoyin interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 826d94eab86SWang Xiaoyin gpio-controller; 827d94eab86SWang Xiaoyin #gpio-cells = <2>; 828d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 0 8>; 829d94eab86SWang Xiaoyin interrupt-controller; 830d94eab86SWang Xiaoyin #interrupt-cells = <2>; 831d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 832d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 833d94eab86SWang Xiaoyin }; 834d94eab86SWang Xiaoyin 835d94eab86SWang Xiaoyin gpio19: gpio@ff3b5000 { 836d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 837d94eab86SWang Xiaoyin reg = <0 0xff3b5000 0 0x1000>; 838d94eab86SWang Xiaoyin interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 839d94eab86SWang Xiaoyin gpio-controller; 840d94eab86SWang Xiaoyin #gpio-cells = <2>; 841d94eab86SWang Xiaoyin gpio-ranges = <&pmx2 0 8 4>; 842d94eab86SWang Xiaoyin interrupt-controller; 843d94eab86SWang Xiaoyin #interrupt-cells = <2>; 844d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 845d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 846d94eab86SWang Xiaoyin }; 847d94eab86SWang Xiaoyin 848d94eab86SWang Xiaoyin gpio20: gpio@e8a1f000 { 849d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 850d94eab86SWang Xiaoyin reg = <0 0xe8a1f000 0 0x1000>; 851d94eab86SWang Xiaoyin interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 852d94eab86SWang Xiaoyin gpio-controller; 853d94eab86SWang Xiaoyin #gpio-cells = <2>; 854d94eab86SWang Xiaoyin gpio-ranges = <&pmx1 0 0 6>; 855d94eab86SWang Xiaoyin interrupt-controller; 856d94eab86SWang Xiaoyin #interrupt-cells = <2>; 857d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 858d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 859d94eab86SWang Xiaoyin }; 860d94eab86SWang Xiaoyin 861d94eab86SWang Xiaoyin gpio21: gpio@e8a20000 { 862d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 863d94eab86SWang Xiaoyin reg = <0 0xe8a20000 0 0x1000>; 864d94eab86SWang Xiaoyin interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 865d94eab86SWang Xiaoyin gpio-controller; 866d94eab86SWang Xiaoyin #gpio-cells = <2>; 867d94eab86SWang Xiaoyin interrupt-controller; 868d94eab86SWang Xiaoyin #interrupt-cells = <2>; 869d94eab86SWang Xiaoyin gpio-ranges = <&pmx3 0 0 6>; 870d94eab86SWang Xiaoyin clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 871d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 872d94eab86SWang Xiaoyin }; 873d94eab86SWang Xiaoyin 874d94eab86SWang Xiaoyin gpio22: gpio@fff0b000 { 875d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 876d94eab86SWang Xiaoyin reg = <0 0xfff0b000 0 0x1000>; 877d94eab86SWang Xiaoyin interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 878d94eab86SWang Xiaoyin gpio-controller; 879d94eab86SWang Xiaoyin #gpio-cells = <2>; 880d94eab86SWang Xiaoyin /* GPIO176 */ 881d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 2 0 6>; 882d94eab86SWang Xiaoyin interrupt-controller; 883d94eab86SWang Xiaoyin #interrupt-cells = <2>; 884d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 885d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 886d94eab86SWang Xiaoyin }; 887d94eab86SWang Xiaoyin 888d94eab86SWang Xiaoyin gpio23: gpio@fff0c000 { 889d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 890d94eab86SWang Xiaoyin reg = <0 0xfff0c000 0 0x1000>; 891d94eab86SWang Xiaoyin interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 892d94eab86SWang Xiaoyin gpio-controller; 893d94eab86SWang Xiaoyin #gpio-cells = <2>; 894d94eab86SWang Xiaoyin /* GPIO184 */ 895d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 6 7>; 896d94eab86SWang Xiaoyin interrupt-controller; 897d94eab86SWang Xiaoyin #interrupt-cells = <2>; 898d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 899d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 900d94eab86SWang Xiaoyin }; 901d94eab86SWang Xiaoyin 902d94eab86SWang Xiaoyin gpio24: gpio@fff0d000 { 903d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 904d94eab86SWang Xiaoyin reg = <0 0xfff0d000 0 0x1000>; 905d94eab86SWang Xiaoyin interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 906d94eab86SWang Xiaoyin gpio-controller; 907d94eab86SWang Xiaoyin #gpio-cells = <2>; 908d94eab86SWang Xiaoyin /* GPIO192 */ 909d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 13 8>; 910d94eab86SWang Xiaoyin interrupt-controller; 911d94eab86SWang Xiaoyin #interrupt-cells = <2>; 912d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 913d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 914d94eab86SWang Xiaoyin }; 915d94eab86SWang Xiaoyin 916d94eab86SWang Xiaoyin gpio25: gpio@fff0e000 { 917d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 918d94eab86SWang Xiaoyin reg = <0 0xfff0e000 0 0x1000>; 919d94eab86SWang Xiaoyin interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 920d94eab86SWang Xiaoyin gpio-controller; 921d94eab86SWang Xiaoyin #gpio-cells = <2>; 922d94eab86SWang Xiaoyin /* GPIO200 */ 923d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 924d94eab86SWang Xiaoyin interrupt-controller; 925d94eab86SWang Xiaoyin #interrupt-cells = <2>; 926d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 927d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 928d94eab86SWang Xiaoyin }; 929d94eab86SWang Xiaoyin 930d94eab86SWang Xiaoyin gpio26: gpio@fff0f000 { 931d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 932d94eab86SWang Xiaoyin reg = <0 0xfff0f000 0 0x1000>; 933d94eab86SWang Xiaoyin interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 934d94eab86SWang Xiaoyin gpio-controller; 935d94eab86SWang Xiaoyin #gpio-cells = <2>; 936d94eab86SWang Xiaoyin /* GPIO208 */ 937d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 28 8>; 938d94eab86SWang Xiaoyin interrupt-controller; 939d94eab86SWang Xiaoyin #interrupt-cells = <2>; 940d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 941d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 942d94eab86SWang Xiaoyin }; 943d94eab86SWang Xiaoyin 944d94eab86SWang Xiaoyin gpio27: gpio@fff10000 { 945d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 946d94eab86SWang Xiaoyin reg = <0 0xfff10000 0 0x1000>; 947d94eab86SWang Xiaoyin interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 948d94eab86SWang Xiaoyin gpio-controller; 949d94eab86SWang Xiaoyin #gpio-cells = <2>; 950d94eab86SWang Xiaoyin /* GPIO216 */ 951d94eab86SWang Xiaoyin gpio-ranges = <&pmx4 0 36 6>; 952d94eab86SWang Xiaoyin interrupt-controller; 953d94eab86SWang Xiaoyin #interrupt-cells = <2>; 954d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 955d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 956d94eab86SWang Xiaoyin }; 957d94eab86SWang Xiaoyin 958d94eab86SWang Xiaoyin gpio28: gpio@fff1d000 { 959d94eab86SWang Xiaoyin compatible = "arm,pl061", "arm,primecell"; 960d94eab86SWang Xiaoyin reg = <0 0xfff1d000 0 0x1000>; 961d94eab86SWang Xiaoyin interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 962d94eab86SWang Xiaoyin gpio-controller; 963d94eab86SWang Xiaoyin #gpio-cells = <2>; 964d94eab86SWang Xiaoyin interrupt-controller; 965d94eab86SWang Xiaoyin #interrupt-cells = <2>; 966d94eab86SWang Xiaoyin clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 967d94eab86SWang Xiaoyin clock-names = "apb_pclk"; 968d94eab86SWang Xiaoyin }; 96938810497SWang Xiaoyin 97038810497SWang Xiaoyin spi2: spi@ffd68000 { 97138810497SWang Xiaoyin compatible = "arm,pl022", "arm,primecell"; 97238810497SWang Xiaoyin reg = <0x0 0xffd68000 0x0 0x1000>; 97338810497SWang Xiaoyin #address-cells = <1>; 97438810497SWang Xiaoyin #size-cells = <0>; 97538810497SWang Xiaoyin interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 976c85731abSZhen Lei clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>, <&crg_ctrl HI3660_CLK_GATE_SPI2>; 977c85731abSZhen Lei clock-names = "sspclk", "apb_pclk"; 97838810497SWang Xiaoyin pinctrl-names = "default"; 979a8dad3e1SLoic Poulain pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>; 98038810497SWang Xiaoyin num-cs = <1>; 98138810497SWang Xiaoyin cs-gpios = <&gpio27 2 0>; 98238810497SWang Xiaoyin status = "disabled"; 98338810497SWang Xiaoyin }; 98438810497SWang Xiaoyin 98538810497SWang Xiaoyin spi3: spi@ff3b3000 { 98638810497SWang Xiaoyin compatible = "arm,pl022", "arm,primecell"; 98738810497SWang Xiaoyin reg = <0x0 0xff3b3000 0x0 0x1000>; 98838810497SWang Xiaoyin #address-cells = <1>; 98938810497SWang Xiaoyin #size-cells = <0>; 99038810497SWang Xiaoyin interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 991c85731abSZhen Lei clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>, <&crg_ctrl HI3660_CLK_GATE_SPI3>; 992c85731abSZhen Lei clock-names = "sspclk", "apb_pclk"; 99338810497SWang Xiaoyin pinctrl-names = "default"; 994a8dad3e1SLoic Poulain pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>; 99538810497SWang Xiaoyin num-cs = <1>; 99638810497SWang Xiaoyin cs-gpios = <&gpio18 5 0>; 99738810497SWang Xiaoyin status = "disabled"; 99838810497SWang Xiaoyin }; 99996909778SXiaowei Song 100096909778SXiaowei Song pcie@f4000000 { 100196909778SXiaowei Song compatible = "hisilicon,kirin960-pcie"; 100296909778SXiaowei Song reg = <0x0 0xf4000000 0x0 0x1000>, 100396909778SXiaowei Song <0x0 0xff3fe000 0x0 0x1000>, 100496909778SXiaowei Song <0x0 0xf3f20000 0x0 0x40000>, 100596909778SXiaowei Song <0x0 0xf5000000 0x0 0x2000>; 100696909778SXiaowei Song reg-names = "dbi", "apb", "phy", "config"; 10072dc30eb9SMauro Carvalho Chehab bus-range = <0x0 0xff>; 100896909778SXiaowei Song #address-cells = <3>; 100996909778SXiaowei Song #size-cells = <2>; 101096909778SXiaowei Song device_type = "pci"; 101196909778SXiaowei Song ranges = <0x02000000 0x0 0x00000000 101296909778SXiaowei Song 0x0 0xf6000000 101396909778SXiaowei Song 0x0 0x02000000>; 101496909778SXiaowei Song num-lanes = <1>; 101596909778SXiaowei Song #interrupt-cells = <1>; 10162bff3594SYao Chen interrupts = <0 283 4>; 10172bff3594SYao Chen interrupt-names = "msi"; 101896909778SXiaowei Song interrupt-map-mask = <0xf800 0 0 7>; 101996909778SXiaowei Song interrupt-map = <0x0 0 0 1 102096909778SXiaowei Song &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 102196909778SXiaowei Song <0x0 0 0 2 102296909778SXiaowei Song &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 102396909778SXiaowei Song <0x0 0 0 3 102496909778SXiaowei Song &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 102596909778SXiaowei Song <0x0 0 0 4 102696909778SXiaowei Song &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 102796909778SXiaowei Song clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 102896909778SXiaowei Song <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 102996909778SXiaowei Song <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 103096909778SXiaowei Song <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 103196909778SXiaowei Song <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 103296909778SXiaowei Song clock-names = "pcie_phy_ref", "pcie_aux", 103396909778SXiaowei Song "pcie_apb_phy", "pcie_apb_sys", 103496909778SXiaowei Song "pcie_aclk"; 103596909778SXiaowei Song reset-gpios = <&gpio11 1 0 >; 103696909778SXiaowei Song }; 1037804d7d7aSLi Wei 1038360249d2Sliwei /* UFS */ 1039360249d2Sliwei ufs: ufs@ff3b0000 { 1040360249d2Sliwei compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; 1041360249d2Sliwei /* 0: HCI standard */ 1042360249d2Sliwei /* 1: UFS SYS CTRL */ 1043360249d2Sliwei reg = <0x0 0xff3b0000 0x0 0x1000>, 1044360249d2Sliwei <0x0 0xff3b1000 0x0 0x1000>; 1045360249d2Sliwei interrupt-parent = <&gic>; 1046360249d2Sliwei interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 1047360249d2Sliwei clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, 1048360249d2Sliwei <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; 1049360249d2Sliwei clock-names = "ref_clk", "phy_clk"; 105065b96377SKrzysztof Kozlowski freq-table-hz = <0 0>, 105165b96377SKrzysztof Kozlowski <0 0>; 1052360249d2Sliwei /* offset: 0x84; bit: 12 */ 1053360249d2Sliwei resets = <&crg_rst 0x84 12>; 1054360249d2Sliwei reset-names = "rst"; 1055360249d2Sliwei }; 1056360249d2Sliwei 1057804d7d7aSLi Wei /* SD */ 1058804d7d7aSLi Wei dwmmc1: dwmmc1@ff37f000 { 1059f0ab786fSoscardagrach compatible = "hisilicon,hi3660-dw-mshc"; 1060f0ab786fSoscardagrach reg = <0x0 0xff37f000 0x0 0x1000>; 1061804d7d7aSLi Wei #address-cells = <1>; 1062804d7d7aSLi Wei #size-cells = <0>; 1063804d7d7aSLi Wei interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1064804d7d7aSLi Wei clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, 1065804d7d7aSLi Wei <&crg_ctrl HI3660_HCLK_GATE_SD>; 1066804d7d7aSLi Wei clock-names = "ciu", "biu"; 1067804d7d7aSLi Wei clock-frequency = <3200000>; 1068804d7d7aSLi Wei resets = <&crg_rst 0x94 18>; 1069996707d7SGuodong Xu reset-names = "reset"; 1070804d7d7aSLi Wei hisilicon,peripheral-syscon = <&sctrl>; 1071f0ab786fSoscardagrach card-detect-delay = <200>; 1072804d7d7aSLi Wei status = "disabled"; 1073804d7d7aSLi Wei }; 1074804d7d7aSLi Wei 1075804d7d7aSLi Wei /* SDIO */ 1076804d7d7aSLi Wei dwmmc2: dwmmc2@ff3ff000 { 1077804d7d7aSLi Wei compatible = "hisilicon,hi3660-dw-mshc"; 1078804d7d7aSLi Wei reg = <0x0 0xff3ff000 0x0 0x1000>; 1079f0ab786fSoscardagrach #address-cells = <0x1>; 1080f0ab786fSoscardagrach #size-cells = <0x0>; 1081804d7d7aSLi Wei interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1082804d7d7aSLi Wei clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, 1083804d7d7aSLi Wei <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; 1084804d7d7aSLi Wei clock-names = "ciu", "biu"; 1085804d7d7aSLi Wei resets = <&crg_rst 0x94 20>; 1086996707d7SGuodong Xu reset-names = "reset"; 1087804d7d7aSLi Wei card-detect-delay = <200>; 1088804d7d7aSLi Wei status = "disabled"; 1089804d7d7aSLi Wei }; 1090487f00d4SLeo Yan 1091487f00d4SLeo Yan watchdog0: watchdog@e8a06000 { 1092894d4f1fSMichael Walle compatible = "arm,sp805", "arm,primecell"; 1093487f00d4SLeo Yan reg = <0x0 0xe8a06000 0x0 0x1000>; 1094487f00d4SLeo Yan interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1095a665b2c1SAndre Przywara clocks = <&crg_ctrl HI3660_OSC32K>, 1096a665b2c1SAndre Przywara <&crg_ctrl HI3660_OSC32K>; 1097a665b2c1SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 1098487f00d4SLeo Yan }; 1099487f00d4SLeo Yan 1100487f00d4SLeo Yan watchdog1: watchdog@e8a07000 { 1101894d4f1fSMichael Walle compatible = "arm,sp805", "arm,primecell"; 1102487f00d4SLeo Yan reg = <0x0 0xe8a07000 0x0 0x1000>; 1103487f00d4SLeo Yan interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1104a665b2c1SAndre Przywara clocks = <&crg_ctrl HI3660_OSC32K>, 1105a665b2c1SAndre Przywara <&crg_ctrl HI3660_OSC32K>; 1106a665b2c1SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 1107487f00d4SLeo Yan }; 1108a7ab4cb4SKevin Wangtao 1109a7ab4cb4SKevin Wangtao tsensor: tsensor@fff30000 { 1110a7ab4cb4SKevin Wangtao compatible = "hisilicon,hi3660-tsensor"; 1111a7ab4cb4SKevin Wangtao reg = <0x0 0xfff30000 0x0 0x1000>; 1112a7ab4cb4SKevin Wangtao interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 1113a7ab4cb4SKevin Wangtao #thermal-sensor-cells = <1>; 1114a7ab4cb4SKevin Wangtao }; 11158d93e94bSTao Wang 11168d93e94bSTao Wang thermal-zones { 11178d93e94bSTao Wang 1118dbbf5131SZhen Lei cls0: cls0-thermal { 11198d93e94bSTao Wang polling-delay = <1000>; 11208d93e94bSTao Wang polling-delay-passive = <100>; 11218d93e94bSTao Wang sustainable-power = <4500>; 11228d93e94bSTao Wang 11238d93e94bSTao Wang /* sensor ID */ 11248d93e94bSTao Wang thermal-sensors = <&tsensor 1>; 11258d93e94bSTao Wang 11268d93e94bSTao Wang trips { 1127dbbf5131SZhen Lei threshold: trip-point0 { 11288d93e94bSTao Wang temperature = <65000>; 11298d93e94bSTao Wang hysteresis = <1000>; 11308d93e94bSTao Wang type = "passive"; 11318d93e94bSTao Wang }; 11328d93e94bSTao Wang 1133dbbf5131SZhen Lei target: trip-point1 { 11348d93e94bSTao Wang temperature = <75000>; 11358d93e94bSTao Wang hysteresis = <1000>; 11368d93e94bSTao Wang type = "passive"; 11378d93e94bSTao Wang }; 11388d93e94bSTao Wang }; 11398d93e94bSTao Wang 11408d93e94bSTao Wang cooling-maps { 11418d93e94bSTao Wang map0 { 11428d93e94bSTao Wang trip = <&target>; 11438d93e94bSTao Wang contribution = <1024>; 11446ad5506eSViresh Kumar cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 11456ad5506eSViresh Kumar <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 11466ad5506eSViresh Kumar <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 11476ad5506eSViresh Kumar <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 11488d93e94bSTao Wang }; 11498d93e94bSTao Wang map1 { 11508d93e94bSTao Wang trip = <&target>; 11518d93e94bSTao Wang contribution = <512>; 11526ad5506eSViresh Kumar cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 11536ad5506eSViresh Kumar <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 11546ad5506eSViresh Kumar <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 11556ad5506eSViresh Kumar <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 11568d93e94bSTao Wang }; 11578d93e94bSTao Wang }; 11588d93e94bSTao Wang }; 11598d93e94bSTao Wang }; 116047e2843fSJohn Stultz 116147e2843fSJohn Stultz usb3_otg_bc: usb3_otg_bc@ff200000 { 116247e2843fSJohn Stultz compatible = "syscon", "simple-mfd"; 116347e2843fSJohn Stultz reg = <0x0 0xff200000 0x0 0x1000>; 116447e2843fSJohn Stultz 116547e2843fSJohn Stultz usb_phy: usb-phy { 116647e2843fSJohn Stultz compatible = "hisilicon,hi3660-usb-phy"; 116747e2843fSJohn Stultz #phy-cells = <0>; 116847e2843fSJohn Stultz hisilicon,pericrg-syscon = <&crg_ctrl>; 116947e2843fSJohn Stultz hisilicon,pctrl-syscon = <&pctrl>; 117047e2843fSJohn Stultz hisilicon,eye-diagram-param = <0x22466e4>; 117147e2843fSJohn Stultz }; 117247e2843fSJohn Stultz }; 117347e2843fSJohn Stultz 11744dc5288fSSerge Semin dwc3: usb@ff100000 { 117547e2843fSJohn Stultz compatible = "snps,dwc3"; 117647e2843fSJohn Stultz reg = <0x0 0xff100000 0x0 0x100000>; 117747e2843fSJohn Stultz 117847e2843fSJohn Stultz clocks = <&crg_ctrl HI3660_CLK_ABB_USB>, 117947e2843fSJohn Stultz <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; 118047e2843fSJohn Stultz clock-names = "ref", "bus_early"; 118147e2843fSJohn Stultz 118247e2843fSJohn Stultz assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; 118347e2843fSJohn Stultz assigned-clock-rates = <229000000>; 118447e2843fSJohn Stultz 118547e2843fSJohn Stultz resets = <&crg_rst 0x90 8>, 118647e2843fSJohn Stultz <&crg_rst 0x90 7>, 118747e2843fSJohn Stultz <&crg_rst 0x90 6>, 118847e2843fSJohn Stultz <&crg_rst 0x90 5>; 118947e2843fSJohn Stultz 119047e2843fSJohn Stultz interrupts = <0 159 4>, <0 161 4>; 119147e2843fSJohn Stultz phys = <&usb_phy>; 119247e2843fSJohn Stultz phy-names = "usb3-phy"; 119347e2843fSJohn Stultz }; 119435ca8168SChen Feng }; 119535ca8168SChen Feng}; 11969500ff14SWanglai Shi 11979500ff14SWanglai Shi#include "hi3660-coresight.dtsi" 1198