1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP 5 * Dong Aisheng <aisheng.dong@nxp.com> 6 */ 7 8#include <dt-bindings/clock/imx8-clock.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/pinctrl/pads-imx8qxp.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 gpio0 = &lsio_gpio0; 21 gpio1 = &lsio_gpio1; 22 gpio2 = &lsio_gpio2; 23 gpio3 = &lsio_gpio3; 24 gpio4 = &lsio_gpio4; 25 gpio5 = &lsio_gpio5; 26 gpio6 = &lsio_gpio6; 27 gpio7 = &lsio_gpio7; 28 mmc0 = &usdhc1; 29 mmc1 = &usdhc2; 30 mmc2 = &usdhc3; 31 mu1 = &lsio_mu1; 32 serial0 = &adma_lpuart0; 33 serial1 = &adma_lpuart1; 34 serial2 = &adma_lpuart2; 35 serial3 = &adma_lpuart3; 36 }; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 /* We have 1 clusters with 4 Cortex-A35 cores */ 43 A35_0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a35"; 46 reg = <0x0 0x0>; 47 enable-method = "psci"; 48 next-level-cache = <&A35_L2>; 49 clocks = <&clk IMX_A35_CLK>; 50 operating-points-v2 = <&a35_opp_table>; 51 #cooling-cells = <2>; 52 }; 53 54 A35_1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a35"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 next-level-cache = <&A35_L2>; 60 clocks = <&clk IMX_A35_CLK>; 61 operating-points-v2 = <&a35_opp_table>; 62 #cooling-cells = <2>; 63 }; 64 65 A35_2: cpu@2 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a35"; 68 reg = <0x0 0x2>; 69 enable-method = "psci"; 70 next-level-cache = <&A35_L2>; 71 clocks = <&clk IMX_A35_CLK>; 72 operating-points-v2 = <&a35_opp_table>; 73 #cooling-cells = <2>; 74 }; 75 76 A35_3: cpu@3 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a35"; 79 reg = <0x0 0x3>; 80 enable-method = "psci"; 81 next-level-cache = <&A35_L2>; 82 clocks = <&clk IMX_A35_CLK>; 83 operating-points-v2 = <&a35_opp_table>; 84 #cooling-cells = <2>; 85 }; 86 87 A35_L2: l2-cache0 { 88 compatible = "cache"; 89 }; 90 }; 91 92 a35_opp_table: opp-table { 93 compatible = "operating-points-v2"; 94 opp-shared; 95 96 opp-900000000 { 97 opp-hz = /bits/ 64 <900000000>; 98 opp-microvolt = <1000000>; 99 clock-latency-ns = <150000>; 100 }; 101 102 opp-1200000000 { 103 opp-hz = /bits/ 64 <1200000000>; 104 opp-microvolt = <1100000>; 105 clock-latency-ns = <150000>; 106 opp-suspend; 107 }; 108 }; 109 110 gic: interrupt-controller@51a00000 { 111 compatible = "arm,gic-v3"; 112 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 113 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 114 #interrupt-cells = <3>; 115 interrupt-controller; 116 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 117 }; 118 119 pmu { 120 compatible = "arm,armv8-pmuv3"; 121 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 122 }; 123 124 psci { 125 compatible = "arm,psci-1.0"; 126 method = "smc"; 127 }; 128 129 scu { 130 compatible = "fsl,imx-scu"; 131 mbox-names = "tx0", "tx1", "tx2", "tx3", 132 "rx0", "rx1", "rx2", "rx3", 133 "gip3"; 134 mboxes = <&lsio_mu1 0 0 135 &lsio_mu1 0 1 136 &lsio_mu1 0 2 137 &lsio_mu1 0 3 138 &lsio_mu1 1 0 139 &lsio_mu1 1 1 140 &lsio_mu1 1 2 141 &lsio_mu1 1 3 142 &lsio_mu1 3 3>; 143 144 clk: clock-controller { 145 compatible = "fsl,imx8qxp-clk"; 146 #clock-cells = <1>; 147 clocks = <&xtal32k &xtal24m>; 148 clock-names = "xtal_32KHz", "xtal_24Mhz"; 149 }; 150 151 iomuxc: pinctrl { 152 compatible = "fsl,imx8qxp-iomuxc"; 153 }; 154 155 ocotp: imx8qx-ocotp { 156 compatible = "fsl,imx8qxp-scu-ocotp"; 157 #address-cells = <1>; 158 #size-cells = <1>; 159 }; 160 161 pd: imx8qx-pd { 162 compatible = "fsl,imx8qxp-scu-pd"; 163 #power-domain-cells = <1>; 164 }; 165 166 rtc: rtc { 167 compatible = "fsl,imx8qxp-sc-rtc"; 168 }; 169 170 watchdog { 171 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 172 timeout-sec = <60>; 173 }; 174 }; 175 176 timer { 177 compatible = "arm,armv8-timer"; 178 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 179 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 180 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 181 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 182 }; 183 184 xtal32k: clock-xtal32k { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency = <32768>; 188 clock-output-names = "xtal_32KHz"; 189 }; 190 191 xtal24m: clock-xtal24m { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <24000000>; 195 clock-output-names = "xtal_24MHz"; 196 }; 197 198 adma_subsys: bus@59000000 { 199 compatible = "simple-bus"; 200 #address-cells = <1>; 201 #size-cells = <1>; 202 ranges = <0x59000000 0x0 0x59000000 0x2000000>; 203 204 adma_lpcg: clock-controller@59000000 { 205 compatible = "fsl,imx8qxp-lpcg-adma"; 206 reg = <0x59000000 0x2000000>; 207 #clock-cells = <1>; 208 }; 209 210 adma_lpuart0: serial@5a060000 { 211 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 212 reg = <0x5a060000 0x1000>; 213 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 214 interrupt-parent = <&gic>; 215 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>, 216 <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; 217 clock-names = "ipg", "baud"; 218 power-domains = <&pd IMX_SC_R_UART_0>; 219 status = "disabled"; 220 }; 221 222 adma_lpuart1: serial@5a070000 { 223 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 224 reg = <0x5a070000 0x1000>; 225 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 226 interrupt-parent = <&gic>; 227 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, 228 <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; 229 clock-names = "ipg", "baud"; 230 power-domains = <&pd IMX_SC_R_UART_1>; 231 status = "disabled"; 232 }; 233 234 adma_lpuart2: serial@5a080000 { 235 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 236 reg = <0x5a080000 0x1000>; 237 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 238 interrupt-parent = <&gic>; 239 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>, 240 <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; 241 clock-names = "ipg", "baud"; 242 power-domains = <&pd IMX_SC_R_UART_2>; 243 status = "disabled"; 244 }; 245 246 adma_lpuart3: serial@5a090000 { 247 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 248 reg = <0x5a090000 0x1000>; 249 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 250 interrupt-parent = <&gic>; 251 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>, 252 <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; 253 clock-names = "ipg", "baud"; 254 power-domains = <&pd IMX_SC_R_UART_3>; 255 status = "disabled"; 256 }; 257 258 adma_i2c0: i2c@5a800000 { 259 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 260 reg = <0x5a800000 0x4000>; 261 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 262 interrupt-parent = <&gic>; 263 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; 264 clock-names = "per"; 265 assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; 266 assigned-clock-rates = <24000000>; 267 power-domains = <&pd IMX_SC_R_I2C_0>; 268 status = "disabled"; 269 }; 270 271 adma_i2c1: i2c@5a810000 { 272 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 273 reg = <0x5a810000 0x4000>; 274 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 275 interrupt-parent = <&gic>; 276 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; 277 clock-names = "per"; 278 assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; 279 assigned-clock-rates = <24000000>; 280 power-domains = <&pd IMX_SC_R_I2C_1>; 281 status = "disabled"; 282 }; 283 284 adma_i2c2: i2c@5a820000 { 285 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 286 reg = <0x5a820000 0x4000>; 287 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 288 interrupt-parent = <&gic>; 289 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; 290 clock-names = "per"; 291 assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; 292 assigned-clock-rates = <24000000>; 293 power-domains = <&pd IMX_SC_R_I2C_2>; 294 status = "disabled"; 295 }; 296 297 adma_i2c3: i2c@5a830000 { 298 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 299 reg = <0x5a830000 0x4000>; 300 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 301 interrupt-parent = <&gic>; 302 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; 303 clock-names = "per"; 304 assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; 305 assigned-clock-rates = <24000000>; 306 power-domains = <&pd IMX_SC_R_I2C_3>; 307 status = "disabled"; 308 }; 309 }; 310 311 conn_subsys: bus@5b000000 { 312 compatible = "simple-bus"; 313 #address-cells = <1>; 314 #size-cells = <1>; 315 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 316 317 conn_lpcg: clock-controller@5b200000 { 318 compatible = "fsl,imx8qxp-lpcg-conn"; 319 reg = <0x5b200000 0xb0000>; 320 #clock-cells = <1>; 321 }; 322 323 usdhc1: mmc@5b010000 { 324 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 325 interrupt-parent = <&gic>; 326 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 327 reg = <0x5b010000 0x10000>; 328 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, 329 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, 330 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; 331 clock-names = "ipg", "per", "ahb"; 332 assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; 333 assigned-clock-rates = <200000000>; 334 power-domains = <&pd IMX_SC_R_SDHC_0>; 335 status = "disabled"; 336 }; 337 338 usdhc2: mmc@5b020000 { 339 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 340 interrupt-parent = <&gic>; 341 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 342 reg = <0x5b020000 0x10000>; 343 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, 344 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, 345 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; 346 clock-names = "ipg", "per", "ahb"; 347 assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; 348 assigned-clock-rates = <200000000>; 349 power-domains = <&pd IMX_SC_R_SDHC_1>; 350 fsl,tuning-start-tap = <20>; 351 fsl,tuning-step= <2>; 352 status = "disabled"; 353 }; 354 355 usdhc3: mmc@5b030000 { 356 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 357 interrupt-parent = <&gic>; 358 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 359 reg = <0x5b030000 0x10000>; 360 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, 361 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, 362 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; 363 clock-names = "ipg", "per", "ahb"; 364 assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; 365 assigned-clock-rates = <200000000>; 366 power-domains = <&pd IMX_SC_R_SDHC_2>; 367 status = "disabled"; 368 }; 369 370 fec1: ethernet@5b040000 { 371 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 372 reg = <0x5b040000 0x10000>; 373 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, 378 <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, 379 <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, 380 <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; 381 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 382 fsl,num-tx-queues=<3>; 383 fsl,num-rx-queues=<3>; 384 power-domains = <&pd IMX_SC_R_ENET_0>; 385 status = "disabled"; 386 }; 387 388 fec2: ethernet@5b050000 { 389 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 390 reg = <0x5b050000 0x10000>; 391 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, 396 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, 397 <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, 398 <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; 399 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 400 fsl,num-tx-queues=<3>; 401 fsl,num-rx-queues=<3>; 402 power-domains = <&pd IMX_SC_R_ENET_1>; 403 status = "disabled"; 404 }; 405 }; 406 407 ddr_subsyss: bus@5c000000 { 408 compatible = "simple-bus"; 409 #address-cells = <1>; 410 #size-cells = <1>; 411 ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; 412 413 ddr-pmu@5c020000 { 414 compatible = "fsl,imx8-ddr-pmu"; 415 reg = <0x5c020000 0x10000>; 416 interrupt-parent = <&gic>; 417 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 418 }; 419 }; 420 421 lsio_subsys: bus@5d000000 { 422 compatible = "simple-bus"; 423 #address-cells = <1>; 424 #size-cells = <1>; 425 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; 426 427 lsio_gpio0: gpio@5d080000 { 428 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 429 reg = <0x5d080000 0x10000>; 430 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 431 gpio-controller; 432 #gpio-cells = <2>; 433 interrupt-controller; 434 #interrupt-cells = <2>; 435 power-domains = <&pd IMX_SC_R_GPIO_0>; 436 }; 437 438 lsio_gpio1: gpio@5d090000 { 439 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 440 reg = <0x5d090000 0x10000>; 441 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 442 gpio-controller; 443 #gpio-cells = <2>; 444 interrupt-controller; 445 #interrupt-cells = <2>; 446 power-domains = <&pd IMX_SC_R_GPIO_1>; 447 }; 448 449 lsio_gpio2: gpio@5d0a0000 { 450 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 451 reg = <0x5d0a0000 0x10000>; 452 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 453 gpio-controller; 454 #gpio-cells = <2>; 455 interrupt-controller; 456 #interrupt-cells = <2>; 457 power-domains = <&pd IMX_SC_R_GPIO_2>; 458 }; 459 460 lsio_gpio3: gpio@5d0b0000 { 461 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 462 reg = <0x5d0b0000 0x10000>; 463 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 464 gpio-controller; 465 #gpio-cells = <2>; 466 interrupt-controller; 467 #interrupt-cells = <2>; 468 power-domains = <&pd IMX_SC_R_GPIO_3>; 469 }; 470 471 lsio_gpio4: gpio@5d0c0000 { 472 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 473 reg = <0x5d0c0000 0x10000>; 474 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 475 gpio-controller; 476 #gpio-cells = <2>; 477 interrupt-controller; 478 #interrupt-cells = <2>; 479 power-domains = <&pd IMX_SC_R_GPIO_4>; 480 }; 481 482 lsio_gpio5: gpio@5d0d0000 { 483 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 484 reg = <0x5d0d0000 0x10000>; 485 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 486 gpio-controller; 487 #gpio-cells = <2>; 488 interrupt-controller; 489 #interrupt-cells = <2>; 490 power-domains = <&pd IMX_SC_R_GPIO_5>; 491 }; 492 493 lsio_gpio6: gpio@5d0e0000 { 494 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 495 reg = <0x5d0e0000 0x10000>; 496 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 497 gpio-controller; 498 #gpio-cells = <2>; 499 interrupt-controller; 500 #interrupt-cells = <2>; 501 power-domains = <&pd IMX_SC_R_GPIO_6>; 502 }; 503 504 lsio_gpio7: gpio@5d0f0000 { 505 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 506 reg = <0x5d0f0000 0x10000>; 507 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 508 gpio-controller; 509 #gpio-cells = <2>; 510 interrupt-controller; 511 #interrupt-cells = <2>; 512 power-domains = <&pd IMX_SC_R_GPIO_7>; 513 }; 514 515 lsio_mu0: mailbox@5d1b0000 { 516 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 517 reg = <0x5d1b0000 0x10000>; 518 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 519 #mbox-cells = <2>; 520 status = "disabled"; 521 }; 522 523 lsio_mu1: mailbox@5d1c0000 { 524 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 525 reg = <0x5d1c0000 0x10000>; 526 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 527 #mbox-cells = <2>; 528 }; 529 530 lsio_mu2: mailbox@5d1d0000 { 531 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 532 reg = <0x5d1d0000 0x10000>; 533 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 534 #mbox-cells = <2>; 535 status = "disabled"; 536 }; 537 538 lsio_mu3: mailbox@5d1e0000 { 539 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 540 reg = <0x5d1e0000 0x10000>; 541 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 542 #mbox-cells = <2>; 543 status = "disabled"; 544 }; 545 546 lsio_mu4: mailbox@5d1f0000 { 547 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 548 reg = <0x5d1f0000 0x10000>; 549 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 550 #mbox-cells = <2>; 551 status = "disabled"; 552 }; 553 554 lsio_mu13: mailbox@5d280000 { 555 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 556 reg = <0x5d280000 0x10000>; 557 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 558 #mbox-cells = <2>; 559 power-domains = <&pd IMX_SC_R_MU_13A>; 560 }; 561 562 lsio_lpcg: clock-controller@5d400000 { 563 compatible = "fsl,imx8qxp-lpcg-lsio"; 564 reg = <0x5d400000 0x400000>; 565 #clock-cells = <1>; 566 }; 567 }; 568}; 569