1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP 5 * Dong Aisheng <aisheng.dong@nxp.com> 6 */ 7 8#include <dt-bindings/clock/imx8-clock.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/pinctrl/pads-imx8qxp.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 gpio0 = &lsio_gpio0; 22 gpio1 = &lsio_gpio1; 23 gpio2 = &lsio_gpio2; 24 gpio3 = &lsio_gpio3; 25 gpio4 = &lsio_gpio4; 26 gpio5 = &lsio_gpio5; 27 gpio6 = &lsio_gpio6; 28 gpio7 = &lsio_gpio7; 29 mmc0 = &usdhc1; 30 mmc1 = &usdhc2; 31 mmc2 = &usdhc3; 32 mu1 = &lsio_mu1; 33 serial0 = &adma_lpuart0; 34 serial1 = &adma_lpuart1; 35 serial2 = &adma_lpuart2; 36 serial3 = &adma_lpuart3; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 /* We have 1 clusters with 4 Cortex-A35 cores */ 44 A35_0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a35"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 next-level-cache = <&A35_L2>; 50 clocks = <&clk IMX_A35_CLK>; 51 operating-points-v2 = <&a35_opp_table>; 52 #cooling-cells = <2>; 53 }; 54 55 A35_1: cpu@1 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a35"; 58 reg = <0x0 0x1>; 59 enable-method = "psci"; 60 next-level-cache = <&A35_L2>; 61 clocks = <&clk IMX_A35_CLK>; 62 operating-points-v2 = <&a35_opp_table>; 63 #cooling-cells = <2>; 64 }; 65 66 A35_2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a35"; 69 reg = <0x0 0x2>; 70 enable-method = "psci"; 71 next-level-cache = <&A35_L2>; 72 clocks = <&clk IMX_A35_CLK>; 73 operating-points-v2 = <&a35_opp_table>; 74 #cooling-cells = <2>; 75 }; 76 77 A35_3: cpu@3 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a35"; 80 reg = <0x0 0x3>; 81 enable-method = "psci"; 82 next-level-cache = <&A35_L2>; 83 clocks = <&clk IMX_A35_CLK>; 84 operating-points-v2 = <&a35_opp_table>; 85 #cooling-cells = <2>; 86 }; 87 88 A35_L2: l2-cache0 { 89 compatible = "cache"; 90 }; 91 }; 92 93 a35_opp_table: opp-table { 94 compatible = "operating-points-v2"; 95 opp-shared; 96 97 opp-900000000 { 98 opp-hz = /bits/ 64 <900000000>; 99 opp-microvolt = <1000000>; 100 clock-latency-ns = <150000>; 101 }; 102 103 opp-1200000000 { 104 opp-hz = /bits/ 64 <1200000000>; 105 opp-microvolt = <1100000>; 106 clock-latency-ns = <150000>; 107 opp-suspend; 108 }; 109 }; 110 111 gic: interrupt-controller@51a00000 { 112 compatible = "arm,gic-v3"; 113 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 114 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 115 #interrupt-cells = <3>; 116 interrupt-controller; 117 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 118 }; 119 120 reserved-memory { 121 #address-cells = <2>; 122 #size-cells = <2>; 123 ranges; 124 125 dsp_reserved: dsp@92400000 { 126 reg = <0 0x92400000 0 0x2000000>; 127 no-map; 128 }; 129 }; 130 131 pmu { 132 compatible = "arm,armv8-pmuv3"; 133 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 134 }; 135 136 psci { 137 compatible = "arm,psci-1.0"; 138 method = "smc"; 139 }; 140 141 scu { 142 compatible = "fsl,imx-scu"; 143 mbox-names = "tx0", "tx1", "tx2", "tx3", 144 "rx0", "rx1", "rx2", "rx3", 145 "gip3"; 146 mboxes = <&lsio_mu1 0 0 147 &lsio_mu1 0 1 148 &lsio_mu1 0 2 149 &lsio_mu1 0 3 150 &lsio_mu1 1 0 151 &lsio_mu1 1 1 152 &lsio_mu1 1 2 153 &lsio_mu1 1 3 154 &lsio_mu1 3 3>; 155 156 clk: clock-controller { 157 compatible = "fsl,imx8qxp-clk"; 158 #clock-cells = <1>; 159 clocks = <&xtal32k &xtal24m>; 160 clock-names = "xtal_32KHz", "xtal_24Mhz"; 161 }; 162 163 iomuxc: pinctrl { 164 compatible = "fsl,imx8qxp-iomuxc"; 165 }; 166 167 ocotp: imx8qx-ocotp { 168 compatible = "fsl,imx8qxp-scu-ocotp"; 169 #address-cells = <1>; 170 #size-cells = <1>; 171 }; 172 173 pd: imx8qx-pd { 174 compatible = "fsl,imx8qxp-scu-pd"; 175 #power-domain-cells = <1>; 176 }; 177 178 scu_key: scu-key { 179 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 180 linux,keycodes = <KEY_POWER>; 181 status = "disabled"; 182 }; 183 184 rtc: rtc { 185 compatible = "fsl,imx8qxp-sc-rtc"; 186 }; 187 188 watchdog { 189 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 190 timeout-sec = <60>; 191 }; 192 }; 193 194 timer { 195 compatible = "arm,armv8-timer"; 196 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 197 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 198 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 199 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 200 }; 201 202 xtal32k: clock-xtal32k { 203 compatible = "fixed-clock"; 204 #clock-cells = <0>; 205 clock-frequency = <32768>; 206 clock-output-names = "xtal_32KHz"; 207 }; 208 209 xtal24m: clock-xtal24m { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <24000000>; 213 clock-output-names = "xtal_24MHz"; 214 }; 215 216 adma_subsys: bus@59000000 { 217 compatible = "simple-bus"; 218 #address-cells = <1>; 219 #size-cells = <1>; 220 ranges = <0x59000000 0x0 0x59000000 0x2000000>; 221 222 adma_lpcg: clock-controller@59000000 { 223 compatible = "fsl,imx8qxp-lpcg-adma"; 224 reg = <0x59000000 0x2000000>; 225 #clock-cells = <1>; 226 }; 227 228 adma_dsp: dsp@596e8000 { 229 compatible = "fsl,imx8qxp-dsp"; 230 reg = <0x596e8000 0x88000>; 231 clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, 232 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, 233 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; 234 clock-names = "ipg", "ocram", "core"; 235 power-domains = <&pd IMX_SC_R_MU_13A>, 236 <&pd IMX_SC_R_MU_13B>, 237 <&pd IMX_SC_R_DSP>, 238 <&pd IMX_SC_R_DSP_RAM>; 239 mbox-names = "txdb0", "txdb1", 240 "rxdb0", "rxdb1"; 241 mboxes = <&lsio_mu13 2 0>, 242 <&lsio_mu13 2 1>, 243 <&lsio_mu13 3 0>, 244 <&lsio_mu13 3 1>; 245 memory-region = <&dsp_reserved>; 246 status = "disabled"; 247 }; 248 249 adma_lpuart0: serial@5a060000 { 250 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 251 reg = <0x5a060000 0x1000>; 252 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 253 interrupt-parent = <&gic>; 254 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>, 255 <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; 256 clock-names = "ipg", "baud"; 257 power-domains = <&pd IMX_SC_R_UART_0>; 258 status = "disabled"; 259 }; 260 261 adma_lpuart1: serial@5a070000 { 262 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 263 reg = <0x5a070000 0x1000>; 264 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 265 interrupt-parent = <&gic>; 266 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, 267 <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; 268 clock-names = "ipg", "baud"; 269 power-domains = <&pd IMX_SC_R_UART_1>; 270 status = "disabled"; 271 }; 272 273 adma_lpuart2: serial@5a080000 { 274 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 275 reg = <0x5a080000 0x1000>; 276 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 277 interrupt-parent = <&gic>; 278 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>, 279 <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; 280 clock-names = "ipg", "baud"; 281 power-domains = <&pd IMX_SC_R_UART_2>; 282 status = "disabled"; 283 }; 284 285 adma_lpuart3: serial@5a090000 { 286 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 287 reg = <0x5a090000 0x1000>; 288 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 289 interrupt-parent = <&gic>; 290 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>, 291 <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; 292 clock-names = "ipg", "baud"; 293 power-domains = <&pd IMX_SC_R_UART_3>; 294 status = "disabled"; 295 }; 296 297 adma_i2c0: i2c@5a800000 { 298 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 299 reg = <0x5a800000 0x4000>; 300 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 301 interrupt-parent = <&gic>; 302 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; 303 clock-names = "per"; 304 assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; 305 assigned-clock-rates = <24000000>; 306 power-domains = <&pd IMX_SC_R_I2C_0>; 307 status = "disabled"; 308 }; 309 310 adma_i2c1: i2c@5a810000 { 311 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 312 reg = <0x5a810000 0x4000>; 313 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 314 interrupt-parent = <&gic>; 315 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; 316 clock-names = "per"; 317 assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; 318 assigned-clock-rates = <24000000>; 319 power-domains = <&pd IMX_SC_R_I2C_1>; 320 status = "disabled"; 321 }; 322 323 adma_i2c2: i2c@5a820000 { 324 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 325 reg = <0x5a820000 0x4000>; 326 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 327 interrupt-parent = <&gic>; 328 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; 329 clock-names = "per"; 330 assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; 331 assigned-clock-rates = <24000000>; 332 power-domains = <&pd IMX_SC_R_I2C_2>; 333 status = "disabled"; 334 }; 335 336 adma_i2c3: i2c@5a830000 { 337 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 338 reg = <0x5a830000 0x4000>; 339 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 340 interrupt-parent = <&gic>; 341 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; 342 clock-names = "per"; 343 assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; 344 assigned-clock-rates = <24000000>; 345 power-domains = <&pd IMX_SC_R_I2C_3>; 346 status = "disabled"; 347 }; 348 }; 349 350 conn_subsys: bus@5b000000 { 351 compatible = "simple-bus"; 352 #address-cells = <1>; 353 #size-cells = <1>; 354 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 355 356 conn_lpcg: clock-controller@5b200000 { 357 compatible = "fsl,imx8qxp-lpcg-conn"; 358 reg = <0x5b200000 0xb0000>; 359 #clock-cells = <1>; 360 }; 361 362 usdhc1: mmc@5b010000 { 363 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 364 interrupt-parent = <&gic>; 365 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 366 reg = <0x5b010000 0x10000>; 367 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, 368 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, 369 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; 370 clock-names = "ipg", "per", "ahb"; 371 assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; 372 assigned-clock-rates = <200000000>; 373 power-domains = <&pd IMX_SC_R_SDHC_0>; 374 status = "disabled"; 375 }; 376 377 usdhc2: mmc@5b020000 { 378 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 379 interrupt-parent = <&gic>; 380 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 381 reg = <0x5b020000 0x10000>; 382 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, 383 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, 384 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; 385 clock-names = "ipg", "per", "ahb"; 386 assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; 387 assigned-clock-rates = <200000000>; 388 power-domains = <&pd IMX_SC_R_SDHC_1>; 389 fsl,tuning-start-tap = <20>; 390 fsl,tuning-step= <2>; 391 status = "disabled"; 392 }; 393 394 usdhc3: mmc@5b030000 { 395 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 396 interrupt-parent = <&gic>; 397 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 398 reg = <0x5b030000 0x10000>; 399 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, 400 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, 401 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; 402 clock-names = "ipg", "per", "ahb"; 403 assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; 404 assigned-clock-rates = <200000000>; 405 power-domains = <&pd IMX_SC_R_SDHC_2>; 406 status = "disabled"; 407 }; 408 409 fec1: ethernet@5b040000 { 410 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 411 reg = <0x5b040000 0x10000>; 412 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, 417 <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, 418 <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, 419 <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; 420 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 421 fsl,num-tx-queues=<3>; 422 fsl,num-rx-queues=<3>; 423 power-domains = <&pd IMX_SC_R_ENET_0>; 424 status = "disabled"; 425 }; 426 427 fec2: ethernet@5b050000 { 428 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 429 reg = <0x5b050000 0x10000>; 430 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, 435 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, 436 <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, 437 <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; 438 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 439 fsl,num-tx-queues=<3>; 440 fsl,num-rx-queues=<3>; 441 power-domains = <&pd IMX_SC_R_ENET_1>; 442 status = "disabled"; 443 }; 444 }; 445 446 ddr_subsyss: bus@5c000000 { 447 compatible = "simple-bus"; 448 #address-cells = <1>; 449 #size-cells = <1>; 450 ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; 451 452 ddr-pmu@5c020000 { 453 compatible = "fsl,imx8-ddr-pmu"; 454 reg = <0x5c020000 0x10000>; 455 interrupt-parent = <&gic>; 456 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 457 }; 458 }; 459 460 lsio_subsys: bus@5d000000 { 461 compatible = "simple-bus"; 462 #address-cells = <1>; 463 #size-cells = <1>; 464 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; 465 466 lsio_gpio0: gpio@5d080000 { 467 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 468 reg = <0x5d080000 0x10000>; 469 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 470 gpio-controller; 471 #gpio-cells = <2>; 472 interrupt-controller; 473 #interrupt-cells = <2>; 474 power-domains = <&pd IMX_SC_R_GPIO_0>; 475 }; 476 477 lsio_gpio1: gpio@5d090000 { 478 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 479 reg = <0x5d090000 0x10000>; 480 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 481 gpio-controller; 482 #gpio-cells = <2>; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 power-domains = <&pd IMX_SC_R_GPIO_1>; 486 }; 487 488 lsio_gpio2: gpio@5d0a0000 { 489 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 490 reg = <0x5d0a0000 0x10000>; 491 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 492 gpio-controller; 493 #gpio-cells = <2>; 494 interrupt-controller; 495 #interrupt-cells = <2>; 496 power-domains = <&pd IMX_SC_R_GPIO_2>; 497 }; 498 499 lsio_gpio3: gpio@5d0b0000 { 500 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 501 reg = <0x5d0b0000 0x10000>; 502 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 503 gpio-controller; 504 #gpio-cells = <2>; 505 interrupt-controller; 506 #interrupt-cells = <2>; 507 power-domains = <&pd IMX_SC_R_GPIO_3>; 508 }; 509 510 lsio_gpio4: gpio@5d0c0000 { 511 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 512 reg = <0x5d0c0000 0x10000>; 513 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 514 gpio-controller; 515 #gpio-cells = <2>; 516 interrupt-controller; 517 #interrupt-cells = <2>; 518 power-domains = <&pd IMX_SC_R_GPIO_4>; 519 }; 520 521 lsio_gpio5: gpio@5d0d0000 { 522 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 523 reg = <0x5d0d0000 0x10000>; 524 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 525 gpio-controller; 526 #gpio-cells = <2>; 527 interrupt-controller; 528 #interrupt-cells = <2>; 529 power-domains = <&pd IMX_SC_R_GPIO_5>; 530 }; 531 532 lsio_gpio6: gpio@5d0e0000 { 533 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 534 reg = <0x5d0e0000 0x10000>; 535 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 536 gpio-controller; 537 #gpio-cells = <2>; 538 interrupt-controller; 539 #interrupt-cells = <2>; 540 power-domains = <&pd IMX_SC_R_GPIO_6>; 541 }; 542 543 lsio_gpio7: gpio@5d0f0000 { 544 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 545 reg = <0x5d0f0000 0x10000>; 546 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 547 gpio-controller; 548 #gpio-cells = <2>; 549 interrupt-controller; 550 #interrupt-cells = <2>; 551 power-domains = <&pd IMX_SC_R_GPIO_7>; 552 }; 553 554 lsio_mu0: mailbox@5d1b0000 { 555 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 556 reg = <0x5d1b0000 0x10000>; 557 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 558 #mbox-cells = <2>; 559 status = "disabled"; 560 }; 561 562 lsio_mu1: mailbox@5d1c0000 { 563 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 564 reg = <0x5d1c0000 0x10000>; 565 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 566 #mbox-cells = <2>; 567 }; 568 569 lsio_mu2: mailbox@5d1d0000 { 570 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 571 reg = <0x5d1d0000 0x10000>; 572 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 573 #mbox-cells = <2>; 574 status = "disabled"; 575 }; 576 577 lsio_mu3: mailbox@5d1e0000 { 578 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 579 reg = <0x5d1e0000 0x10000>; 580 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 581 #mbox-cells = <2>; 582 status = "disabled"; 583 }; 584 585 lsio_mu4: mailbox@5d1f0000 { 586 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 587 reg = <0x5d1f0000 0x10000>; 588 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 589 #mbox-cells = <2>; 590 status = "disabled"; 591 }; 592 593 lsio_mu13: mailbox@5d280000 { 594 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 595 reg = <0x5d280000 0x10000>; 596 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 597 #mbox-cells = <2>; 598 power-domains = <&pd IMX_SC_R_MU_13A>; 599 }; 600 601 lsio_lpcg: clock-controller@5d400000 { 602 compatible = "fsl,imx8qxp-lpcg-lsio"; 603 reg = <0x5d400000 0x400000>; 604 #clock-cells = <1>; 605 }; 606 }; 607}; 608