1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP 5 * Dong Aisheng <aisheng.dong@nxp.com> 6 */ 7 8#include <dt-bindings/clock/imx8-clock.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/pinctrl/pads-imx8qxp.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 mmc0 = &usdhc1; 21 mmc1 = &usdhc2; 22 mmc2 = &usdhc3; 23 serial0 = &adma_lpuart0; 24 }; 25 26 cpus { 27 #address-cells = <2>; 28 #size-cells = <0>; 29 30 /* We have 1 clusters with 4 Cortex-A35 cores */ 31 A35_0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a35"; 34 reg = <0x0 0x0>; 35 enable-method = "psci"; 36 next-level-cache = <&A35_L2>; 37 }; 38 39 A35_1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a35"; 42 reg = <0x0 0x1>; 43 enable-method = "psci"; 44 next-level-cache = <&A35_L2>; 45 }; 46 47 A35_2: cpu@2 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a35"; 50 reg = <0x0 0x2>; 51 enable-method = "psci"; 52 next-level-cache = <&A35_L2>; 53 }; 54 55 A35_3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a35"; 58 reg = <0x0 0x3>; 59 enable-method = "psci"; 60 next-level-cache = <&A35_L2>; 61 }; 62 63 A35_L2: l2-cache0 { 64 compatible = "cache"; 65 }; 66 }; 67 68 gic: interrupt-controller@51a00000 { 69 compatible = "arm,gic-v3"; 70 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 71 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 72 #interrupt-cells = <3>; 73 interrupt-controller; 74 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 75 }; 76 77 pmu { 78 compatible = "arm,armv8-pmuv3"; 79 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 80 }; 81 82 psci { 83 compatible = "arm,psci-1.0"; 84 method = "smc"; 85 }; 86 87 scu { 88 compatible = "fsl,imx-scu"; 89 mbox-names = "tx0", "tx1", "tx2", "tx3", 90 "rx0", "rx1", "rx2", "rx3"; 91 mboxes = <&lsio_mu1 0 0 92 &lsio_mu1 0 1 93 &lsio_mu1 0 2 94 &lsio_mu1 0 3 95 &lsio_mu1 1 0 96 &lsio_mu1 1 1 97 &lsio_mu1 1 2 98 &lsio_mu1 1 3>; 99 100 clk: clock-controller { 101 compatible = "fsl,imx8qxp-clk"; 102 #clock-cells = <1>; 103 clocks = <&xtal32k &xtal24m>; 104 clock-names = "xtal_32KHz", "xtal_24Mhz"; 105 }; 106 107 iomuxc: pinctrl { 108 compatible = "fsl,imx8qxp-iomuxc"; 109 }; 110 111 pd: imx8qx-pd { 112 compatible = "fsl,imx8qxp-scu-pd"; 113 #power-domain-cells = <1>; 114 }; 115 }; 116 117 timer { 118 compatible = "arm,armv8-timer"; 119 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 120 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 121 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 122 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 123 }; 124 125 xtal32k: clock-xtal32k { 126 compatible = "fixed-clock"; 127 #clock-cells = <0>; 128 clock-frequency = <32768>; 129 clock-output-names = "xtal_32KHz"; 130 }; 131 132 xtal24m: clock-xtal24m { 133 compatible = "fixed-clock"; 134 #clock-cells = <0>; 135 clock-frequency = <24000000>; 136 clock-output-names = "xtal_24MHz"; 137 }; 138 139 adma_subsys: bus@59000000 { 140 compatible = "simple-bus"; 141 #address-cells = <1>; 142 #size-cells = <1>; 143 ranges = <0x59000000 0x0 0x59000000 0x2000000>; 144 145 adma_lpcg: clock-controller@59000000 { 146 compatible = "fsl,imx8qxp-lpcg-adma"; 147 reg = <0x59000000 0x2000000>; 148 #clock-cells = <1>; 149 }; 150 151 adma_lpuart0: serial@5a060000 { 152 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 153 reg = <0x5a060000 0x1000>; 154 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 155 interrupt-parent = <&gic>; 156 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; 157 clock-names = "ipg"; 158 power-domains = <&pd IMX_SC_R_UART_0>; 159 status = "disabled"; 160 }; 161 162 adma_i2c0: i2c@5a800000 { 163 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 164 reg = <0x5a800000 0x4000>; 165 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 166 interrupt-parent = <&gic>; 167 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; 168 clock-names = "per"; 169 assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; 170 assigned-clock-rates = <24000000>; 171 power-domains = <&pd IMX_SC_R_I2C_0>; 172 status = "disabled"; 173 }; 174 175 adma_i2c1: i2c@5a810000 { 176 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 177 reg = <0x5a810000 0x4000>; 178 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 179 interrupt-parent = <&gic>; 180 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; 181 clock-names = "per"; 182 assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; 183 assigned-clock-rates = <24000000>; 184 power-domains = <&pd IMX_SC_R_I2C_1>; 185 status = "disabled"; 186 }; 187 188 adma_i2c2: i2c@5a820000 { 189 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 190 reg = <0x5a820000 0x4000>; 191 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 192 interrupt-parent = <&gic>; 193 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; 194 clock-names = "per"; 195 assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; 196 assigned-clock-rates = <24000000>; 197 power-domains = <&pd IMX_SC_R_I2C_2>; 198 status = "disabled"; 199 }; 200 201 adma_i2c3: i2c@5a830000 { 202 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 203 reg = <0x5a830000 0x4000>; 204 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 205 interrupt-parent = <&gic>; 206 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; 207 clock-names = "per"; 208 assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; 209 assigned-clock-rates = <24000000>; 210 power-domains = <&pd IMX_SC_R_I2C_3>; 211 status = "disabled"; 212 }; 213 }; 214 215 conn_subsys: bus@5b000000 { 216 compatible = "simple-bus"; 217 #address-cells = <1>; 218 #size-cells = <1>; 219 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 220 221 conn_lpcg: clock-controller@5b200000 { 222 compatible = "fsl,imx8qxp-lpcg-conn"; 223 reg = <0x5b200000 0xb0000>; 224 #clock-cells = <1>; 225 }; 226 227 usdhc1: mmc@5b010000 { 228 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 229 interrupt-parent = <&gic>; 230 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 231 reg = <0x5b010000 0x10000>; 232 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, 233 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, 234 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; 235 clock-names = "ipg", "per", "ahb"; 236 assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; 237 assigned-clock-rates = <200000000>; 238 power-domains = <&pd IMX_SC_R_SDHC_0>; 239 status = "disabled"; 240 }; 241 242 usdhc2: mmc@5b020000 { 243 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 244 interrupt-parent = <&gic>; 245 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 246 reg = <0x5b020000 0x10000>; 247 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, 248 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, 249 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; 250 clock-names = "ipg", "per", "ahb"; 251 assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; 252 assigned-clock-rates = <200000000>; 253 power-domains = <&pd IMX_SC_R_SDHC_1>; 254 fsl,tuning-start-tap = <20>; 255 fsl,tuning-step= <2>; 256 status = "disabled"; 257 }; 258 259 usdhc3: mmc@5b030000 { 260 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 261 interrupt-parent = <&gic>; 262 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 263 reg = <0x5b030000 0x10000>; 264 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, 265 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, 266 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; 267 clock-names = "ipg", "per", "ahb"; 268 assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; 269 assigned-clock-rates = <200000000>; 270 power-domains = <&pd IMX_SC_R_SDHC_2>; 271 status = "disabled"; 272 }; 273 274 fec1: ethernet@5b040000 { 275 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 276 reg = <0x5b040000 0x10000>; 277 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, 282 <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, 283 <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, 284 <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; 285 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 286 fsl,num-tx-queues=<3>; 287 fsl,num-rx-queues=<3>; 288 power-domains = <&pd IMX_SC_R_ENET_0>; 289 status = "disabled"; 290 }; 291 292 fec2: ethernet@5b050000 { 293 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 294 reg = <0x5b050000 0x10000>; 295 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, 300 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, 301 <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, 302 <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; 303 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 304 fsl,num-tx-queues=<3>; 305 fsl,num-rx-queues=<3>; 306 power-domains = <&pd IMX_SC_R_ENET_1>; 307 status = "disabled"; 308 }; 309 }; 310 311 lsio_subsys: bus@5d000000 { 312 compatible = "simple-bus"; 313 #address-cells = <1>; 314 #size-cells = <1>; 315 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; 316 317 lsio_lpcg: clock-controller@5d400000 { 318 compatible = "fsl,imx8qxp-lpcg-lsio"; 319 reg = <0x5d400000 0x400000>; 320 #clock-cells = <1>; 321 }; 322 323 lsio_mu0: mailbox@5d1b0000 { 324 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 325 reg = <0x5d1b0000 0x10000>; 326 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 327 #mbox-cells = <0>; 328 status = "disabled"; 329 }; 330 331 lsio_mu1: mailbox@5d1c0000 { 332 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 333 reg = <0x5d1c0000 0x10000>; 334 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 335 #mbox-cells = <2>; 336 }; 337 338 lsio_mu3: mailbox@5d1e0000 { 339 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 340 reg = <0x5d1e0000 0x10000>; 341 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 342 #mbox-cells = <0>; 343 status = "disabled"; 344 }; 345 346 lsio_mu4: mailbox@5d1f0000 { 347 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 348 reg = <0x5d1f0000 0x10000>; 349 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 350 #mbox-cells = <0>; 351 status = "disabled"; 352 }; 353 354 lsio_gpio0: gpio@5d080000 { 355 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 356 reg = <0x5d080000 0x10000>; 357 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 358 gpio-controller; 359 #gpio-cells = <2>; 360 interrupt-controller; 361 #interrupt-cells = <2>; 362 power-domains = <&pd IMX_SC_R_GPIO_0>; 363 }; 364 365 lsio_gpio1: gpio@5d090000 { 366 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 367 reg = <0x5d090000 0x10000>; 368 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 369 gpio-controller; 370 #gpio-cells = <2>; 371 interrupt-controller; 372 #interrupt-cells = <2>; 373 power-domains = <&pd IMX_SC_R_GPIO_1>; 374 }; 375 376 lsio_gpio2: gpio@5d0a0000 { 377 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 378 reg = <0x5d0a0000 0x10000>; 379 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 380 gpio-controller; 381 #gpio-cells = <2>; 382 interrupt-controller; 383 #interrupt-cells = <2>; 384 power-domains = <&pd IMX_SC_R_GPIO_2>; 385 }; 386 387 lsio_gpio3: gpio@5d0b0000 { 388 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 389 reg = <0x5d0b0000 0x10000>; 390 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 391 gpio-controller; 392 #gpio-cells = <2>; 393 interrupt-controller; 394 #interrupt-cells = <2>; 395 power-domains = <&pd IMX_SC_R_GPIO_3>; 396 }; 397 398 lsio_gpio4: gpio@5d0c0000 { 399 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 400 reg = <0x5d0c0000 0x10000>; 401 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 402 gpio-controller; 403 #gpio-cells = <2>; 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 power-domains = <&pd IMX_SC_R_GPIO_4>; 407 }; 408 409 lsio_gpio5: gpio@5d0d0000 { 410 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 411 reg = <0x5d0d0000 0x10000>; 412 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 413 gpio-controller; 414 #gpio-cells = <2>; 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 power-domains = <&pd IMX_SC_R_GPIO_5>; 418 }; 419 420 lsio_gpio6: gpio@5d0e0000 { 421 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 422 reg = <0x5d0e0000 0x10000>; 423 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 424 gpio-controller; 425 #gpio-cells = <2>; 426 interrupt-controller; 427 #interrupt-cells = <2>; 428 power-domains = <&pd IMX_SC_R_GPIO_6>; 429 }; 430 431 lsio_gpio7: gpio@5d0f0000 { 432 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 433 reg = <0x5d0f0000 0x10000>; 434 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 435 gpio-controller; 436 #gpio-cells = <2>; 437 interrupt-controller; 438 #interrupt-cells = <2>; 439 power-domains = <&pd IMX_SC_R_GPIO_7>; 440 }; 441 }; 442}; 443