1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2018 Boundary Devices
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/input/input.h>
9#include "imx8mq.dtsi"
10
11/ {
12	model = "Boundary Devices i.MX8MQ Nitrogen8M";
13	compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq";
14
15	chosen {
16		stdout-path = "serial0:115200n8";
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0x00000000 0x40000000 0 0x80000000>;
22	};
23
24	gpio-keys {
25		compatible = "gpio-keys";
26		pinctrl-names = "default";
27		pinctrl-0 = <&pinctrl_gpio_keys>;
28
29		power {
30			label = "Power Button";
31			gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
32			linux,code = <KEY_POWER>;
33			wakeup-source;
34		};
35	};
36
37	reg_usb_otg_vbus: regulator-usb-otg-vbus {
38		compatible = "regulator-fixed";
39		pinctrl-names = "default";
40		pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
41		regulator-name = "usb_otg_vbus";
42		regulator-min-microvolt = <5000000>;
43		regulator-max-microvolt = <5000000>;
44		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
45		enable-active-high;
46	};
47
48	reg_vref_0v9: regulator-vref-0v9 {
49		compatible = "regulator-fixed";
50		regulator-name = "vref-0v9";
51		regulator-min-microvolt = <900000>;
52		regulator-max-microvolt = <900000>;
53	};
54
55	reg_vref_1v8: regulator-vref-1v8 {
56		compatible = "regulator-fixed";
57		regulator-name = "vref-1v8";
58		regulator-min-microvolt = <1800000>;
59		regulator-max-microvolt = <1800000>;
60	};
61
62	reg_vref_2v5: regulator-vref-2v5 {
63		compatible = "regulator-fixed";
64		regulator-name = "vref-2v5";
65		regulator-min-microvolt = <2500000>;
66		regulator-max-microvolt = <2500000>;
67	};
68
69	reg_vref_3v3: regulator-vref-3v3 {
70		compatible = "regulator-fixed";
71		regulator-name = "vref-3v3";
72		regulator-min-microvolt = <3300000>;
73		regulator-max-microvolt = <3300000>;
74	};
75
76	reg_vref_5v: regulator-vref-5v {
77		compatible = "regulator-fixed";
78		regulator-name = "vref-5v";
79		regulator-min-microvolt = <5000000>;
80		regulator-max-microvolt = <5000000>;
81	};
82};
83
84
85&fec1 {
86	pinctrl-names = "default";
87	pinctrl-0 = <&pinctrl_fec1>;
88	phy-mode = "rgmii-id";
89	phy-handle = <&ethphy0>;
90	fsl,magic-packet;
91	status = "okay";
92
93	mdio {
94		#address-cells = <1>;
95		#size-cells = <0>;
96
97		ethphy0: ethernet-phy@4 {
98			compatible = "ethernet-phy-ieee802.3-c22";
99			reg = <4>;
100			interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
101		};
102	};
103};
104
105&i2c1 {
106	clock-frequency = <400000>;
107	pinctrl-names = "default";
108	pinctrl-0 = <&pinctrl_i2c1>;
109	status = "okay";
110
111	i2cmux@70 {
112		compatible = "nxp,pca9546";
113		pinctrl-names = "default";
114		pinctrl-0 = <&pinctrl_i2c1_pca9546>;
115		reg = <0x70>;
116		reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
117		#address-cells = <1>;
118		#size-cells = <0>;
119
120		i2c1a: i2c1@0 {
121			reg = <0>;
122			#address-cells = <1>;
123			#size-cells = <0>;
124
125			reg_arm_dram: regulator@60 {
126				compatible = "fcs,fan53555";
127				pinctrl-names = "default";
128				pinctrl-0 = <&pinctrl_reg_arm_dram>;
129				reg = <0x60>;
130				regulator-min-microvolt =  <900000>;
131				regulator-max-microvolt = <1000000>;
132				regulator-always-on;
133				vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
134			};
135		};
136
137		i2c1b: i2c1@1 {
138			reg = <1>;
139			#address-cells = <1>;
140			#size-cells = <0>;
141
142			reg_dram_1p1v: regulator@60 {
143				compatible = "fcs,fan53555";
144				pinctrl-names = "default";
145				pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
146				reg = <0x60>;
147				regulator-min-microvolt = <1100000>;
148				regulator-max-microvolt = <1100000>;
149				regulator-always-on;
150				vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
151			};
152		};
153
154		i2c1c: i2c1@2 {
155			reg = <2>;
156			#address-cells = <1>;
157			#size-cells = <0>;
158
159			reg_soc_gpu_vpu: regulator@60 {
160				compatible = "fcs,fan53555";
161				pinctrl-names = "default";
162				pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
163				reg = <0x60>;
164				regulator-min-microvolt =  <900000>;
165				regulator-max-microvolt = <1000000>;
166				regulator-always-on;
167				vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
168			};
169		};
170
171		i2c1d: i2c1@3 {
172			reg = <3>;
173			#address-cells = <1>;
174			#size-cells = <0>;
175
176			rtc@68 {
177				compatible = "microcrystal,rv4162";
178				pinctrl-names = "default";
179				pinctrl-0 = <&pinctrl_i2c1d_rv4162>;
180				reg = <0x68>;
181				interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
182				wakeup-source;
183			};
184		};
185	};
186};
187
188&uart1 { /* console */
189	pinctrl-names = "default";
190	pinctrl-0 = <&pinctrl_uart1>;
191	assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
192	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
193	status = "okay";
194};
195
196&uart2 {
197	pinctrl-names = "default";
198	pinctrl-0 = <&pinctrl_uart2>;
199	assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
200	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
201	status = "okay";
202};
203
204&usb_dwc3_0 {
205	dr_mode = "otg";
206	pinctrl-names = "default";
207	pinctrl-0 = <&pinctrl_usb3_0>;
208	status = "okay";
209};
210
211&usb3_phy0 {
212	vbus-supply = <&reg_usb_otg_vbus>;
213	status = "okay";
214};
215
216&usdhc1 {
217	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
218	assigned-clock-rates = <400000000>;
219	bus-width = <8>;
220	pinctrl-names = "default";
221	pinctrl-0 = <&pinctrl_usdhc1>;
222	non-removable;
223	vmmc-supply = <&reg_vref_1v8>;
224	status = "okay";
225};
226
227&wdog1 {
228	pinctrl-names = "default";
229	pinctrl-0 = <&pinctrl_wdog>;
230	fsl,ext-reset-output;
231	status = "okay";
232};
233
234&iomuxc {
235	pinctrl-names = "default";
236	pinctrl-0 = <&pinctrl_hog>;
237
238	pinctrl_hog: hoggrp {
239		fsl,pins = <
240			/* J17 connector, odd */
241			MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0		0x19	/* Pin 19 */
242			MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1			0x19	/* Pin 21 */
243			MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3		0x19	/* Pin 23 */
244			MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4		0x19	/* Pin 25 */
245			MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5		0x19	/* Pin 27 */
246			MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6		0x19	/* Pin 29 */
247			MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7		0x19	/* Pin 31 */
248			MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8		0x19	/* Pin 33 */
249			MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x19	/* Pin 35 */
250			MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13		0x19	/* Pin 39 */
251			MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14		0x19	/* Pin 41 */
252			MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15		0x19	/* Pin 43 */
253			MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16		0x19	/* Pin 45 */
254			MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17		0x19	/* Pin 47 */
255			MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x19	/* Pin 49 */
256			MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x19	/* Pin 51 */
257
258			/* J17 connector, even */
259			MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28		0x19	/* Pin 44 */
260			MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29		0x19	/* Pin 48 */
261			MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19	/* Pin 50 */
262			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x19	/* Pin 54 */
263			MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x19	/* Pin 56 */
264
265			/* J18 connector, odd */
266			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x19	/* Pin 41 */
267			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5			0x19	/* Pin 43 */
268			MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16		0x19	/* Pin 45 */
269			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11		0x19	/* Pin 47 */
270			MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18		0x19	/* Pin 49 */
271			MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14		0x19	/* Pin 53 */
272
273			/* J18 connector, even */
274			MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0			0x19	/* Pin 32 */
275			MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1		0x19	/* Pin 36 */
276			MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6		0x19	/* Pin 38 */
277			MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7		0x19	/* Pin 40 */
278			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8		0x19	/* Pin 42 */
279			MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9		0x19	/* Pin 44 */
280			MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10		0x19	/* Pin 46 */
281
282			/* J13 Pin 2, WL_WAKE */
283			MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23		0xd6
284			/* J13 Pin 4, WL_IRQ, not needed for Silex */
285			MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21		0xd6
286			/* J13 pin 9, unused */
287			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x19
288			/* J13 Pin 41, BT_CLK_REQ */
289			MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22		0xd6
290			/* J13 Pin 42, BT_HOST_WAKE */
291			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25		0xd6
292
293			/* Clock for both CSI1 and CSI2 */
294			MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2	0x07
295			/* test points */
296			MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4		0xc1	/* TP87 */
297		>;
298	};
299
300	pinctrl_fec1: fec1grp {
301		fsl,pins = <
302			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
303			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
304			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
305			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
306			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
307			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
308			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
309			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
310			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
311			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
312			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
313			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
314			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
315			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
316			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
317			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x59
318		>;
319	};
320
321	pinctrl_gpio_keys: gpio-keysgrp {
322		fsl,pins = <
323			MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
324		>;
325	};
326
327
328	pinctrl_i2c1: i2c1grp {
329		fsl,pins = <
330			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
331			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
332		>;
333	};
334
335	pinctrl_i2c1_pca9546: i2c1-pca9546grp {
336		fsl,pins = <
337			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x49
338		>;
339	};
340
341	pinctrl_i2c1d_rv4162: i2c1d-rv4162grp {
342		fsl,pins = <
343			MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x49
344		>;
345	};
346
347	pinctrl_reg_arm_dram: reg-arm-dramgrp {
348		fsl,pins = <
349			MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24	0x16
350		>;
351	};
352
353	pinctrl_reg_dram_1p1v: reg-dram-1p1vgrp {
354		fsl,pins = <
355			MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11	0x16
356		>;
357	};
358
359	pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpugrp {
360		fsl,pins = <
361			MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20		0x16
362		>;
363	};
364
365	pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {
366		fsl,pins = <
367			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x16
368		>;
369	};
370
371	pinctrl_uart1: uart1grp {
372		fsl,pins = <
373			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x45
374			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x45
375		>;
376	};
377
378	pinctrl_uart2: uart2grp {
379		fsl,pins = <
380			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x45
381			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x45
382		>;
383	};
384
385	pinctrl_usb3_0: usb3-0grp {
386		fsl,pins = <
387			MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x16
388		>;
389	};
390
391	pinctrl_usdhc1: usdhc1grp {
392		fsl,pins = <
393			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
394			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
395			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
396			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
397			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
398			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
399			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
400			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
401			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
402			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
403			MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10		0x41
404		>;
405	};
406
407	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
408		fsl,pins = <
409			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
410			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
411			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
412			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
413			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
414			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
415			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
416			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
417			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
418			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
419		>;
420	};
421
422	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
423		fsl,pins = <
424			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
425			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
426			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
427			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
428			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
429			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
430			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
431			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
432			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
433			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
434		>;
435	};
436
437	pinctrl_wdog: wdoggrp {
438		fsl,pins = <
439		MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
440		>;
441	};
442};
443