1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2018 Boundary Devices
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/input/input.h>
9#include "imx8mq.dtsi"
10
11/ {
12	model = "Boundary Devices i.MX8MQ Nitrogen8M";
13	compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq";
14
15	chosen {
16		stdout-path = "serial0:115200n8";
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0x00000000 0x40000000 0 0x80000000>;
22	};
23
24	gpio-keys {
25		compatible = "gpio-keys";
26		pinctrl-names = "default";
27		pinctrl-0 = <&pinctrl_gpio_keys>;
28
29		power {
30			label = "Power Button";
31			gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
32			linux,code = <KEY_POWER>;
33			wakeup-source;
34		};
35	};
36
37	reg_usb_otg_vbus: regulator-usb-otg-vbus {
38		compatible = "regulator-fixed";
39		pinctrl-names = "default";
40		pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
41		regulator-name = "usb_otg_vbus";
42		regulator-min-microvolt = <5000000>;
43		regulator-max-microvolt = <5000000>;
44		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
45		enable-active-high;
46	};
47
48	reg_vref_0v9: regulator-vref-0v9 {
49		compatible = "regulator-fixed";
50		regulator-name = "vref-0v9";
51		regulator-min-microvolt = <900000>;
52		regulator-max-microvolt = <900000>;
53	};
54
55	reg_vref_1v8: regulator-vref-1v8 {
56		compatible = "regulator-fixed";
57		regulator-name = "vref-1v8";
58		regulator-min-microvolt = <1800000>;
59		regulator-max-microvolt = <1800000>;
60	};
61
62	reg_vref_2v5: regulator-vref-2v5 {
63		compatible = "regulator-fixed";
64		regulator-name = "vref-2v5";
65		regulator-min-microvolt = <2500000>;
66		regulator-max-microvolt = <2500000>;
67	};
68
69	reg_vref_3v3: regulator-vref-3v3 {
70		compatible = "regulator-fixed";
71		regulator-name = "vref-3v3";
72		regulator-min-microvolt = <3300000>;
73		regulator-max-microvolt = <3300000>;
74	};
75
76	reg_vref_5v: regulator-vref-5v {
77		compatible = "regulator-fixed";
78		regulator-name = "vref-5v";
79		regulator-min-microvolt = <5000000>;
80		regulator-max-microvolt = <5000000>;
81	};
82};
83
84
85&fec1 {
86	pinctrl-names = "default";
87	pinctrl-0 = <&pinctrl_fec1>;
88	phy-mode = "rgmii-id";
89	phy-handle = <&ethphy0>;
90	fsl,magic-packet;
91	status = "okay";
92
93	mdio {
94		#address-cells = <1>;
95		#size-cells = <0>;
96
97		ethphy0: ethernet-phy@4 {
98			compatible = "ethernet-phy-ieee802.3-c22";
99			reg = <4>;
100			interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
101		};
102	};
103};
104
105/* Release reset of the USB Host HUB */
106&gpio1 {
107	usb-host-reset-hog {
108		gpio-hog;
109		gpios = <14 GPIO_ACTIVE_HIGH>;
110		output-high;
111	};
112};
113
114&i2c1 {
115	clock-frequency = <400000>;
116	pinctrl-names = "default";
117	pinctrl-0 = <&pinctrl_i2c1>;
118	status = "okay";
119
120	i2cmux@70 {
121		compatible = "nxp,pca9546";
122		pinctrl-names = "default";
123		pinctrl-0 = <&pinctrl_i2c1_pca9546>;
124		reg = <0x70>;
125		reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
126		#address-cells = <1>;
127		#size-cells = <0>;
128
129		i2c1a: i2c1@0 {
130			reg = <0>;
131			#address-cells = <1>;
132			#size-cells = <0>;
133
134			reg_arm_dram: regulator@60 {
135				compatible = "fcs,fan53555";
136				pinctrl-names = "default";
137				pinctrl-0 = <&pinctrl_reg_arm_dram>;
138				reg = <0x60>;
139				regulator-min-microvolt =  <900000>;
140				regulator-max-microvolt = <1000000>;
141				regulator-always-on;
142				vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
143			};
144		};
145
146		i2c1b: i2c1@1 {
147			reg = <1>;
148			#address-cells = <1>;
149			#size-cells = <0>;
150
151			reg_dram_1p1v: regulator@60 {
152				compatible = "fcs,fan53555";
153				pinctrl-names = "default";
154				pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
155				reg = <0x60>;
156				regulator-min-microvolt = <1100000>;
157				regulator-max-microvolt = <1100000>;
158				regulator-always-on;
159				vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
160			};
161		};
162
163		i2c1c: i2c1@2 {
164			reg = <2>;
165			#address-cells = <1>;
166			#size-cells = <0>;
167
168			reg_soc_gpu_vpu: regulator@60 {
169				compatible = "fcs,fan53555";
170				pinctrl-names = "default";
171				pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
172				reg = <0x60>;
173				regulator-min-microvolt =  <900000>;
174				regulator-max-microvolt = <1000000>;
175				regulator-always-on;
176				vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
177			};
178		};
179
180		i2c1d: i2c1@3 {
181			reg = <3>;
182			#address-cells = <1>;
183			#size-cells = <0>;
184
185			rtc@68 {
186				compatible = "microcrystal,rv4162";
187				pinctrl-names = "default";
188				pinctrl-0 = <&pinctrl_i2c1d_rv4162>;
189				reg = <0x68>;
190				interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
191				wakeup-source;
192			};
193		};
194	};
195};
196
197&uart1 { /* console */
198	pinctrl-names = "default";
199	pinctrl-0 = <&pinctrl_uart1>;
200	assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
201	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
202	status = "okay";
203};
204
205&uart2 {
206	pinctrl-names = "default";
207	pinctrl-0 = <&pinctrl_uart2>;
208	assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
209	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
210	status = "okay";
211};
212
213&usb_dwc3_0 {
214	dr_mode = "otg";
215	pinctrl-names = "default";
216	pinctrl-0 = <&pinctrl_usb3_0>;
217	status = "okay";
218};
219
220&usb3_phy0 {
221	vbus-supply = <&reg_usb_otg_vbus>;
222	status = "okay";
223};
224
225&usb_dwc3_1 {
226	dr_mode = "host";
227	status = "okay";
228};
229
230&usb3_phy1 {
231	pinctrl-names = "default";
232	pinctrl-0 = <&pinctrl_usb3_1>;
233	status = "okay";
234};
235
236&usdhc1 {
237	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
238	assigned-clock-rates = <400000000>;
239	bus-width = <8>;
240	pinctrl-names = "default";
241	pinctrl-0 = <&pinctrl_usdhc1>;
242	non-removable;
243	vmmc-supply = <&reg_vref_1v8>;
244	status = "okay";
245};
246
247&wdog1 {
248	pinctrl-names = "default";
249	pinctrl-0 = <&pinctrl_wdog>;
250	fsl,ext-reset-output;
251	status = "okay";
252};
253
254&iomuxc {
255	pinctrl-names = "default";
256	pinctrl-0 = <&pinctrl_hog>;
257
258	pinctrl_hog: hoggrp {
259		fsl,pins = <
260			/* J17 connector, odd */
261			MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0		0x19	/* Pin 19 */
262			MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1			0x19	/* Pin 21 */
263			MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3		0x19	/* Pin 23 */
264			MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4		0x19	/* Pin 25 */
265			MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5		0x19	/* Pin 27 */
266			MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6		0x19	/* Pin 29 */
267			MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7		0x19	/* Pin 31 */
268			MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8		0x19	/* Pin 33 */
269			MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x19	/* Pin 35 */
270			MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13		0x19	/* Pin 39 */
271			MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14		0x19	/* Pin 41 */
272			MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15		0x19	/* Pin 43 */
273			MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16		0x19	/* Pin 45 */
274			MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17		0x19	/* Pin 47 */
275			MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x19	/* Pin 49 */
276			MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x19	/* Pin 51 */
277
278			/* J17 connector, even */
279			MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28		0x19	/* Pin 44 */
280			MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29		0x19	/* Pin 48 */
281			MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19	/* Pin 50 */
282			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x19	/* Pin 54 */
283			MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x19	/* Pin 56 */
284
285			/* J18 connector, odd */
286			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x19	/* Pin 41 */
287			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5			0x19	/* Pin 43 */
288			MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16		0x19	/* Pin 45 */
289			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11		0x19	/* Pin 47 */
290			MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18		0x19	/* Pin 49 */
291			MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14		0x19	/* Pin 53 */
292
293			/* J18 connector, even */
294			MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0			0x19	/* Pin 32 */
295			MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1		0x19	/* Pin 36 */
296			MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6		0x19	/* Pin 38 */
297			MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7		0x19	/* Pin 40 */
298			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8		0x19	/* Pin 42 */
299			MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9		0x19	/* Pin 44 */
300			MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10		0x19	/* Pin 46 */
301
302			/* J13 Pin 2, WL_WAKE */
303			MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23		0xd6
304			/* J13 Pin 4, WL_IRQ, not needed for Silex */
305			MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21		0xd6
306			/* J13 pin 9, unused */
307			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x19
308			/* J13 Pin 41, BT_CLK_REQ */
309			MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22		0xd6
310			/* J13 Pin 42, BT_HOST_WAKE */
311			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25		0xd6
312
313			/* Clock for both CSI1 and CSI2 */
314			MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2	0x07
315			/* test points */
316			MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4		0xc1	/* TP87 */
317		>;
318	};
319
320	pinctrl_fec1: fec1grp {
321		fsl,pins = <
322			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
323			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
324			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
325			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
326			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
327			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
328			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
329			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
330			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
331			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
332			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
333			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
334			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
335			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
336			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
337			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x59
338		>;
339	};
340
341	pinctrl_gpio_keys: gpio-keysgrp {
342		fsl,pins = <
343			MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
344		>;
345	};
346
347
348	pinctrl_i2c1: i2c1grp {
349		fsl,pins = <
350			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
351			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
352		>;
353	};
354
355	pinctrl_i2c1_pca9546: i2c1-pca9546grp {
356		fsl,pins = <
357			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x49
358		>;
359	};
360
361	pinctrl_i2c1d_rv4162: i2c1d-rv4162grp {
362		fsl,pins = <
363			MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x49
364		>;
365	};
366
367	pinctrl_reg_arm_dram: reg-arm-dramgrp {
368		fsl,pins = <
369			MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24	0x16
370		>;
371	};
372
373	pinctrl_reg_dram_1p1v: reg-dram-1p1vgrp {
374		fsl,pins = <
375			MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11	0x16
376		>;
377	};
378
379	pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpugrp {
380		fsl,pins = <
381			MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20		0x16
382		>;
383	};
384
385	pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {
386		fsl,pins = <
387			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x16
388		>;
389	};
390
391	pinctrl_uart1: uart1grp {
392		fsl,pins = <
393			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x45
394			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x45
395		>;
396	};
397
398	pinctrl_uart2: uart2grp {
399		fsl,pins = <
400			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x45
401			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x45
402		>;
403	};
404
405	pinctrl_usb3_0: usb3-0grp {
406		fsl,pins = <
407			MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x16
408		>;
409	};
410
411	pinctrl_usb3_1: usb3-1grp {
412		fsl,pins = <
413			MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x16
414		>;
415	};
416
417	pinctrl_usdhc1: usdhc1grp {
418		fsl,pins = <
419			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
420			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
421			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
422			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
423			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
424			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
425			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
426			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
427			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
428			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
429			MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10		0x41
430		>;
431	};
432
433	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
434		fsl,pins = <
435			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
436			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
437			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
438			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
439			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
440			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
441			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
442			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
443			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
444			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
445		>;
446	};
447
448	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
449		fsl,pins = <
450			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
451			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
452			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
453			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
454			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
455			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
456			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
457			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
458			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
459			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
460		>;
461	};
462
463	pinctrl_wdog: wdoggrp {
464		fsl,pins = <
465		MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
466		>;
467	};
468};
469