1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3/*
4 * Copyright 2019-2021 MNT Research GmbH
5 * Copyright 2021 Lucas Stach <dev@lynxeye.de>
6 */
7
8/dts-v1/;
9
10#include "imx8mq-nitrogen-som.dtsi"
11
12/ {
13	model = "MNT Reform 2";
14	compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
15
16	pcie1_refclk: clock-pcie1-refclk {
17		compatible = "fixed-clock";
18		#clock-cells = <0>;
19		clock-frequency = <100000000>;
20	};
21
22	reg_main_5v: regulator-main-5v {
23		compatible = "regulator-fixed";
24		regulator-name = "5V";
25		regulator-min-microvolt = <5000000>;
26		regulator-max-microvolt = <5000000>;
27	};
28
29	reg_main_3v3: regulator-main-3v3 {
30		compatible = "regulator-fixed";
31		regulator-name = "3V3";
32		regulator-min-microvolt = <3300000>;
33		regulator-max-microvolt = <3300000>;
34	};
35
36	reg_main_usb: regulator-main-usb {
37		compatible = "regulator-fixed";
38		regulator-name = "USB_PWR";
39		regulator-min-microvolt = <5000000>;
40		regulator-max-microvolt = <5000000>;
41		vin-supply = <&reg_main_5v>;
42	};
43};
44
45&fec1 {
46	status = "okay";
47};
48
49&i2c3 {
50	pinctrl-names = "default";
51	pinctrl-0 = <&pinctrl_i2c3>;
52	status = "okay";
53
54	rtc@68 {
55		compatible = "nxp,pcf8523";
56		reg = <0x68>;
57	};
58};
59
60&pcie1 {
61	pinctrl-names = "default";
62	pinctrl-0 = <&pinctrl_pcie1>;
63	reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
64	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
65		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
66		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
67		 <&pcie1_refclk>;
68	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
69	status = "okay";
70};
71
72&reg_1p8v {
73	vin-supply = <&reg_main_5v>;
74};
75
76&reg_snvs {
77	vin-supply = <&reg_main_5v>;
78};
79
80&reg_arm_dram {
81	vin-supply = <&reg_main_5v>;
82};
83
84&reg_dram_1p1v {
85	vin-supply = <&reg_main_5v>;
86};
87
88&reg_soc_gpu_vpu {
89	vin-supply = <&reg_main_5v>;
90};
91
92&snvs_rtc {
93	status = "disabled";
94};
95
96&uart2 {
97	pinctrl-names = "default";
98	pinctrl-0 = <&pinctrl_uart2>;
99	status = "okay";
100};
101
102&usb3_phy0 {
103	vbus-supply = <&reg_main_usb>;
104	status = "okay";
105};
106
107&usb3_phy1 {
108	vbus-supply = <&reg_main_usb>;
109	status = "okay";
110};
111
112&usb_dwc3_0 {
113	dr_mode = "host";
114	status = "okay";
115};
116
117&usb_dwc3_1 {
118	dr_mode = "host";
119	status = "okay";
120};
121
122&usdhc2 {
123	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
124	assigned-clock-rates = <200000000>;
125	pinctrl-names = "default";
126	pinctrl-0 = <&pinctrl_usdhc2>;
127	vqmmc-supply = <&reg_main_3v3>;
128	vmmc-supply = <&reg_main_3v3>;
129	bus-width = <4>;
130	status = "okay";
131};
132
133&iomuxc {
134	pinctrl_i2c3: i2c3grp {
135		fsl,pins = <
136			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f
137			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f
138		>;
139	};
140
141	pinctrl_pcie1: pcie1grp {
142		fsl,pins = <
143			MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23		0x16
144		>;
145	};
146
147	pinctrl_uart2: uart2grp {
148		fsl,pins = <
149			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x45
150			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x45
151		>;
152	};
153
154	pinctrl_usdhc2: usdhc2grp {
155		fsl,pins = <
156			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
157			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
158			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
159			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
160			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
161			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
162		>;
163	};
164};
165