1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 * Copyright 2019-2020 Variscite Ltd.
5 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
6 */
7
8#include "imx8mn.dtsi"
9
10/ {
11	model = "Variscite VAR-SOM-MX8MN module";
12	compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
13
14	chosen {
15		stdout-path = &uart4;
16	};
17
18	memory@40000000 {
19		device_type = "memory";
20		reg = <0x0 0x40000000 0 0x40000000>;
21	};
22
23	reg_eth_phy: regulator-eth-phy {
24		compatible = "regulator-fixed";
25		pinctrl-names = "default";
26		pinctrl-0 = <&pinctrl_reg_eth_phy>;
27		regulator-name = "eth_phy_pwr";
28		regulator-min-microvolt = <3300000>;
29		regulator-max-microvolt = <3300000>;
30		regulator-enable-ramp-delay = <20000>;
31		gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
32		enable-active-high;
33	};
34};
35
36&A53_0 {
37	cpu-supply = <&buck2_reg>;
38};
39
40&A53_1 {
41	cpu-supply = <&buck2_reg>;
42};
43
44&A53_2 {
45	cpu-supply = <&buck2_reg>;
46};
47
48&A53_3 {
49	cpu-supply = <&buck2_reg>;
50};
51
52&ecspi1 {
53	pinctrl-names = "default";
54	pinctrl-0 = <&pinctrl_ecspi1>;
55	cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
56		   <&gpio1  0 GPIO_ACTIVE_LOW>;
57	/delete-property/ dmas;
58	/delete-property/ dma-names;
59	status = "okay";
60
61	/* Resistive touch controller */
62	touchscreen@0 {
63		reg = <0>;
64		compatible = "ti,ads7846";
65		pinctrl-names = "default";
66		pinctrl-0 = <&pinctrl_restouch>;
67		interrupt-parent = <&gpio1>;
68		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
69
70		spi-max-frequency = <1500000>;
71		pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
72
73		ti,x-min = /bits/ 16 <125>;
74		touchscreen-size-x = <4008>;
75		ti,y-min = /bits/ 16 <282>;
76		touchscreen-size-y = <3864>;
77		ti,x-plate-ohms = /bits/ 16 <180>;
78		touchscreen-max-pressure = <255>;
79		touchscreen-average-samples = <10>;
80		ti,debounce-tol = /bits/ 16 <3>;
81		ti,debounce-rep = /bits/ 16 <1>;
82		ti,settle-delay-usec = /bits/ 16 <150>;
83		ti,keep-vref-on;
84		wakeup-source;
85	};
86};
87
88&fec1 {
89	pinctrl-names = "default", "sleep";
90	pinctrl-0 = <&pinctrl_fec1>;
91	pinctrl-1 = <&pinctrl_fec1_sleep>;
92	phy-mode = "rgmii";
93	phy-handle = <&ethphy>;
94	phy-supply = <&reg_eth_phy>;
95	fsl,magic-packet;
96	status = "okay";
97
98	mdio {
99		#address-cells = <1>;
100		#size-cells = <0>;
101
102		ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
103			compatible = "ethernet-phy-ieee802.3-c22";
104			reg = <4>;
105			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
106			reset-assert-us = <10000>;
107			/*
108			 * Deassert delay:
109			 * ADIN1300 requires 5ms.
110			 * AR8033   requires 1ms.
111			 */
112			reset-deassert-us = <20000>;
113		};
114	};
115};
116
117&i2c1 {
118	clock-frequency = <400000>;
119	pinctrl-names = "default";
120	pinctrl-0 = <&pinctrl_i2c1>;
121	status = "okay";
122
123	pmic@4b {
124		compatible = "rohm,bd71847";
125		reg = <0x4b>;
126		pinctrl-names = "default";
127		pinctrl-0 = <&pinctrl_pmic>;
128		interrupt-parent = <&gpio2>;
129		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
130		rohm,reset-snvs-powered;
131
132		regulators {
133			buck1_reg: BUCK1 {
134				regulator-name = "buck1";
135				regulator-min-microvolt = <700000>;
136				regulator-max-microvolt = <1300000>;
137				regulator-boot-on;
138				regulator-always-on;
139				regulator-ramp-delay = <1250>;
140			};
141
142			buck2_reg: BUCK2 {
143				regulator-name = "buck2";
144				regulator-min-microvolt = <700000>;
145				regulator-max-microvolt = <1300000>;
146				regulator-boot-on;
147				regulator-always-on;
148				regulator-ramp-delay = <1250>;
149				rohm,dvs-run-voltage = <1000000>;
150				rohm,dvs-idle-voltage = <900000>;
151			};
152
153			buck3_reg: BUCK3 {
154				regulator-name = "buck3";
155				regulator-min-microvolt = <700000>;
156				regulator-max-microvolt = <1350000>;
157				regulator-boot-on;
158				regulator-always-on;
159			};
160
161			buck4_reg: BUCK4 {
162				regulator-name = "buck4";
163				regulator-min-microvolt = <2600000>;
164				regulator-max-microvolt = <3300000>;
165				regulator-boot-on;
166				regulator-always-on;
167			};
168
169			buck5_reg: BUCK5 {
170				regulator-name = "buck5";
171				regulator-min-microvolt = <1605000>;
172				regulator-max-microvolt = <1995000>;
173				regulator-boot-on;
174				regulator-always-on;
175			};
176
177			buck6_reg: BUCK6 {
178				regulator-name = "buck6";
179				regulator-min-microvolt = <800000>;
180				regulator-max-microvolt = <1400000>;
181				regulator-boot-on;
182				regulator-always-on;
183			};
184
185			ldo1_reg: LDO1 {
186				regulator-name = "ldo1";
187				regulator-min-microvolt = <1600000>;
188				regulator-max-microvolt = <1900000>;
189				regulator-boot-on;
190				regulator-always-on;
191			};
192
193			ldo2_reg: LDO2 {
194				regulator-name = "ldo2";
195				regulator-min-microvolt = <800000>;
196				regulator-max-microvolt = <900000>;
197				regulator-boot-on;
198				regulator-always-on;
199			};
200
201			ldo3_reg: LDO3 {
202				regulator-name = "ldo3";
203				regulator-min-microvolt = <1800000>;
204				regulator-max-microvolt = <3300000>;
205				regulator-boot-on;
206				regulator-always-on;
207			};
208
209			ldo4_reg: LDO4 {
210				regulator-name = "ldo4";
211				regulator-min-microvolt = <900000>;
212				regulator-max-microvolt = <1800000>;
213				regulator-always-on;
214			};
215
216			ldo5_reg: LDO5 {
217				regulator-name = "ldo5";
218				regulator-min-microvolt = <1800000>;
219				regulator-max-microvolt = <1800000>;
220				regulator-always-on;
221			};
222
223			ldo6_reg: LDO6 {
224				regulator-name = "ldo6";
225				regulator-min-microvolt = <900000>;
226				regulator-max-microvolt = <1800000>;
227				regulator-boot-on;
228				regulator-always-on;
229			};
230		};
231	};
232
233	eeprom_som: eeprom@52 {
234		compatible = "atmel,24c04";
235		reg = <0x52>;
236		pagesize = <16>;
237	};
238};
239
240&i2c3 {
241	clock-frequency = <400000>;
242	pinctrl-names = "default";
243	pinctrl-0 = <&pinctrl_i2c3>;
244	status = "okay";
245
246	/* TODO: configure audio, as of now just put a placeholder */
247	wm8904: codec@1a {
248		compatible = "wlf,wm8904";
249		reg = <0x1a>;
250		status = "disabled";
251	};
252};
253
254&snvs_pwrkey {
255	status = "okay";
256};
257
258/* Bluetooth */
259&uart2 {
260	pinctrl-names = "default";
261	pinctrl-0 = <&pinctrl_uart2>;
262	assigned-clocks = <&clk IMX8MN_CLK_UART2>;
263	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
264	uart-has-rtscts;
265	status = "okay";
266};
267
268/* Console */
269&uart4 {
270	pinctrl-names = "default";
271	pinctrl-0 = <&pinctrl_uart4>;
272	status = "okay";
273};
274
275&usbotg1 {
276	dr_mode = "otg";
277	usb-role-switch;
278	status = "okay";
279};
280
281/* WIFI */
282&usdhc1 {
283	#address-cells = <1>;
284	#size-cells = <0>;
285	pinctrl-names = "default", "state_100mhz", "state_200mhz";
286	pinctrl-0 = <&pinctrl_usdhc1>;
287	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
288	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
289	bus-width = <4>;
290	non-removable;
291	keep-power-in-suspend;
292	status = "okay";
293
294	brcmf: bcrmf@1 {
295		reg = <1>;
296		compatible = "brcm,bcm4329-fmac";
297	};
298};
299
300/* SD */
301&usdhc2 {
302	assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
303	assigned-clock-rates = <200000000>;
304	pinctrl-names = "default", "state_100mhz", "state_200mhz";
305	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
306	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
307	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
308	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
309	bus-width = <4>;
310	vmmc-supply = <&reg_usdhc2_vmmc>;
311	status = "okay";
312};
313
314/* eMMC */
315&usdhc3 {
316	assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
317	assigned-clock-rates = <400000000>;
318	pinctrl-names = "default", "state_100mhz", "state_200mhz";
319	pinctrl-0 = <&pinctrl_usdhc3>;
320	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
321	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
322	bus-width = <8>;
323	non-removable;
324	status = "okay";
325};
326
327&wdog1 {
328	pinctrl-names = "default";
329	pinctrl-0 = <&pinctrl_wdog>;
330	fsl,ext-reset-output;
331	status = "okay";
332};
333
334&iomuxc {
335	pinctrl_ecspi1: ecspi1grp {
336		fsl,pins = <
337			MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x13
338			MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x13
339			MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x13
340			MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x13
341			MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x13
342		>;
343	};
344
345	pinctrl_fec1: fec1grp {
346		fsl,pins = <
347			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC			0x3
348			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
349			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
350			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
351			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
352			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
353			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
354			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
355			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
356			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
357			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
358			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
359			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
360			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
361			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x159
362		>;
363	};
364
365	pinctrl_fec1_sleep: fec1sleepgrp {
366		fsl,pins = <
367			MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16		0x120
368			MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17		0x120
369			MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18		0x120
370			MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19		0x120
371			MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20		0x120
372			MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21		0x120
373			MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29		0x120
374			MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28		0x120
375			MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27		0x120
376			MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26		0x120
377			MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23		0x120
378			MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25		0x120
379			MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24		0x120
380			MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x120
381			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x120
382		>;
383	};
384
385	pinctrl_i2c1: i2c1grp {
386		fsl,pins = <
387			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
388			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
389		>;
390	};
391
392	pinctrl_i2c3: i2c3grp {
393		fsl,pins = <
394			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
395			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
396		>;
397	};
398
399	pinctrl_pmic: pmicirqgrp {
400		fsl,pins = <
401			MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8	0x141
402		>;
403	};
404
405	pinctrl_reg_eth_phy: regethphygrp {
406		fsl,pins = <
407			MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9	0x41
408		>;
409	};
410
411	pinctrl_restouch: restouchgrp {
412		fsl,pins = <
413			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x1c0
414		>;
415	};
416
417	pinctrl_uart2: uart2grp {
418		fsl,pins = <
419			MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX	0x140
420			MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX	0x140
421			MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B	0x140
422			MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B	0x140
423		>;
424	};
425
426	pinctrl_uart4: uart4grp {
427		fsl,pins = <
428			MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
429			MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
430		>;
431	};
432
433	pinctrl_usdhc1: usdhc1grp {
434		fsl,pins = <
435			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
436			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
437			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
438			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
439			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
440			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
441		>;
442	};
443
444	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
445		fsl,pins = <
446			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
447			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
448			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
449			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
450			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
451			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
452		>;
453	};
454
455	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
456		fsl,pins = <
457			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
458			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
459			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
460			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
461			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
462			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
463		>;
464	};
465
466	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
467		fsl,pins = <
468			MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x41
469		>;
470	};
471
472	pinctrl_usdhc2: usdhc2grp {
473		fsl,pins = <
474			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
475			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
476			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
477			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
478			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
479			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
480			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
481		>;
482	};
483
484	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
485		fsl,pins = <
486			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
487			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
488			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
489			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
490			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
491			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
492			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
493		>;
494	};
495
496	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
497		fsl,pins = <
498			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
499			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
500			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
501			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
502			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
503			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
504			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
505		>;
506	};
507
508	pinctrl_usdhc3: usdhc3grp {
509		fsl,pins = <
510			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
511			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
512			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
513			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
514			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
515			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
516			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
517			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
518			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
519			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
520			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
521		>;
522	};
523
524	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
525		fsl,pins = <
526			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
527			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
528			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
529			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
530			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
531			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
532			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
533			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
534			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
535			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
536			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
537		>;
538	};
539
540	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
541		fsl,pins = <
542			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
543			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
544			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
545			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
546			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
547			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
548			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
549			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
550			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
551			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
552			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
553		>;
554	};
555
556	pinctrl_wdog: wdoggrp {
557		fsl,pins = <
558			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166
559		>;
560	};
561};
562