xref: /openbmc/linux/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-verdin-dahlia.dtsi (revision 840d9a813c8eaa5c55d86525e374a97ca5023b53)
16a57f224SMarcel Ziswiler// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
26a57f224SMarcel Ziswiler/*
36a57f224SMarcel Ziswiler * Copyright 2022 Toradex
46a57f224SMarcel Ziswiler */
56a57f224SMarcel Ziswiler
66a57f224SMarcel Ziswiler/ {
76a57f224SMarcel Ziswiler	sound_card: sound-card {
86a57f224SMarcel Ziswiler		compatible = "simple-audio-card";
96a57f224SMarcel Ziswiler		simple-audio-card,bitclock-master = <&dailink_master>;
106a57f224SMarcel Ziswiler		simple-audio-card,format = "i2s";
116a57f224SMarcel Ziswiler		simple-audio-card,frame-master = <&dailink_master>;
120d1d030fSEmanuele Ghidoli		simple-audio-card,mclk-fs = <256>;
136a57f224SMarcel Ziswiler		simple-audio-card,name = "imx8mm-wm8904";
146a57f224SMarcel Ziswiler		simple-audio-card,routing =
156a57f224SMarcel Ziswiler			"Headphone Jack", "HPOUTL",
166a57f224SMarcel Ziswiler			"Headphone Jack", "HPOUTR",
176a57f224SMarcel Ziswiler			"IN2L", "Line In Jack",
186a57f224SMarcel Ziswiler			"IN2R", "Line In Jack",
19*3db71cf0SStefan Eichenberger			"Microphone Jack", "MICBIAS",
20*3db71cf0SStefan Eichenberger			"IN1L", "Microphone Jack";
216a57f224SMarcel Ziswiler		simple-audio-card,widgets =
22*3db71cf0SStefan Eichenberger			"Microphone", "Microphone Jack",
236a57f224SMarcel Ziswiler			"Headphone", "Headphone Jack",
246a57f224SMarcel Ziswiler			"Line", "Line In Jack";
256a57f224SMarcel Ziswiler
266a57f224SMarcel Ziswiler		dailink_master: simple-audio-card,codec {
276a57f224SMarcel Ziswiler			clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
286a57f224SMarcel Ziswiler			sound-dai = <&wm8904_1a>;
296a57f224SMarcel Ziswiler		};
306a57f224SMarcel Ziswiler
316a57f224SMarcel Ziswiler		simple-audio-card,cpu {
326a57f224SMarcel Ziswiler			sound-dai = <&sai2>;
336a57f224SMarcel Ziswiler		};
346a57f224SMarcel Ziswiler	};
356a57f224SMarcel Ziswiler};
366a57f224SMarcel Ziswiler
376a57f224SMarcel Ziswiler/* Verdin SPI_1 */
386a57f224SMarcel Ziswiler&ecspi2 {
396a57f224SMarcel Ziswiler	status = "okay";
406a57f224SMarcel Ziswiler};
416a57f224SMarcel Ziswiler
426a57f224SMarcel Ziswiler/* EEPROM on display adapter boards */
436a57f224SMarcel Ziswiler&eeprom_display_adapter {
446a57f224SMarcel Ziswiler	status = "okay";
456a57f224SMarcel Ziswiler};
466a57f224SMarcel Ziswiler
476a57f224SMarcel Ziswiler/* EEPROM on Verdin Development board */
486a57f224SMarcel Ziswiler&eeprom_carrier_board {
496a57f224SMarcel Ziswiler	status = "okay";
506a57f224SMarcel Ziswiler};
516a57f224SMarcel Ziswiler
526a57f224SMarcel Ziswiler&fec1 {
536a57f224SMarcel Ziswiler	status = "okay";
546a57f224SMarcel Ziswiler};
556a57f224SMarcel Ziswiler
566a57f224SMarcel Ziswiler/* Verdin QSPI_1 */
576a57f224SMarcel Ziswiler&flexspi {
586a57f224SMarcel Ziswiler	status = "okay";
596a57f224SMarcel Ziswiler};
606a57f224SMarcel Ziswiler
616a57f224SMarcel Ziswiler/* Current measurement into module VCC */
626a57f224SMarcel Ziswiler&hwmon {
636a57f224SMarcel Ziswiler	status = "okay";
646a57f224SMarcel Ziswiler};
656a57f224SMarcel Ziswiler
666a57f224SMarcel Ziswiler&hwmon_temp {
676a57f224SMarcel Ziswiler	vs-supply = <&reg_1p8v>;
686a57f224SMarcel Ziswiler	status = "okay";
696a57f224SMarcel Ziswiler};
706a57f224SMarcel Ziswiler
716a57f224SMarcel Ziswiler&i2c3 {
726a57f224SMarcel Ziswiler	status = "okay";
736a57f224SMarcel Ziswiler};
746a57f224SMarcel Ziswiler
756a57f224SMarcel Ziswiler/* Verdin I2C_1 */
766a57f224SMarcel Ziswiler&i2c4 {
776a57f224SMarcel Ziswiler	status = "okay";
786a57f224SMarcel Ziswiler
796a57f224SMarcel Ziswiler	/* Audio Codec */
806a57f224SMarcel Ziswiler	wm8904_1a: audio-codec@1a {
816a57f224SMarcel Ziswiler		compatible = "wlf,wm8904";
826a57f224SMarcel Ziswiler		AVDD-supply = <&reg_3p3v>;
836a57f224SMarcel Ziswiler		clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
846a57f224SMarcel Ziswiler		clock-names = "mclk";
856a57f224SMarcel Ziswiler		CPVDD-supply = <&reg_3p3v>;
866a57f224SMarcel Ziswiler		DBVDD-supply = <&reg_3p3v>;
876a57f224SMarcel Ziswiler		DCVDD-supply = <&reg_3p3v>;
886a57f224SMarcel Ziswiler		MICVDD-supply = <&reg_3p3v>;
896a57f224SMarcel Ziswiler		reg = <0x1a>;
906a57f224SMarcel Ziswiler		#sound-dai-cells = <0>;
916a57f224SMarcel Ziswiler	};
926a57f224SMarcel Ziswiler};
936a57f224SMarcel Ziswiler
946a57f224SMarcel Ziswiler/* Verdin PCIE_1 */
956a57f224SMarcel Ziswiler&pcie0 {
966a57f224SMarcel Ziswiler	status = "okay";
976a57f224SMarcel Ziswiler};
986a57f224SMarcel Ziswiler
996a57f224SMarcel Ziswiler&pcie_phy {
1006a57f224SMarcel Ziswiler	status = "okay";
1016a57f224SMarcel Ziswiler};
1026a57f224SMarcel Ziswiler
1036a57f224SMarcel Ziswiler/* Verdin PWM_3_DSI */
1046a57f224SMarcel Ziswiler&pwm1 {
1056a57f224SMarcel Ziswiler	status = "okay";
1066a57f224SMarcel Ziswiler};
1076a57f224SMarcel Ziswiler
1086a57f224SMarcel Ziswiler/* Verdin PWM_1 */
1096a57f224SMarcel Ziswiler&pwm2 {
1106a57f224SMarcel Ziswiler	status = "okay";
1116a57f224SMarcel Ziswiler};
1126a57f224SMarcel Ziswiler
1136a57f224SMarcel Ziswiler/* Verdin PWM_2 */
1146a57f224SMarcel Ziswiler&pwm3 {
1156a57f224SMarcel Ziswiler	status = "okay";
1166a57f224SMarcel Ziswiler};
1176a57f224SMarcel Ziswiler
118473b34b8SMarcel Ziswiler/* Verdin I2S_1 */
1196a57f224SMarcel Ziswiler&sai2 {
1206a57f224SMarcel Ziswiler	status = "okay";
1216a57f224SMarcel Ziswiler};
1226a57f224SMarcel Ziswiler
1236a57f224SMarcel Ziswiler/* Verdin UART_3 */
1246a57f224SMarcel Ziswiler&uart1 {
1256a57f224SMarcel Ziswiler	status = "okay";
1266a57f224SMarcel Ziswiler};
1276a57f224SMarcel Ziswiler
1286a57f224SMarcel Ziswiler/* Verdin UART_1 */
1296a57f224SMarcel Ziswiler&uart2 {
1306a57f224SMarcel Ziswiler	status = "okay";
1316a57f224SMarcel Ziswiler};
1326a57f224SMarcel Ziswiler
1336a57f224SMarcel Ziswiler/* Verdin UART_2 */
1346a57f224SMarcel Ziswiler&uart3 {
1356a57f224SMarcel Ziswiler	status = "okay";
1366a57f224SMarcel Ziswiler};
1376a57f224SMarcel Ziswiler
1386a57f224SMarcel Ziswiler/* Verdin USB_1 */
1396a57f224SMarcel Ziswiler&usbotg1 {
1404763009eSPhilippe Schenker	disable-over-current;
1416a57f224SMarcel Ziswiler	status = "okay";
1426a57f224SMarcel Ziswiler};
1436a57f224SMarcel Ziswiler
1446a57f224SMarcel Ziswiler/* Verdin USB_2 */
1456a57f224SMarcel Ziswiler&usbotg2 {
1464763009eSPhilippe Schenker	disable-over-current;
1476a57f224SMarcel Ziswiler	status = "okay";
1486a57f224SMarcel Ziswiler};
1496a57f224SMarcel Ziswiler
1506a57f224SMarcel Ziswiler/* Verdin SD_1 */
1516a57f224SMarcel Ziswiler&usdhc2 {
1526a57f224SMarcel Ziswiler	status = "okay";
1536a57f224SMarcel Ziswiler};
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