1*21480ffdSJagan Teki// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*21480ffdSJagan Teki/* 3*21480ffdSJagan Teki * Copyright (c) 2019 NXP 4*21480ffdSJagan Teki * Copyright (c) 2019 Engicam srl 5*21480ffdSJagan Teki * Copyright (c) 2020 Amarula Solutions(India) 6*21480ffdSJagan Teki */ 7*21480ffdSJagan Teki 8*21480ffdSJagan Teki/dts-v1/; 9*21480ffdSJagan Teki#include "imx8mm.dtsi" 10*21480ffdSJagan Teki#include "imx8mm-icore-mx8mm.dtsi" 11*21480ffdSJagan Teki 12*21480ffdSJagan Teki/ { 13*21480ffdSJagan Teki model = "Engicam i.Core MX8M Mini C.TOUCH 2.0"; 14*21480ffdSJagan Teki compatible = "engicam,icore-mx8mm-ctouch2", "engicam,icore-mx8mm", 15*21480ffdSJagan Teki "fsl,imx8mm"; 16*21480ffdSJagan Teki 17*21480ffdSJagan Teki chosen { 18*21480ffdSJagan Teki stdout-path = &uart2; 19*21480ffdSJagan Teki }; 20*21480ffdSJagan Teki}; 21*21480ffdSJagan Teki 22*21480ffdSJagan Teki&fec1 { 23*21480ffdSJagan Teki status = "okay"; 24*21480ffdSJagan Teki}; 25*21480ffdSJagan Teki 26*21480ffdSJagan Teki&i2c2 { 27*21480ffdSJagan Teki clock-frequency = <400000>; 28*21480ffdSJagan Teki pinctrl-names = "default"; 29*21480ffdSJagan Teki pinctrl-0 = <&pinctrl_i2c2>; 30*21480ffdSJagan Teki status = "okay"; 31*21480ffdSJagan Teki}; 32*21480ffdSJagan Teki 33*21480ffdSJagan Teki&i2c4 { 34*21480ffdSJagan Teki clock-frequency = <100000>; 35*21480ffdSJagan Teki pinctrl-names = "default"; 36*21480ffdSJagan Teki pinctrl-0 = <&pinctrl_i2c4>; 37*21480ffdSJagan Teki status = "okay"; 38*21480ffdSJagan Teki}; 39*21480ffdSJagan Teki 40*21480ffdSJagan Teki&iomuxc { 41*21480ffdSJagan Teki pinctrl_i2c2: i2c2grp { 42*21480ffdSJagan Teki fsl,pins = < 43*21480ffdSJagan Teki MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 44*21480ffdSJagan Teki MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 45*21480ffdSJagan Teki >; 46*21480ffdSJagan Teki }; 47*21480ffdSJagan Teki 48*21480ffdSJagan Teki pinctrl_i2c4: i2c4grp { 49*21480ffdSJagan Teki fsl,pins = < 50*21480ffdSJagan Teki MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 51*21480ffdSJagan Teki MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 52*21480ffdSJagan Teki >; 53*21480ffdSJagan Teki }; 54*21480ffdSJagan Teki 55*21480ffdSJagan Teki pinctrl_uart2: uart2grp { 56*21480ffdSJagan Teki fsl,pins = < 57*21480ffdSJagan Teki MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 58*21480ffdSJagan Teki MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 59*21480ffdSJagan Teki >; 60*21480ffdSJagan Teki }; 61*21480ffdSJagan Teki 62*21480ffdSJagan Teki pinctrl_usdhc1_gpio: usdhc1gpiogrp { 63*21480ffdSJagan Teki fsl,pins = < 64*21480ffdSJagan Teki MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41 65*21480ffdSJagan Teki >; 66*21480ffdSJagan Teki }; 67*21480ffdSJagan Teki 68*21480ffdSJagan Teki pinctrl_usdhc1: usdhc1grp { 69*21480ffdSJagan Teki fsl,pins = < 70*21480ffdSJagan Teki MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 71*21480ffdSJagan Teki MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 72*21480ffdSJagan Teki MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 73*21480ffdSJagan Teki MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 74*21480ffdSJagan Teki MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 75*21480ffdSJagan Teki MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 76*21480ffdSJagan Teki >; 77*21480ffdSJagan Teki }; 78*21480ffdSJagan Teki}; 79*21480ffdSJagan Teki 80*21480ffdSJagan Teki&uart2 { 81*21480ffdSJagan Teki pinctrl-names = "default"; 82*21480ffdSJagan Teki pinctrl-0 = <&pinctrl_uart2>; 83*21480ffdSJagan Teki status = "okay"; 84*21480ffdSJagan Teki}; 85*21480ffdSJagan Teki 86*21480ffdSJagan Teki/* SD */ 87*21480ffdSJagan Teki&usdhc1 { 88*21480ffdSJagan Teki pinctrl-names = "default"; 89*21480ffdSJagan Teki pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; 90*21480ffdSJagan Teki cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; 91*21480ffdSJagan Teki max-frequency = <50000000>; 92*21480ffdSJagan Teki bus-width = <4>; 93*21480ffdSJagan Teki no-1-8-v; 94*21480ffdSJagan Teki keep-power-in-suspend; 95*21480ffdSJagan Teki status = "okay"; 96*21480ffdSJagan Teki}; 97