1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1043A family SoC. 4 * 5 * Copyright 2014-2015 Freescale Semiconductor, Inc. 6 * Copyright 2018, 2020 NXP 7 * 8 * Mingkai Hu <Mingkai.hu@freescale.com> 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/thermal/thermal.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/gpio/gpio.h> 15 16/ { 17 compatible = "fsl,ls1043a"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 crypto = &crypto; 24 fman0 = &fman0; 25 ethernet0 = &enet0; 26 ethernet1 = &enet1; 27 ethernet2 = &enet2; 28 ethernet3 = &enet3; 29 ethernet4 = &enet4; 30 ethernet5 = &enet5; 31 ethernet6 = &enet6; 32 rtc1 = &ftm_alarm0; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 /* 40 * We expect the enable-method for cpu's to be "psci", but this 41 * is dependent on the SoC FW, which will fill this in. 42 * 43 * Currently supported enable-method is psci v0.2 44 */ 45 cpu0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53"; 48 reg = <0x0>; 49 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 50 next-level-cache = <&l2>; 51 cpu-idle-states = <&CPU_PH20>; 52 #cooling-cells = <2>; 53 }; 54 55 cpu1: cpu@1 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 reg = <0x1>; 59 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 60 next-level-cache = <&l2>; 61 cpu-idle-states = <&CPU_PH20>; 62 #cooling-cells = <2>; 63 }; 64 65 cpu2: cpu@2 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53"; 68 reg = <0x2>; 69 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 70 next-level-cache = <&l2>; 71 cpu-idle-states = <&CPU_PH20>; 72 #cooling-cells = <2>; 73 }; 74 75 cpu3: cpu@3 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a53"; 78 reg = <0x3>; 79 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 80 next-level-cache = <&l2>; 81 cpu-idle-states = <&CPU_PH20>; 82 #cooling-cells = <2>; 83 }; 84 85 l2: l2-cache { 86 compatible = "cache"; 87 cache-level = <2>; 88 cache-unified; 89 }; 90 }; 91 92 idle-states { 93 /* 94 * PSCI node is not added default, U-boot will add missing 95 * parts if it determines to use PSCI. 96 */ 97 entry-method = "psci"; 98 99 CPU_PH20: cpu-ph20 { 100 compatible = "arm,idle-state"; 101 idle-state-name = "PH20"; 102 arm,psci-suspend-param = <0x0>; 103 entry-latency-us = <1000>; 104 exit-latency-us = <1000>; 105 min-residency-us = <3000>; 106 }; 107 }; 108 109 memory@80000000 { 110 device_type = "memory"; 111 reg = <0x0 0x80000000 0 0x80000000>; 112 /* DRAM space 1, size: 2GiB DRAM */ 113 }; 114 115 reserved-memory { 116 #address-cells = <2>; 117 #size-cells = <2>; 118 ranges; 119 120 bman_fbpr: bman-fbpr { 121 compatible = "shared-dma-pool"; 122 size = <0 0x1000000>; 123 alignment = <0 0x1000000>; 124 no-map; 125 }; 126 127 qman_fqd: qman-fqd { 128 compatible = "shared-dma-pool"; 129 size = <0 0x400000>; 130 alignment = <0 0x400000>; 131 no-map; 132 }; 133 134 qman_pfdr: qman-pfdr { 135 compatible = "shared-dma-pool"; 136 size = <0 0x2000000>; 137 alignment = <0 0x2000000>; 138 no-map; 139 }; 140 }; 141 142 sysclk: sysclk { 143 compatible = "fixed-clock"; 144 #clock-cells = <0>; 145 clock-frequency = <100000000>; 146 clock-output-names = "sysclk"; 147 }; 148 149 reboot { 150 compatible = "syscon-reboot"; 151 regmap = <&dcfg>; 152 offset = <0xb0>; 153 mask = <0x02>; 154 }; 155 156 thermal-zones { 157 ddr-controller { 158 polling-delay-passive = <1000>; 159 polling-delay = <5000>; 160 thermal-sensors = <&tmu 0>; 161 162 trips { 163 ddr-ctrler-alert { 164 temperature = <85000>; 165 hysteresis = <2000>; 166 type = "passive"; 167 }; 168 169 ddr-ctrler-crit { 170 temperature = <95000>; 171 hysteresis = <2000>; 172 type = "critical"; 173 }; 174 }; 175 }; 176 177 serdes { 178 polling-delay-passive = <1000>; 179 polling-delay = <5000>; 180 thermal-sensors = <&tmu 1>; 181 182 trips { 183 serdes-alert { 184 temperature = <85000>; 185 hysteresis = <2000>; 186 type = "passive"; 187 }; 188 189 serdes-crit { 190 temperature = <95000>; 191 hysteresis = <2000>; 192 type = "critical"; 193 }; 194 }; 195 }; 196 197 fman { 198 polling-delay-passive = <1000>; 199 polling-delay = <5000>; 200 thermal-sensors = <&tmu 2>; 201 202 trips { 203 fman-alert { 204 temperature = <85000>; 205 hysteresis = <2000>; 206 type = "passive"; 207 }; 208 209 fman-crit { 210 temperature = <95000>; 211 hysteresis = <2000>; 212 type = "critical"; 213 }; 214 }; 215 }; 216 217 core-cluster { 218 polling-delay-passive = <1000>; 219 polling-delay = <5000>; 220 thermal-sensors = <&tmu 3>; 221 222 trips { 223 core_cluster_alert: core-cluster-alert { 224 temperature = <85000>; 225 hysteresis = <2000>; 226 type = "passive"; 227 }; 228 229 core_cluster_crit: core-cluster-crit { 230 temperature = <95000>; 231 hysteresis = <2000>; 232 type = "critical"; 233 }; 234 }; 235 236 cooling-maps { 237 map0 { 238 trip = <&core_cluster_alert>; 239 cooling-device = 240 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 241 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 242 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 243 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 244 }; 245 }; 246 }; 247 248 sec { 249 polling-delay-passive = <1000>; 250 polling-delay = <5000>; 251 thermal-sensors = <&tmu 4>; 252 253 trips { 254 sec-alert { 255 temperature = <85000>; 256 hysteresis = <2000>; 257 type = "passive"; 258 }; 259 260 sec-crit { 261 temperature = <95000>; 262 hysteresis = <2000>; 263 type = "critical"; 264 }; 265 }; 266 }; 267 }; 268 269 timer { 270 compatible = "arm,armv8-timer"; 271 interrupts = <1 13 0xf08>, /* Physical Secure PPI */ 272 <1 14 0xf08>, /* Physical Non-Secure PPI */ 273 <1 11 0xf08>, /* Virtual PPI */ 274 <1 10 0xf08>; /* Hypervisor PPI */ 275 fsl,erratum-a008585; 276 }; 277 278 pmu { 279 compatible = "arm,armv8-pmuv3"; 280 interrupts = <0 106 0x4>, 281 <0 107 0x4>, 282 <0 95 0x4>, 283 <0 97 0x4>; 284 interrupt-affinity = <&cpu0>, 285 <&cpu1>, 286 <&cpu2>, 287 <&cpu3>; 288 }; 289 290 gic: interrupt-controller@1400000 { 291 compatible = "arm,gic-400"; 292 #interrupt-cells = <3>; 293 interrupt-controller; 294 reg = <0x0 0x1401000 0 0x1000>, /* GICD */ 295 <0x0 0x1402000 0 0x2000>, /* GICC */ 296 <0x0 0x1404000 0 0x2000>, /* GICH */ 297 <0x0 0x1406000 0 0x2000>; /* GICV */ 298 interrupts = <1 9 0xf08>; 299 }; 300 301 soc: soc { 302 compatible = "simple-bus"; 303 #address-cells = <2>; 304 #size-cells = <2>; 305 ranges; 306 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 307 dma-coherent; 308 309 clockgen: clocking@1ee1000 { 310 compatible = "fsl,ls1043a-clockgen"; 311 reg = <0x0 0x1ee1000 0x0 0x1000>; 312 #clock-cells = <2>; 313 clocks = <&sysclk>; 314 }; 315 316 scfg: scfg@1570000 { 317 compatible = "fsl,ls1043a-scfg", "syscon"; 318 reg = <0x0 0x1570000 0x0 0x10000>; 319 big-endian; 320 #address-cells = <1>; 321 #size-cells = <1>; 322 ranges = <0x0 0x0 0x1570000 0x10000>; 323 324 extirq: interrupt-controller@1ac { 325 compatible = "fsl,ls1043a-extirq"; 326 #interrupt-cells = <2>; 327 #address-cells = <0>; 328 interrupt-controller; 329 reg = <0x1ac 4>; 330 interrupt-map = 331 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 332 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 333 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 334 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 335 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 336 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 337 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 338 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 339 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 340 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 341 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 342 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 343 interrupt-map-mask = <0xf 0x0>; 344 }; 345 }; 346 347 crypto: crypto@1700000 { 348 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 349 "fsl,sec-v4.0"; 350 fsl,sec-era = <3>; 351 #address-cells = <1>; 352 #size-cells = <1>; 353 ranges = <0x0 0x00 0x1700000 0x100000>; 354 reg = <0x00 0x1700000 0x0 0x100000>; 355 interrupts = <0 75 0x4>; 356 dma-coherent; 357 358 sec_jr0: jr@10000 { 359 compatible = "fsl,sec-v5.4-job-ring", 360 "fsl,sec-v5.0-job-ring", 361 "fsl,sec-v4.0-job-ring"; 362 reg = <0x10000 0x10000>; 363 interrupts = <0 71 0x4>; 364 }; 365 366 sec_jr1: jr@20000 { 367 compatible = "fsl,sec-v5.4-job-ring", 368 "fsl,sec-v5.0-job-ring", 369 "fsl,sec-v4.0-job-ring"; 370 reg = <0x20000 0x10000>; 371 interrupts = <0 72 0x4>; 372 }; 373 374 sec_jr2: jr@30000 { 375 compatible = "fsl,sec-v5.4-job-ring", 376 "fsl,sec-v5.0-job-ring", 377 "fsl,sec-v4.0-job-ring"; 378 reg = <0x30000 0x10000>; 379 interrupts = <0 73 0x4>; 380 }; 381 382 sec_jr3: jr@40000 { 383 compatible = "fsl,sec-v5.4-job-ring", 384 "fsl,sec-v5.0-job-ring", 385 "fsl,sec-v4.0-job-ring"; 386 reg = <0x40000 0x10000>; 387 interrupts = <0 74 0x4>; 388 }; 389 }; 390 391 sfp: efuse@1e80000 { 392 compatible = "fsl,ls1021a-sfp"; 393 reg = <0x0 0x1e80000 0x0 0x10000>; 394 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 395 QORIQ_CLK_PLL_DIV(4)>; 396 clock-names = "sfp"; 397 }; 398 399 dcfg: dcfg@1ee0000 { 400 compatible = "fsl,ls1043a-dcfg", "syscon"; 401 reg = <0x0 0x1ee0000 0x0 0x1000>; 402 big-endian; 403 }; 404 405 ifc: memory-controller@1530000 { 406 compatible = "fsl,ifc"; 407 reg = <0x0 0x1530000 0x0 0x10000>; 408 interrupts = <0 43 0x4>; 409 }; 410 411 qspi: spi@1550000 { 412 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi"; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 reg = <0x0 0x1550000 0x0 0x10000>, 416 <0x0 0x40000000 0x0 0x4000000>; 417 reg-names = "QuadSPI", "QuadSPI-memory"; 418 interrupts = <0 99 0x4>; 419 clock-names = "qspi_en", "qspi"; 420 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 421 QORIQ_CLK_PLL_DIV(1)>, 422 <&clockgen QORIQ_CLK_PLATFORM_PLL 423 QORIQ_CLK_PLL_DIV(1)>; 424 status = "disabled"; 425 }; 426 427 esdhc: esdhc@1560000 { 428 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; 429 reg = <0x0 0x1560000 0x0 0x10000>; 430 interrupts = <0 62 0x4>; 431 clock-frequency = <0>; 432 voltage-ranges = <1800 1800 3300 3300>; 433 sdhci,auto-cmd12; 434 big-endian; 435 bus-width = <4>; 436 }; 437 438 ddr: memory-controller@1080000 { 439 compatible = "fsl,qoriq-memory-controller"; 440 reg = <0x0 0x1080000 0x0 0x1000>; 441 interrupts = <0 144 0x4>; 442 big-endian; 443 }; 444 445 tmu: tmu@1f00000 { 446 compatible = "fsl,qoriq-tmu"; 447 reg = <0x0 0x1f00000 0x0 0x10000>; 448 interrupts = <0 33 0x4>; 449 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 450 fsl,tmu-calibration = <0x00000000 0x00000023 451 0x00000001 0x0000002a 452 0x00000002 0x00000031 453 0x00000003 0x00000037 454 0x00000004 0x0000003e 455 0x00000005 0x00000044 456 0x00000006 0x0000004b 457 0x00000007 0x00000051 458 0x00000008 0x00000058 459 0x00000009 0x0000005e 460 0x0000000a 0x00000065 461 0x0000000b 0x0000006b 462 463 0x00010000 0x00000023 464 0x00010001 0x0000002b 465 0x00010002 0x00000033 466 0x00010003 0x0000003b 467 0x00010004 0x00000043 468 0x00010005 0x0000004b 469 0x00010006 0x00000054 470 0x00010007 0x0000005c 471 0x00010008 0x00000064 472 0x00010009 0x0000006c 473 474 0x00020000 0x00000021 475 0x00020001 0x0000002c 476 0x00020002 0x00000036 477 0x00020003 0x00000040 478 0x00020004 0x0000004b 479 0x00020005 0x00000055 480 0x00020006 0x0000005f 481 482 0x00030000 0x00000013 483 0x00030001 0x0000001d 484 0x00030002 0x00000028 485 0x00030003 0x00000032 486 0x00030004 0x0000003d 487 0x00030005 0x00000047 488 0x00030006 0x00000052 489 0x00030007 0x0000005c>; 490 #thermal-sensor-cells = <1>; 491 }; 492 493 qman: qman@1880000 { 494 compatible = "fsl,qman"; 495 reg = <0x0 0x1880000 0x0 0x10000>; 496 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 497 memory-region = <&qman_fqd &qman_pfdr>; 498 }; 499 500 bman: bman@1890000 { 501 compatible = "fsl,bman"; 502 reg = <0x0 0x1890000 0x0 0x10000>; 503 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 504 memory-region = <&bman_fbpr>; 505 }; 506 507 bportals: bman-portals@508000000 { 508 ranges = <0x0 0x5 0x08000000 0x8000000>; 509 }; 510 511 qportals: qman-portals@500000000 { 512 ranges = <0x0 0x5 0x00000000 0x8000000>; 513 }; 514 515 dspi0: spi@2100000 { 516 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 reg = <0x0 0x2100000 0x0 0x10000>; 520 interrupts = <0 64 0x4>; 521 clock-names = "dspi"; 522 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 523 QORIQ_CLK_PLL_DIV(1)>; 524 spi-num-chipselects = <5>; 525 big-endian; 526 status = "disabled"; 527 }; 528 529 dspi1: spi@2110000 { 530 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 reg = <0x0 0x2110000 0x0 0x10000>; 534 interrupts = <0 65 0x4>; 535 clock-names = "dspi"; 536 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 537 QORIQ_CLK_PLL_DIV(1)>; 538 spi-num-chipselects = <5>; 539 big-endian; 540 status = "disabled"; 541 }; 542 543 i2c0: i2c@2180000 { 544 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 reg = <0x0 0x2180000 0x0 0x10000>; 548 interrupts = <0 56 0x4>; 549 clock-names = "i2c"; 550 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 551 QORIQ_CLK_PLL_DIV(1)>; 552 dmas = <&edma0 1 38>, 553 <&edma0 1 39>; 554 dma-names = "rx", "tx"; 555 status = "disabled"; 556 }; 557 558 i2c1: i2c@2190000 { 559 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 reg = <0x0 0x2190000 0x0 0x10000>; 563 interrupts = <0 57 0x4>; 564 clock-names = "i2c"; 565 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 566 QORIQ_CLK_PLL_DIV(1)>; 567 scl-gpios = <&gpio4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 568 status = "disabled"; 569 }; 570 571 i2c2: i2c@21a0000 { 572 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 reg = <0x0 0x21a0000 0x0 0x10000>; 576 interrupts = <0 58 0x4>; 577 clock-names = "i2c"; 578 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 579 QORIQ_CLK_PLL_DIV(1)>; 580 scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 581 status = "disabled"; 582 }; 583 584 i2c3: i2c@21b0000 { 585 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 reg = <0x0 0x21b0000 0x0 0x10000>; 589 interrupts = <0 59 0x4>; 590 clock-names = "i2c"; 591 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 592 QORIQ_CLK_PLL_DIV(1)>; 593 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 594 status = "disabled"; 595 }; 596 597 duart0: serial@21c0500 { 598 compatible = "fsl,ns16550", "ns16550a"; 599 reg = <0x00 0x21c0500 0x0 0x100>; 600 interrupts = <0 54 0x4>; 601 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 602 QORIQ_CLK_PLL_DIV(1)>; 603 }; 604 605 duart1: serial@21c0600 { 606 compatible = "fsl,ns16550", "ns16550a"; 607 reg = <0x00 0x21c0600 0x0 0x100>; 608 interrupts = <0 54 0x4>; 609 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 610 QORIQ_CLK_PLL_DIV(1)>; 611 }; 612 613 duart2: serial@21d0500 { 614 compatible = "fsl,ns16550", "ns16550a"; 615 reg = <0x0 0x21d0500 0x0 0x100>; 616 interrupts = <0 55 0x4>; 617 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 618 QORIQ_CLK_PLL_DIV(1)>; 619 }; 620 621 duart3: serial@21d0600 { 622 compatible = "fsl,ns16550", "ns16550a"; 623 reg = <0x0 0x21d0600 0x0 0x100>; 624 interrupts = <0 55 0x4>; 625 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 626 QORIQ_CLK_PLL_DIV(1)>; 627 }; 628 629 gpio1: gpio@2300000 { 630 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 631 reg = <0x0 0x2300000 0x0 0x10000>; 632 interrupts = <0 66 0x4>; 633 gpio-controller; 634 #gpio-cells = <2>; 635 interrupt-controller; 636 #interrupt-cells = <2>; 637 }; 638 639 gpio2: gpio@2310000 { 640 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 641 reg = <0x0 0x2310000 0x0 0x10000>; 642 interrupts = <0 67 0x4>; 643 gpio-controller; 644 #gpio-cells = <2>; 645 interrupt-controller; 646 #interrupt-cells = <2>; 647 }; 648 649 gpio3: gpio@2320000 { 650 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 651 reg = <0x0 0x2320000 0x0 0x10000>; 652 interrupts = <0 68 0x4>; 653 gpio-controller; 654 #gpio-cells = <2>; 655 interrupt-controller; 656 #interrupt-cells = <2>; 657 }; 658 659 gpio4: gpio@2330000 { 660 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 661 reg = <0x0 0x2330000 0x0 0x10000>; 662 interrupts = <0 134 0x4>; 663 gpio-controller; 664 #gpio-cells = <2>; 665 interrupt-controller; 666 #interrupt-cells = <2>; 667 }; 668 669 uqe: uqe@2400000 { 670 #address-cells = <1>; 671 #size-cells = <1>; 672 compatible = "fsl,qe", "simple-bus"; 673 ranges = <0x0 0x0 0x2400000 0x40000>; 674 reg = <0x0 0x2400000 0x0 0x480>; 675 brg-frequency = <100000000>; 676 bus-frequency = <200000000>; 677 fsl,qe-num-riscs = <1>; 678 fsl,qe-num-snums = <28>; 679 680 qeic: qeic@80 { 681 compatible = "fsl,qe-ic"; 682 reg = <0x80 0x80>; 683 #address-cells = <0>; 684 interrupt-controller; 685 #interrupt-cells = <1>; 686 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 688 }; 689 690 si1: si@700 { 691 #address-cells = <1>; 692 #size-cells = <0>; 693 compatible = "fsl,ls1043-qe-si", 694 "fsl,t1040-qe-si"; 695 reg = <0x700 0x80>; 696 }; 697 698 siram1: siram@1000 { 699 #address-cells = <1>; 700 #size-cells = <1>; 701 compatible = "fsl,ls1043-qe-siram", 702 "fsl,t1040-qe-siram"; 703 reg = <0x1000 0x800>; 704 }; 705 706 ucc@2000 { 707 cell-index = <1>; 708 reg = <0x2000 0x200>; 709 interrupts = <32>; 710 interrupt-parent = <&qeic>; 711 }; 712 713 ucc@2200 { 714 cell-index = <3>; 715 reg = <0x2200 0x200>; 716 interrupts = <34>; 717 interrupt-parent = <&qeic>; 718 }; 719 720 muram@10000 { 721 #address-cells = <1>; 722 #size-cells = <1>; 723 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 724 ranges = <0x0 0x10000 0x6000>; 725 726 data-only@0 { 727 compatible = "fsl,qe-muram-data", 728 "fsl,cpm-muram-data"; 729 reg = <0x0 0x6000>; 730 }; 731 }; 732 }; 733 734 lpuart0: serial@2950000 { 735 compatible = "fsl,ls1021a-lpuart"; 736 reg = <0x0 0x2950000 0x0 0x1000>; 737 interrupts = <0 48 0x4>; 738 clocks = <&clockgen QORIQ_CLK_SYSCLK 0>; 739 clock-names = "ipg"; 740 status = "disabled"; 741 }; 742 743 lpuart1: serial@2960000 { 744 compatible = "fsl,ls1021a-lpuart"; 745 reg = <0x0 0x2960000 0x0 0x1000>; 746 interrupts = <0 49 0x4>; 747 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 748 QORIQ_CLK_PLL_DIV(1)>; 749 clock-names = "ipg"; 750 status = "disabled"; 751 }; 752 753 lpuart2: serial@2970000 { 754 compatible = "fsl,ls1021a-lpuart"; 755 reg = <0x0 0x2970000 0x0 0x1000>; 756 interrupts = <0 50 0x4>; 757 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 758 QORIQ_CLK_PLL_DIV(1)>; 759 clock-names = "ipg"; 760 status = "disabled"; 761 }; 762 763 lpuart3: serial@2980000 { 764 compatible = "fsl,ls1021a-lpuart"; 765 reg = <0x0 0x2980000 0x0 0x1000>; 766 interrupts = <0 51 0x4>; 767 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 768 QORIQ_CLK_PLL_DIV(1)>; 769 clock-names = "ipg"; 770 status = "disabled"; 771 }; 772 773 lpuart4: serial@2990000 { 774 compatible = "fsl,ls1021a-lpuart"; 775 reg = <0x0 0x2990000 0x0 0x1000>; 776 interrupts = <0 52 0x4>; 777 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 778 QORIQ_CLK_PLL_DIV(1)>; 779 clock-names = "ipg"; 780 status = "disabled"; 781 }; 782 783 lpuart5: serial@29a0000 { 784 compatible = "fsl,ls1021a-lpuart"; 785 reg = <0x0 0x29a0000 0x0 0x1000>; 786 interrupts = <0 53 0x4>; 787 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 788 QORIQ_CLK_PLL_DIV(1)>; 789 clock-names = "ipg"; 790 status = "disabled"; 791 }; 792 793 wdog0: watchdog@2ad0000 { 794 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; 795 reg = <0x0 0x2ad0000 0x0 0x10000>; 796 interrupts = <0 83 0x4>; 797 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 798 QORIQ_CLK_PLL_DIV(1)>; 799 clock-names = "wdog"; 800 big-endian; 801 }; 802 803 edma0: dma-controller@2c00000 { 804 #dma-cells = <2>; 805 compatible = "fsl,vf610-edma"; 806 reg = <0x0 0x2c00000 0x0 0x10000>, 807 <0x0 0x2c10000 0x0 0x10000>, 808 <0x0 0x2c20000 0x0 0x10000>; 809 interrupts = <0 103 0x4>, 810 <0 103 0x4>; 811 interrupt-names = "edma-tx", "edma-err"; 812 dma-channels = <32>; 813 big-endian; 814 clock-names = "dmamux0", "dmamux1"; 815 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 816 QORIQ_CLK_PLL_DIV(1)>, 817 <&clockgen QORIQ_CLK_PLATFORM_PLL 818 QORIQ_CLK_PLL_DIV(1)>; 819 }; 820 821 aux_bus: aux_bus { 822 #address-cells = <2>; 823 #size-cells = <2>; 824 compatible = "simple-bus"; 825 ranges; 826 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; 827 828 usb0: usb@2f00000 { 829 compatible = "snps,dwc3"; 830 reg = <0x0 0x2f00000 0x0 0x10000>; 831 interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>; 832 dr_mode = "host"; 833 snps,quirk-frame-length-adjustment = <0x20>; 834 snps,dis_rxdet_inp3_quirk; 835 usb3-lpm-capable; 836 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 837 status = "disabled"; 838 }; 839 840 usb1: usb@3000000 { 841 compatible = "snps,dwc3"; 842 reg = <0x0 0x3000000 0x0 0x10000>; 843 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; 844 dr_mode = "host"; 845 snps,quirk-frame-length-adjustment = <0x20>; 846 snps,dis_rxdet_inp3_quirk; 847 usb3-lpm-capable; 848 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 849 status = "disabled"; 850 }; 851 852 usb2: usb@3100000 { 853 compatible = "snps,dwc3"; 854 reg = <0x0 0x3100000 0x0 0x10000>; 855 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; 856 dr_mode = "host"; 857 snps,quirk-frame-length-adjustment = <0x20>; 858 snps,dis_rxdet_inp3_quirk; 859 usb3-lpm-capable; 860 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 861 status = "disabled"; 862 }; 863 864 sata: sata@3200000 { 865 compatible = "fsl,ls1043a-ahci"; 866 reg = <0x0 0x3200000 0x0 0x10000>, 867 <0x0 0x20140520 0x0 0x4>; 868 reg-names = "ahci", "sata-ecc"; 869 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 871 QORIQ_CLK_PLL_DIV(1)>; 872 dma-coherent; 873 }; 874 }; 875 876 msi1: msi-controller1@1571000 { 877 compatible = "fsl,ls1043a-msi"; 878 reg = <0x0 0x1571000 0x0 0x8>; 879 msi-controller; 880 interrupts = <0 116 0x4>; 881 }; 882 883 msi2: msi-controller2@1572000 { 884 compatible = "fsl,ls1043a-msi"; 885 reg = <0x0 0x1572000 0x0 0x8>; 886 msi-controller; 887 interrupts = <0 126 0x4>; 888 }; 889 890 msi3: msi-controller3@1573000 { 891 compatible = "fsl,ls1043a-msi"; 892 reg = <0x0 0x1573000 0x0 0x8>; 893 msi-controller; 894 interrupts = <0 160 0x4>; 895 }; 896 897 pcie1: pcie@3400000 { 898 compatible = "fsl,ls1043a-pcie"; 899 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 900 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 901 reg-names = "regs", "config"; 902 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>, 903 <0 118 IRQ_TYPE_LEVEL_HIGH>; 904 interrupt-names = "pme", "aer"; 905 #address-cells = <3>; 906 #size-cells = <2>; 907 device_type = "pci"; 908 num-viewport = <6>; 909 bus-range = <0x0 0xff>; 910 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 911 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 912 msi-parent = <&msi1>, <&msi2>, <&msi3>; 913 #interrupt-cells = <1>; 914 interrupt-map-mask = <0 0 0 7>; 915 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, 916 <0000 0 0 2 &gic 0 111 0x4>, 917 <0000 0 0 3 &gic 0 112 0x4>, 918 <0000 0 0 4 &gic 0 113 0x4>; 919 fsl,pcie-scfg = <&scfg 0>; 920 big-endian; 921 status = "disabled"; 922 }; 923 924 pcie2: pcie@3500000 { 925 compatible = "fsl,ls1043a-pcie"; 926 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 927 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 928 reg-names = "regs", "config"; 929 interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>, 930 <0 128 IRQ_TYPE_LEVEL_HIGH>; 931 interrupt-names = "pme", "aer"; 932 #address-cells = <3>; 933 #size-cells = <2>; 934 device_type = "pci"; 935 num-viewport = <6>; 936 bus-range = <0x0 0xff>; 937 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 938 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 939 msi-parent = <&msi1>, <&msi2>, <&msi3>; 940 #interrupt-cells = <1>; 941 interrupt-map-mask = <0 0 0 7>; 942 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, 943 <0000 0 0 2 &gic 0 121 0x4>, 944 <0000 0 0 3 &gic 0 122 0x4>, 945 <0000 0 0 4 &gic 0 123 0x4>; 946 fsl,pcie-scfg = <&scfg 1>; 947 big-endian; 948 status = "disabled"; 949 }; 950 951 pcie3: pcie@3600000 { 952 compatible = "fsl,ls1043a-pcie"; 953 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 954 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 955 reg-names = "regs", "config"; 956 interrupts = <0 161 IRQ_TYPE_LEVEL_HIGH>, 957 <0 162 IRQ_TYPE_LEVEL_HIGH>; 958 interrupt-names = "pme", "aer"; 959 #address-cells = <3>; 960 #size-cells = <2>; 961 device_type = "pci"; 962 num-viewport = <6>; 963 bus-range = <0x0 0xff>; 964 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 965 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 966 msi-parent = <&msi1>, <&msi2>, <&msi3>; 967 #interrupt-cells = <1>; 968 interrupt-map-mask = <0 0 0 7>; 969 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, 970 <0000 0 0 2 &gic 0 155 0x4>, 971 <0000 0 0 3 &gic 0 156 0x4>, 972 <0000 0 0 4 &gic 0 157 0x4>; 973 fsl,pcie-scfg = <&scfg 2>; 974 big-endian; 975 status = "disabled"; 976 }; 977 978 qdma: dma-controller@8380000 { 979 compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma"; 980 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 981 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 982 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 983 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 988 interrupt-names = "qdma-error", "qdma-queue0", 989 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 990 dma-channels = <8>; 991 block-number = <1>; 992 block-offset = <0x10000>; 993 fsl,dma-queues = <2>; 994 status-sizes = <64>; 995 queue-sizes = <64 64>; 996 big-endian; 997 }; 998 999 rcpm: power-controller@1ee2140 { 1000 compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1001 reg = <0x0 0x1ee2140 0x0 0x4>; 1002 #fsl,rcpm-wakeup-cells = <1>; 1003 }; 1004 1005 ftm_alarm0: timer@29d0000 { 1006 compatible = "fsl,ls1043a-ftm-alarm"; 1007 reg = <0x0 0x29d0000 0x0 0x10000>; 1008 fsl,rcpm-wakeup = <&rcpm 0x20000>; 1009 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1010 big-endian; 1011 }; 1012 }; 1013 1014 firmware { 1015 optee { 1016 compatible = "linaro,optee-tz"; 1017 method = "smc"; 1018 }; 1019 }; 1020 1021}; 1022 1023#include "qoriq-qman-portals.dtsi" 1024#include "qoriq-bman-portals.dtsi" 1025