1/*
2 * dtsi file for Cavium ThunderX2 CN99XX processor
3 *
4 * Copyright (c) 2017 Cavium Inc.
5 * Copyright (c) 2013-2016 Broadcom
6 * Author: Zi Shen Lim <zlim@broadcom.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15
16/ {
17	model = "Cavium ThunderX2 CN99XX";
18	compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
19	interrupt-parent = <&gic>;
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	/* just 4 cpus now, 128 needed in full config */
24	cpus {
25		#address-cells = <0x2>;
26		#size-cells = <0x0>;
27
28		cpu@0 {
29			device_type = "cpu";
30			compatible = "cavium,thunder2", "brcm,vulcan";
31			reg = <0x0 0x0>;
32			enable-method = "psci";
33		};
34
35		cpu@1 {
36			device_type = "cpu";
37			compatible = "cavium,thunder2", "brcm,vulcan";
38			reg = <0x0 0x1>;
39			enable-method = "psci";
40		};
41
42		cpu@2 {
43			device_type = "cpu";
44			compatible = "cavium,thunder2", "brcm,vulcan";
45			reg = <0x0 0x2>;
46			enable-method = "psci";
47		};
48
49		cpu@3 {
50			device_type = "cpu";
51			compatible = "cavium,thunder2", "brcm,vulcan";
52			reg = <0x0 0x3>;
53			enable-method = "psci";
54		};
55	};
56
57	psci {
58		compatible = "arm,psci-0.2";
59		method = "smc";
60	};
61
62	gic: interrupt-controller@400080000 {
63		compatible = "arm,gic-v3";
64		#interrupt-cells = <3>;
65		#address-cells = <2>;
66		#size-cells = <2>;
67		ranges;
68		interrupt-controller;
69		#redistributor-regions = <1>;
70		reg = <0x04 0x00080000 0x0 0x20000>,	/* GICD */
71		      <0x04 0x01000000 0x0 0x1000000>;	/* GICR */
72		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
73
74		gicits: gic-its@40010000 {
75			compatible = "arm,gic-v3-its";
76			msi-controller;
77			reg = <0x04 0x00100000 0x0 0x20000>;	/* GIC ITS */
78		};
79	};
80
81	timer {
82		compatible = "arm,armv8-timer";
83		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
84			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
85			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
86			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
87	};
88
89	pmu {
90		compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3";
91		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */
92	};
93
94	clk125mhz: uart_clk125mhz {
95		compatible = "fixed-clock";
96		#clock-cells = <0>;
97		clock-frequency = <125000000>;
98		clock-output-names = "clk125mhz";
99	};
100
101	pcie@30000000 {
102		compatible = "pci-host-ecam-generic";
103		device_type = "pci";
104		#interrupt-cells = <1>;
105		#address-cells = <3>;
106		#size-cells = <2>;
107
108		/* ECAM at 0x3000_0000 - 0x4000_0000 */
109		reg = <0x0 0x30000000  0x0 0x10000000>;
110		reg-names = "PCI ECAM";
111
112		/*
113		 * PCI ranges:
114		 *   IO		no supported
115		 *   MEM        0x4000_0000 - 0x6000_0000
116		 *   MEM64 pref 0x40_0000_0000 - 0x60_0000_0000
117		 */
118		ranges =
119		  <0x02000000    0 0x40000000    0 0x40000000    0 0x20000000
120		   0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>;
121		bus-range = <0 0xff>;
122		interrupt-map-mask = <0 0 0 7>;
123		interrupt-map =
124		      /* addr  pin  ic   icaddr  icintr */
125			<0 0 0  1  &gic   0 0    GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
126			 0 0 0  2  &gic   0 0    GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
127			 0 0 0  3  &gic   0 0    GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
128			 0 0 0  4  &gic   0 0    GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
129		msi-parent = <&gicits>;
130		dma-coherent;
131	};
132
133	soc {
134		compatible = "simple-bus";
135		#address-cells = <2>;
136		#size-cells = <2>;
137		ranges;
138
139		uart0: serial@402020000 {
140			compatible = "arm,pl011", "arm,primecell";
141			reg = <0x04 0x02020000 0x0 0x1000>;
142			interrupt-parent = <&gic>;
143			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
144			clocks = <&clk125mhz>;
145			clock-names = "apb_pclk";
146		};
147	};
148
149};
150