1517b311eSJayachandran C/* 2517b311eSJayachandran C * dtsi file for Cavium ThunderX2 CN99XX processor 3517b311eSJayachandran C * 4517b311eSJayachandran C * Copyright (c) 2017 Cavium Inc. 5517b311eSJayachandran C * Copyright (c) 2013-2016 Broadcom 6517b311eSJayachandran C * Author: Zi Shen Lim <zlim@broadcom.com> 7517b311eSJayachandran C * 8517b311eSJayachandran C * This program is free software; you can redistribute it and/or 9517b311eSJayachandran C * modify it under the terms of the GNU General Public License as 10517b311eSJayachandran C * published by the Free Software Foundation; either version 2 of 11517b311eSJayachandran C * the License, or (at your option) any later version. 12517b311eSJayachandran C */ 13517b311eSJayachandran C 14517b311eSJayachandran C#include <dt-bindings/interrupt-controller/arm-gic.h> 15517b311eSJayachandran C 16517b311eSJayachandran C/ { 17517b311eSJayachandran C model = "Cavium ThunderX2 CN99XX"; 18517b311eSJayachandran C compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; 19517b311eSJayachandran C interrupt-parent = <&gic>; 20517b311eSJayachandran C #address-cells = <2>; 21517b311eSJayachandran C #size-cells = <2>; 22517b311eSJayachandran C 23517b311eSJayachandran C /* just 4 cpus now, 128 needed in full config */ 24517b311eSJayachandran C cpus { 25517b311eSJayachandran C #address-cells = <0x2>; 26517b311eSJayachandran C #size-cells = <0x0>; 27517b311eSJayachandran C 28517b311eSJayachandran C cpu@0 { 29517b311eSJayachandran C device_type = "cpu"; 30517b311eSJayachandran C compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; 31517b311eSJayachandran C reg = <0x0 0x0>; 32517b311eSJayachandran C enable-method = "psci"; 33517b311eSJayachandran C }; 34517b311eSJayachandran C 35517b311eSJayachandran C cpu@1 { 36517b311eSJayachandran C device_type = "cpu"; 37517b311eSJayachandran C compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; 38517b311eSJayachandran C reg = <0x0 0x1>; 39517b311eSJayachandran C enable-method = "psci"; 40517b311eSJayachandran C }; 41517b311eSJayachandran C 42517b311eSJayachandran C cpu@2 { 43517b311eSJayachandran C device_type = "cpu"; 44517b311eSJayachandran C compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; 45517b311eSJayachandran C reg = <0x0 0x2>; 46517b311eSJayachandran C enable-method = "psci"; 47517b311eSJayachandran C }; 48517b311eSJayachandran C 49517b311eSJayachandran C cpu@3 { 50517b311eSJayachandran C device_type = "cpu"; 51517b311eSJayachandran C compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; 52517b311eSJayachandran C reg = <0x0 0x3>; 53517b311eSJayachandran C enable-method = "psci"; 54517b311eSJayachandran C }; 55517b311eSJayachandran C }; 56517b311eSJayachandran C 57517b311eSJayachandran C psci { 58517b311eSJayachandran C compatible = "arm,psci-0.2"; 59517b311eSJayachandran C method = "smc"; 60517b311eSJayachandran C }; 61517b311eSJayachandran C 62517b311eSJayachandran C gic: interrupt-controller@400080000 { 63517b311eSJayachandran C compatible = "arm,gic-v3"; 64517b311eSJayachandran C #interrupt-cells = <3>; 65517b311eSJayachandran C #address-cells = <2>; 66517b311eSJayachandran C #size-cells = <2>; 67517b311eSJayachandran C ranges; 68517b311eSJayachandran C interrupt-controller; 69517b311eSJayachandran C #redistributor-regions = <1>; 70517b311eSJayachandran C reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ 71517b311eSJayachandran C <0x04 0x01000000 0x0 0x1000000>; /* GICR */ 72517b311eSJayachandran C interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 73517b311eSJayachandran C 74517b311eSJayachandran C gicits: gic-its@40010000 { 75517b311eSJayachandran C compatible = "arm,gic-v3-its"; 76517b311eSJayachandran C msi-controller; 77517b311eSJayachandran C reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ 78517b311eSJayachandran C }; 79517b311eSJayachandran C }; 80517b311eSJayachandran C 81517b311eSJayachandran C timer { 82517b311eSJayachandran C compatible = "arm,armv8-timer"; 83517b311eSJayachandran C interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 84517b311eSJayachandran C <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 85517b311eSJayachandran C <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 86517b311eSJayachandran C <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 87517b311eSJayachandran C }; 88517b311eSJayachandran C 89517b311eSJayachandran C pmu { 90517b311eSJayachandran C compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; 91517b311eSJayachandran C interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ 92517b311eSJayachandran C }; 93517b311eSJayachandran C 94517b311eSJayachandran C clk125mhz: uart_clk125mhz { 95517b311eSJayachandran C compatible = "fixed-clock"; 96517b311eSJayachandran C #clock-cells = <0>; 97517b311eSJayachandran C clock-frequency = <125000000>; 98517b311eSJayachandran C clock-output-names = "clk125mhz"; 99517b311eSJayachandran C }; 100517b311eSJayachandran C 101e2c8d283SRob Herring pcie@30000000 { 102517b311eSJayachandran C compatible = "pci-host-ecam-generic"; 103517b311eSJayachandran C device_type = "pci"; 104517b311eSJayachandran C #interrupt-cells = <1>; 105517b311eSJayachandran C #address-cells = <3>; 106517b311eSJayachandran C #size-cells = <2>; 107517b311eSJayachandran C 108517b311eSJayachandran C /* ECAM at 0x3000_0000 - 0x4000_0000 */ 109517b311eSJayachandran C reg = <0x0 0x30000000 0x0 0x10000000>; 110517b311eSJayachandran C reg-names = "PCI ECAM"; 111517b311eSJayachandran C 112517b311eSJayachandran C /* 113517b311eSJayachandran C * PCI ranges: 114517b311eSJayachandran C * IO no supported 115517b311eSJayachandran C * MEM 0x4000_0000 - 0x6000_0000 116517b311eSJayachandran C * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 117517b311eSJayachandran C */ 118517b311eSJayachandran C ranges = 119517b311eSJayachandran C <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 120517b311eSJayachandran C 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; 121e2c8d283SRob Herring bus-range = <0 0xff>; 122517b311eSJayachandran C interrupt-map-mask = <0 0 0 7>; 123517b311eSJayachandran C interrupt-map = 124517b311eSJayachandran C /* addr pin ic icaddr icintr */ 125517b311eSJayachandran C <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 126517b311eSJayachandran C 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 127517b311eSJayachandran C 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 128517b311eSJayachandran C 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 129517b311eSJayachandran C msi-parent = <&gicits>; 130517b311eSJayachandran C dma-coherent; 131517b311eSJayachandran C }; 132517b311eSJayachandran C 133517b311eSJayachandran C soc { 134517b311eSJayachandran C compatible = "simple-bus"; 135517b311eSJayachandran C #address-cells = <2>; 136517b311eSJayachandran C #size-cells = <2>; 137517b311eSJayachandran C ranges; 138517b311eSJayachandran C 139517b311eSJayachandran C uart0: serial@402020000 { 140517b311eSJayachandran C compatible = "arm,pl011", "arm,primecell"; 141517b311eSJayachandran C reg = <0x04 0x02020000 0x0 0x1000>; 142517b311eSJayachandran C interrupt-parent = <&gic>; 143517b311eSJayachandran C interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 144517b311eSJayachandran C clocks = <&clk125mhz>; 145517b311eSJayachandran C clock-names = "apb_pclk"; 146517b311eSJayachandran C }; 147517b311eSJayachandran C }; 148517b311eSJayachandran C 149517b311eSJayachandran C}; 150