12874c5fdSThomas Gleixner// SPDX-License-Identifier: GPL-2.0-or-later 2517b311eSJayachandran C/* 3517b311eSJayachandran C * dtsi file for Cavium ThunderX2 CN99XX processor 4517b311eSJayachandran C * 5517b311eSJayachandran C * Copyright (c) 2017 Cavium Inc. 6517b311eSJayachandran C * Copyright (c) 2013-2016 Broadcom 7517b311eSJayachandran C * Author: Zi Shen Lim <zlim@broadcom.com> 8517b311eSJayachandran C */ 9517b311eSJayachandran C 10517b311eSJayachandran C#include <dt-bindings/interrupt-controller/arm-gic.h> 11517b311eSJayachandran C 12517b311eSJayachandran C/ { 13517b311eSJayachandran C model = "Cavium ThunderX2 CN99XX"; 14517b311eSJayachandran C compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; 15517b311eSJayachandran C interrupt-parent = <&gic>; 16517b311eSJayachandran C #address-cells = <2>; 17517b311eSJayachandran C #size-cells = <2>; 18517b311eSJayachandran C 19517b311eSJayachandran C /* just 4 cpus now, 128 needed in full config */ 20517b311eSJayachandran C cpus { 21517b311eSJayachandran C #address-cells = <0x2>; 22517b311eSJayachandran C #size-cells = <0x0>; 23517b311eSJayachandran C 24517b311eSJayachandran C cpu@0 { 25517b311eSJayachandran C device_type = "cpu"; 2631af04cdSRob Herring compatible = "cavium,thunder2", "brcm,vulcan"; 27517b311eSJayachandran C reg = <0x0 0x0>; 28517b311eSJayachandran C enable-method = "psci"; 29517b311eSJayachandran C }; 30517b311eSJayachandran C 31517b311eSJayachandran C cpu@1 { 32517b311eSJayachandran C device_type = "cpu"; 3331af04cdSRob Herring compatible = "cavium,thunder2", "brcm,vulcan"; 34517b311eSJayachandran C reg = <0x0 0x1>; 35517b311eSJayachandran C enable-method = "psci"; 36517b311eSJayachandran C }; 37517b311eSJayachandran C 38517b311eSJayachandran C cpu@2 { 39517b311eSJayachandran C device_type = "cpu"; 4031af04cdSRob Herring compatible = "cavium,thunder2", "brcm,vulcan"; 41517b311eSJayachandran C reg = <0x0 0x2>; 42517b311eSJayachandran C enable-method = "psci"; 43517b311eSJayachandran C }; 44517b311eSJayachandran C 45517b311eSJayachandran C cpu@3 { 46517b311eSJayachandran C device_type = "cpu"; 4731af04cdSRob Herring compatible = "cavium,thunder2", "brcm,vulcan"; 48517b311eSJayachandran C reg = <0x0 0x3>; 49517b311eSJayachandran C enable-method = "psci"; 50517b311eSJayachandran C }; 51517b311eSJayachandran C }; 52517b311eSJayachandran C 53517b311eSJayachandran C psci { 54517b311eSJayachandran C compatible = "arm,psci-0.2"; 55517b311eSJayachandran C method = "smc"; 56517b311eSJayachandran C }; 57517b311eSJayachandran C 58*d2e5c16fSRob Herring gic: interrupt-controller@4000080000 { 59517b311eSJayachandran C compatible = "arm,gic-v3"; 60517b311eSJayachandran C #interrupt-cells = <3>; 61517b311eSJayachandran C #address-cells = <2>; 62517b311eSJayachandran C #size-cells = <2>; 63517b311eSJayachandran C ranges; 64517b311eSJayachandran C interrupt-controller; 65517b311eSJayachandran C #redistributor-regions = <1>; 66517b311eSJayachandran C reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ 67517b311eSJayachandran C <0x04 0x01000000 0x0 0x1000000>; /* GICR */ 68517b311eSJayachandran C interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 69517b311eSJayachandran C 70*d2e5c16fSRob Herring gicits: msi-controller@4000100000 { 71517b311eSJayachandran C compatible = "arm,gic-v3-its"; 72517b311eSJayachandran C msi-controller; 73517b311eSJayachandran C reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ 74517b311eSJayachandran C }; 75517b311eSJayachandran C }; 76517b311eSJayachandran C 77517b311eSJayachandran C timer { 78517b311eSJayachandran C compatible = "arm,armv8-timer"; 79517b311eSJayachandran C interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 80517b311eSJayachandran C <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 81517b311eSJayachandran C <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 82517b311eSJayachandran C <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 83517b311eSJayachandran C }; 84517b311eSJayachandran C 85517b311eSJayachandran C pmu { 86517b311eSJayachandran C compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; 87517b311eSJayachandran C interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ 88517b311eSJayachandran C }; 89517b311eSJayachandran C 90517b311eSJayachandran C clk125mhz: uart_clk125mhz { 91517b311eSJayachandran C compatible = "fixed-clock"; 92517b311eSJayachandran C #clock-cells = <0>; 93517b311eSJayachandran C clock-frequency = <125000000>; 94517b311eSJayachandran C clock-output-names = "clk125mhz"; 95517b311eSJayachandran C }; 96517b311eSJayachandran C 97e2c8d283SRob Herring pcie@30000000 { 98517b311eSJayachandran C compatible = "pci-host-ecam-generic"; 99517b311eSJayachandran C device_type = "pci"; 100517b311eSJayachandran C #interrupt-cells = <1>; 101517b311eSJayachandran C #address-cells = <3>; 102517b311eSJayachandran C #size-cells = <2>; 103517b311eSJayachandran C 104517b311eSJayachandran C /* ECAM at 0x3000_0000 - 0x4000_0000 */ 105517b311eSJayachandran C reg = <0x0 0x30000000 0x0 0x10000000>; 106517b311eSJayachandran C reg-names = "PCI ECAM"; 107517b311eSJayachandran C 108517b311eSJayachandran C /* 109517b311eSJayachandran C * PCI ranges: 110517b311eSJayachandran C * IO no supported 111517b311eSJayachandran C * MEM 0x4000_0000 - 0x6000_0000 112517b311eSJayachandran C * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 113517b311eSJayachandran C */ 114517b311eSJayachandran C ranges = 115517b311eSJayachandran C <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 116517b311eSJayachandran C 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; 117e2c8d283SRob Herring bus-range = <0 0xff>; 118517b311eSJayachandran C interrupt-map-mask = <0 0 0 7>; 119517b311eSJayachandran C interrupt-map = 120517b311eSJayachandran C /* addr pin ic icaddr icintr */ 121517b311eSJayachandran C <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 122517b311eSJayachandran C 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 123517b311eSJayachandran C 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 124517b311eSJayachandran C 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 125517b311eSJayachandran C msi-parent = <&gicits>; 126517b311eSJayachandran C dma-coherent; 127517b311eSJayachandran C }; 128517b311eSJayachandran C 129517b311eSJayachandran C soc { 130517b311eSJayachandran C compatible = "simple-bus"; 131517b311eSJayachandran C #address-cells = <2>; 132517b311eSJayachandran C #size-cells = <2>; 133517b311eSJayachandran C ranges; 134517b311eSJayachandran C 135517b311eSJayachandran C uart0: serial@402020000 { 136517b311eSJayachandran C compatible = "arm,pl011", "arm,primecell"; 137517b311eSJayachandran C reg = <0x04 0x02020000 0x0 0x1000>; 138517b311eSJayachandran C interrupt-parent = <&gic>; 139517b311eSJayachandran C interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 140517b311eSJayachandran C clocks = <&clk125mhz>; 141517b311eSJayachandran C clock-names = "apb_pclk"; 142517b311eSJayachandran C }; 143517b311eSJayachandran C }; 144517b311eSJayachandran C 145517b311eSJayachandran C}; 146