1ca5b3410SRobert Richter/* 2ca5b3410SRobert Richter * ARM Ltd. Fast Models 3ca5b3410SRobert Richter * 4ca5b3410SRobert Richter * Architecture Envelope Model (AEM) ARMv8-A 5ca5b3410SRobert Richter * ARMAEMv8AMPCT 6ca5b3410SRobert Richter * 7ca5b3410SRobert Richter * RTSM_VE_AEMv8A.lisa 8ca5b3410SRobert Richter */ 9ca5b3410SRobert Richter 10ca5b3410SRobert Richter/dts-v1/; 11ca5b3410SRobert Richter 12ca5b3410SRobert Richter/memreserve/ 0x80000000 0x00010000; 13ca5b3410SRobert Richter 14ca5b3410SRobert Richter/ { 15ca5b3410SRobert Richter model = "RTSM_VE_AEMv8A"; 16ca5b3410SRobert Richter compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress"; 17ca5b3410SRobert Richter interrupt-parent = <&gic>; 18ca5b3410SRobert Richter #address-cells = <2>; 19ca5b3410SRobert Richter #size-cells = <2>; 20ca5b3410SRobert Richter 21ca5b3410SRobert Richter chosen { }; 22ca5b3410SRobert Richter 23ca5b3410SRobert Richter aliases { 24ca5b3410SRobert Richter serial0 = &v2m_serial0; 25ca5b3410SRobert Richter serial1 = &v2m_serial1; 26ca5b3410SRobert Richter serial2 = &v2m_serial2; 27ca5b3410SRobert Richter serial3 = &v2m_serial3; 28ca5b3410SRobert Richter }; 29ca5b3410SRobert Richter 30ca5b3410SRobert Richter cpus { 31ca5b3410SRobert Richter #address-cells = <2>; 32ca5b3410SRobert Richter #size-cells = <0>; 33ca5b3410SRobert Richter 34ca5b3410SRobert Richter cpu@0 { 35ca5b3410SRobert Richter device_type = "cpu"; 36ca5b3410SRobert Richter compatible = "arm,armv8"; 37ca5b3410SRobert Richter reg = <0x0 0x0>; 38ca5b3410SRobert Richter enable-method = "spin-table"; 39ca5b3410SRobert Richter cpu-release-addr = <0x0 0x8000fff8>; 40ca5b3410SRobert Richter }; 41ca5b3410SRobert Richter cpu@1 { 42ca5b3410SRobert Richter device_type = "cpu"; 43ca5b3410SRobert Richter compatible = "arm,armv8"; 44ca5b3410SRobert Richter reg = <0x0 0x1>; 45ca5b3410SRobert Richter enable-method = "spin-table"; 46ca5b3410SRobert Richter cpu-release-addr = <0x0 0x8000fff8>; 47ca5b3410SRobert Richter }; 48ca5b3410SRobert Richter cpu@2 { 49ca5b3410SRobert Richter device_type = "cpu"; 50ca5b3410SRobert Richter compatible = "arm,armv8"; 51ca5b3410SRobert Richter reg = <0x0 0x2>; 52ca5b3410SRobert Richter enable-method = "spin-table"; 53ca5b3410SRobert Richter cpu-release-addr = <0x0 0x8000fff8>; 54ca5b3410SRobert Richter }; 55ca5b3410SRobert Richter cpu@3 { 56ca5b3410SRobert Richter device_type = "cpu"; 57ca5b3410SRobert Richter compatible = "arm,armv8"; 58ca5b3410SRobert Richter reg = <0x0 0x3>; 59ca5b3410SRobert Richter enable-method = "spin-table"; 60ca5b3410SRobert Richter cpu-release-addr = <0x0 0x8000fff8>; 61ca5b3410SRobert Richter }; 62ca5b3410SRobert Richter }; 63ca5b3410SRobert Richter 64ca5b3410SRobert Richter memory@80000000 { 65ca5b3410SRobert Richter device_type = "memory"; 66ca5b3410SRobert Richter reg = <0x00000000 0x80000000 0 0x80000000>, 67ca5b3410SRobert Richter <0x00000008 0x80000000 0 0x80000000>; 68ca5b3410SRobert Richter }; 69ca5b3410SRobert Richter 70ca5b3410SRobert Richter gic: interrupt-controller@2c001000 { 71ca5b3410SRobert Richter compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 72ca5b3410SRobert Richter #interrupt-cells = <3>; 73ca5b3410SRobert Richter #address-cells = <0>; 74ca5b3410SRobert Richter interrupt-controller; 75ca5b3410SRobert Richter reg = <0x0 0x2c001000 0 0x1000>, 76ca5b3410SRobert Richter <0x0 0x2c002000 0 0x1000>, 77ca5b3410SRobert Richter <0x0 0x2c004000 0 0x2000>, 78ca5b3410SRobert Richter <0x0 0x2c006000 0 0x2000>; 79ca5b3410SRobert Richter interrupts = <1 9 0xf04>; 80ca5b3410SRobert Richter }; 81ca5b3410SRobert Richter 82ca5b3410SRobert Richter timer { 83ca5b3410SRobert Richter compatible = "arm,armv8-timer"; 84*6bc474deSLiviu Dudau interrupts = <1 13 0xf08>, 85*6bc474deSLiviu Dudau <1 14 0xf08>, 86*6bc474deSLiviu Dudau <1 11 0xf08>, 87*6bc474deSLiviu Dudau <1 10 0xf08>; 88ca5b3410SRobert Richter clock-frequency = <100000000>; 89ca5b3410SRobert Richter }; 90ca5b3410SRobert Richter 91ca5b3410SRobert Richter pmu { 92ca5b3410SRobert Richter compatible = "arm,armv8-pmuv3"; 93ca5b3410SRobert Richter interrupts = <0 60 4>, 94ca5b3410SRobert Richter <0 61 4>, 95ca5b3410SRobert Richter <0 62 4>, 96ca5b3410SRobert Richter <0 63 4>; 97ca5b3410SRobert Richter }; 98ca5b3410SRobert Richter 99ca5b3410SRobert Richter smb { 100ca5b3410SRobert Richter compatible = "simple-bus"; 101ca5b3410SRobert Richter 102ca5b3410SRobert Richter #address-cells = <2>; 103ca5b3410SRobert Richter #size-cells = <1>; 104ca5b3410SRobert Richter ranges = <0 0 0 0x08000000 0x04000000>, 105ca5b3410SRobert Richter <1 0 0 0x14000000 0x04000000>, 106ca5b3410SRobert Richter <2 0 0 0x18000000 0x04000000>, 107ca5b3410SRobert Richter <3 0 0 0x1c000000 0x04000000>, 108ca5b3410SRobert Richter <4 0 0 0x0c000000 0x04000000>, 109ca5b3410SRobert Richter <5 0 0 0x10000000 0x04000000>; 110ca5b3410SRobert Richter 111ca5b3410SRobert Richter #interrupt-cells = <1>; 112ca5b3410SRobert Richter interrupt-map-mask = <0 0 63>; 113ca5b3410SRobert Richter interrupt-map = <0 0 0 &gic 0 0 4>, 114ca5b3410SRobert Richter <0 0 1 &gic 0 1 4>, 115ca5b3410SRobert Richter <0 0 2 &gic 0 2 4>, 116ca5b3410SRobert Richter <0 0 3 &gic 0 3 4>, 117ca5b3410SRobert Richter <0 0 4 &gic 0 4 4>, 118ca5b3410SRobert Richter <0 0 5 &gic 0 5 4>, 119ca5b3410SRobert Richter <0 0 6 &gic 0 6 4>, 120ca5b3410SRobert Richter <0 0 7 &gic 0 7 4>, 121ca5b3410SRobert Richter <0 0 8 &gic 0 8 4>, 122ca5b3410SRobert Richter <0 0 9 &gic 0 9 4>, 123ca5b3410SRobert Richter <0 0 10 &gic 0 10 4>, 124ca5b3410SRobert Richter <0 0 11 &gic 0 11 4>, 125ca5b3410SRobert Richter <0 0 12 &gic 0 12 4>, 126ca5b3410SRobert Richter <0 0 13 &gic 0 13 4>, 127ca5b3410SRobert Richter <0 0 14 &gic 0 14 4>, 128ca5b3410SRobert Richter <0 0 15 &gic 0 15 4>, 129ca5b3410SRobert Richter <0 0 16 &gic 0 16 4>, 130ca5b3410SRobert Richter <0 0 17 &gic 0 17 4>, 131ca5b3410SRobert Richter <0 0 18 &gic 0 18 4>, 132ca5b3410SRobert Richter <0 0 19 &gic 0 19 4>, 133ca5b3410SRobert Richter <0 0 20 &gic 0 20 4>, 134ca5b3410SRobert Richter <0 0 21 &gic 0 21 4>, 135ca5b3410SRobert Richter <0 0 22 &gic 0 22 4>, 136ca5b3410SRobert Richter <0 0 23 &gic 0 23 4>, 137ca5b3410SRobert Richter <0 0 24 &gic 0 24 4>, 138ca5b3410SRobert Richter <0 0 25 &gic 0 25 4>, 139ca5b3410SRobert Richter <0 0 26 &gic 0 26 4>, 140ca5b3410SRobert Richter <0 0 27 &gic 0 27 4>, 141ca5b3410SRobert Richter <0 0 28 &gic 0 28 4>, 142ca5b3410SRobert Richter <0 0 29 &gic 0 29 4>, 143ca5b3410SRobert Richter <0 0 30 &gic 0 30 4>, 144ca5b3410SRobert Richter <0 0 31 &gic 0 31 4>, 145ca5b3410SRobert Richter <0 0 32 &gic 0 32 4>, 146ca5b3410SRobert Richter <0 0 33 &gic 0 33 4>, 147ca5b3410SRobert Richter <0 0 34 &gic 0 34 4>, 148ca5b3410SRobert Richter <0 0 35 &gic 0 35 4>, 149ca5b3410SRobert Richter <0 0 36 &gic 0 36 4>, 150ca5b3410SRobert Richter <0 0 37 &gic 0 37 4>, 151ca5b3410SRobert Richter <0 0 38 &gic 0 38 4>, 152ca5b3410SRobert Richter <0 0 39 &gic 0 39 4>, 153ca5b3410SRobert Richter <0 0 40 &gic 0 40 4>, 154ca5b3410SRobert Richter <0 0 41 &gic 0 41 4>, 155ca5b3410SRobert Richter <0 0 42 &gic 0 42 4>; 156ca5b3410SRobert Richter 157ca5b3410SRobert Richter /include/ "rtsm_ve-motherboard.dtsi" 158ca5b3410SRobert Richter }; 159ca5b3410SRobert Richter}; 160