1*96bb0954SRobin Murphy/ { 2*96bb0954SRobin Murphy etf@20010000 { 3*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 4*96bb0954SRobin Murphy }; 5*96bb0954SRobin Murphy 6*96bb0954SRobin Murphy tpiu@20030000 { 7*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 8*96bb0954SRobin Murphy }; 9*96bb0954SRobin Murphy 10*96bb0954SRobin Murphy funnel@20040000 { 11*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 12*96bb0954SRobin Murphy }; 13*96bb0954SRobin Murphy 14*96bb0954SRobin Murphy etr@20070000 { 15*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 16*96bb0954SRobin Murphy }; 17*96bb0954SRobin Murphy 18*96bb0954SRobin Murphy stm@20100000 { 19*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 20*96bb0954SRobin Murphy }; 21*96bb0954SRobin Murphy 22*96bb0954SRobin Murphy replicator@20120000 { 23*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 24*96bb0954SRobin Murphy }; 25*96bb0954SRobin Murphy 26*96bb0954SRobin Murphy funnel@220c0000 { 27*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 28*96bb0954SRobin Murphy }; 29*96bb0954SRobin Murphy 30*96bb0954SRobin Murphy funnel@230c0000 { 31*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 32*96bb0954SRobin Murphy }; 33*96bb0954SRobin Murphy 34*96bb0954SRobin Murphy hdlcd@7ff50000 { 35*96bb0954SRobin Murphy clocks = <&scmi_clk 3>; 36*96bb0954SRobin Murphy }; 37*96bb0954SRobin Murphy 38*96bb0954SRobin Murphy hdlcd@7ff60000 { 39*96bb0954SRobin Murphy clocks = <&scmi_clk 3>; 40*96bb0954SRobin Murphy }; 41*96bb0954SRobin Murphy 42*96bb0954SRobin Murphy /delete-node/ scpi; 43*96bb0954SRobin Murphy 44*96bb0954SRobin Murphy firmware { 45*96bb0954SRobin Murphy scmi { 46*96bb0954SRobin Murphy compatible = "arm,scmi"; 47*96bb0954SRobin Murphy mbox-names = "tx", "rx"; 48*96bb0954SRobin Murphy mboxes = <&mailbox 0 0 &mailbox 0 1>; 49*96bb0954SRobin Murphy shmem = <&cpu_scp_lpri0 &cpu_scp_lpri1>; 50*96bb0954SRobin Murphy #address-cells = <1>; 51*96bb0954SRobin Murphy #size-cells = <0>; 52*96bb0954SRobin Murphy 53*96bb0954SRobin Murphy scmi_devpd: protocol@11 { 54*96bb0954SRobin Murphy reg = <0x11>; 55*96bb0954SRobin Murphy #power-domain-cells = <1>; 56*96bb0954SRobin Murphy }; 57*96bb0954SRobin Murphy 58*96bb0954SRobin Murphy scmi_dvfs: protocol@13 { 59*96bb0954SRobin Murphy reg = <0x13>; 60*96bb0954SRobin Murphy #clock-cells = <1>; 61*96bb0954SRobin Murphy mbox-names = "tx", "rx"; 62*96bb0954SRobin Murphy mboxes = <&mailbox 1 0 &mailbox 1 1>; 63*96bb0954SRobin Murphy shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>; 64*96bb0954SRobin Murphy }; 65*96bb0954SRobin Murphy 66*96bb0954SRobin Murphy scmi_clk: protocol@14 { 67*96bb0954SRobin Murphy reg = <0x14>; 68*96bb0954SRobin Murphy #clock-cells = <1>; 69*96bb0954SRobin Murphy }; 70*96bb0954SRobin Murphy 71*96bb0954SRobin Murphy scmi_sensors0: protocol@15 { 72*96bb0954SRobin Murphy reg = <0x15>; 73*96bb0954SRobin Murphy #thermal-sensor-cells = <1>; 74*96bb0954SRobin Murphy }; 75*96bb0954SRobin Murphy }; 76*96bb0954SRobin Murphy }; 77*96bb0954SRobin Murphy 78*96bb0954SRobin Murphy thermal-zones { 79*96bb0954SRobin Murphy pmic { 80*96bb0954SRobin Murphy thermal-sensors = <&scmi_sensors0 0>; 81*96bb0954SRobin Murphy }; 82*96bb0954SRobin Murphy 83*96bb0954SRobin Murphy soc { 84*96bb0954SRobin Murphy thermal-sensors = <&scmi_sensors0 3>; 85*96bb0954SRobin Murphy }; 86*96bb0954SRobin Murphy 87*96bb0954SRobin Murphy big-cluster { 88*96bb0954SRobin Murphy thermal-sensors = <&scmi_sensors0 21>; 89*96bb0954SRobin Murphy }; 90*96bb0954SRobin Murphy 91*96bb0954SRobin Murphy little-cluster { 92*96bb0954SRobin Murphy thermal-sensors = <&scmi_sensors0 22>; 93*96bb0954SRobin Murphy }; 94*96bb0954SRobin Murphy 95*96bb0954SRobin Murphy gpu0 { 96*96bb0954SRobin Murphy thermal-sensors = <&scmi_sensors0 23>; 97*96bb0954SRobin Murphy }; 98*96bb0954SRobin Murphy 99*96bb0954SRobin Murphy gpu1 { 100*96bb0954SRobin Murphy thermal-sensors = <&scmi_sensors0 24>; 101*96bb0954SRobin Murphy }; 102*96bb0954SRobin Murphy }; 103*96bb0954SRobin Murphy 104*96bb0954SRobin Murphy}; 105*96bb0954SRobin Murphy 106*96bb0954SRobin Murphy&A53_0 { 107*96bb0954SRobin Murphy clocks = <&scmi_dvfs 1>; 108*96bb0954SRobin Murphy}; 109*96bb0954SRobin Murphy&A53_1 { 110*96bb0954SRobin Murphy clocks = <&scmi_dvfs 1>; 111*96bb0954SRobin Murphy}; 112*96bb0954SRobin Murphy&A53_2 { 113*96bb0954SRobin Murphy clocks = <&scmi_dvfs 1>; 114*96bb0954SRobin Murphy}; 115*96bb0954SRobin Murphy&A53_3 { 116*96bb0954SRobin Murphy clocks = <&scmi_dvfs 1>; 117*96bb0954SRobin Murphy}; 118*96bb0954SRobin Murphy 119*96bb0954SRobin Murphy&cpu_debug0 { 120*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 121*96bb0954SRobin Murphy}; 122*96bb0954SRobin Murphy&cpu_debug1 { 123*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 124*96bb0954SRobin Murphy}; 125*96bb0954SRobin Murphy&cpu_debug2 { 126*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 127*96bb0954SRobin Murphy}; 128*96bb0954SRobin Murphy&cpu_debug3 { 129*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 130*96bb0954SRobin Murphy}; 131*96bb0954SRobin Murphy&cpu_debug4 { 132*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 133*96bb0954SRobin Murphy}; 134*96bb0954SRobin Murphy&cpu_debug5 { 135*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 136*96bb0954SRobin Murphy}; 137*96bb0954SRobin Murphy 138*96bb0954SRobin Murphy&etm0 { 139*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 140*96bb0954SRobin Murphy}; 141*96bb0954SRobin Murphy&etm1 { 142*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 143*96bb0954SRobin Murphy}; 144*96bb0954SRobin Murphy&etm2 { 145*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 146*96bb0954SRobin Murphy}; 147*96bb0954SRobin Murphy&etm3 { 148*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 149*96bb0954SRobin Murphy}; 150*96bb0954SRobin Murphy&etm4 { 151*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 152*96bb0954SRobin Murphy}; 153*96bb0954SRobin Murphy&etm5 { 154*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 155*96bb0954SRobin Murphy}; 156*96bb0954SRobin Murphy 157*96bb0954SRobin Murphy&gpu { 158*96bb0954SRobin Murphy clocks = <&scmi_dvfs 2>; 159*96bb0954SRobin Murphy power-domains = <&scmi_devpd 9>; 160*96bb0954SRobin Murphy}; 161*96bb0954SRobin Murphy 162*96bb0954SRobin Murphy&mailbox { 163*96bb0954SRobin Murphy compatible = "arm,mhu-doorbell", "arm,primecell"; 164*96bb0954SRobin Murphy #mbox-cells = <2>; 165*96bb0954SRobin Murphy mbox-name = "ARM-MHU"; 166*96bb0954SRobin Murphy}; 167*96bb0954SRobin Murphy 168*96bb0954SRobin Murphy&smmu_etr { 169*96bb0954SRobin Murphy power-domains = <&scmi_devpd 8>; 170*96bb0954SRobin Murphy}; 171*96bb0954SRobin Murphy 172*96bb0954SRobin Murphy&smmu_gpu { 173*96bb0954SRobin Murphy power-domains = <&scmi_devpd 9>; 174*96bb0954SRobin Murphy}; 175*96bb0954SRobin Murphy 176*96bb0954SRobin Murphy&sram { 177*96bb0954SRobin Murphy /delete-node/ scp-sram@0; 178*96bb0954SRobin Murphy /delete-node/ scp-sram@200; 179*96bb0954SRobin Murphy 180*96bb0954SRobin Murphy cpu_scp_lpri0: scp-sram@0 { 181*96bb0954SRobin Murphy compatible = "arm,scmi-shmem"; 182*96bb0954SRobin Murphy reg = <0x0 0x80>; 183*96bb0954SRobin Murphy }; 184*96bb0954SRobin Murphy 185*96bb0954SRobin Murphy cpu_scp_lpri1: scp-sram@80 { 186*96bb0954SRobin Murphy compatible = "arm,scmi-shmem"; 187*96bb0954SRobin Murphy reg = <0x80 0x80>; 188*96bb0954SRobin Murphy }; 189*96bb0954SRobin Murphy 190*96bb0954SRobin Murphy cpu_scp_hpri0: scp-sram@100 { 191*96bb0954SRobin Murphy compatible = "arm,scmi-shmem"; 192*96bb0954SRobin Murphy reg = <0x100 0x80>; 193*96bb0954SRobin Murphy }; 194*96bb0954SRobin Murphy 195*96bb0954SRobin Murphy cpu_scp_hpri1: scp-sram@180 { 196*96bb0954SRobin Murphy compatible = "arm,scmi-shmem"; 197*96bb0954SRobin Murphy reg = <0x180 0x80>; 198*96bb0954SRobin Murphy }; 199*96bb0954SRobin Murphy}; 200