xref: /openbmc/linux/scripts/dtc/include-prefixes/arm64/arm/juno-base.dtsi (revision 6d6acd140ab3d46348ec3a9dbfd386d9ca42b825)
1e8020874SLiviu Dudau	/*
2e8020874SLiviu Dudau	 *  Devices shared by all Juno boards
3e8020874SLiviu Dudau	 */
4e8020874SLiviu Dudau
579502355SLiviu Dudau	memtimer: timer@2a810000 {
679502355SLiviu Dudau		compatible = "arm,armv7-timer-mem";
779502355SLiviu Dudau		reg = <0x0 0x2a810000 0x0 0x10000>;
879502355SLiviu Dudau		clock-frequency = <50000000>;
979502355SLiviu Dudau		#address-cells = <2>;
1079502355SLiviu Dudau		#size-cells = <2>;
1179502355SLiviu Dudau		ranges;
1279502355SLiviu Dudau		status = "disabled";
1379502355SLiviu Dudau		frame@2a830000 {
1479502355SLiviu Dudau			frame-number = <1>;
1579502355SLiviu Dudau			interrupts = <0 60 4>;
1679502355SLiviu Dudau			reg = <0x0 0x2a830000 0x0 0x10000>;
1779502355SLiviu Dudau		};
1879502355SLiviu Dudau	};
1979502355SLiviu Dudau
20ff9a6262SSudeep Holla	mailbox: mhu@2b1f0000 {
21ff9a6262SSudeep Holla		compatible = "arm,mhu", "arm,primecell";
22ff9a6262SSudeep Holla		reg = <0x0 0x2b1f0000 0x0 0x1000>;
23ff9a6262SSudeep Holla		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
24ff9a6262SSudeep Holla			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
25ff9a6262SSudeep Holla		interrupt-names = "mhu_lpri_rx",
26ff9a6262SSudeep Holla				  "mhu_hpri_rx";
27ff9a6262SSudeep Holla		#mbox-cells = <1>;
28ff9a6262SSudeep Holla		clocks = <&soc_refclk100mhz>;
29ff9a6262SSudeep Holla		clock-names = "apb_pclk";
30ff9a6262SSudeep Holla	};
31ff9a6262SSudeep Holla
32e8020874SLiviu Dudau	gic: interrupt-controller@2c010000 {
33e8020874SLiviu Dudau		compatible = "arm,gic-400", "arm,cortex-a15-gic";
34e8020874SLiviu Dudau		reg = <0x0 0x2c010000 0 0x1000>,
35e8020874SLiviu Dudau		      <0x0 0x2c02f000 0 0x2000>,
36e8020874SLiviu Dudau		      <0x0 0x2c04f000 0 0x2000>,
37e8020874SLiviu Dudau		      <0x0 0x2c06f000 0 0x2000>;
389e6f374fSLiviu Dudau		#address-cells = <2>;
39e8020874SLiviu Dudau		#interrupt-cells = <3>;
409e6f374fSLiviu Dudau		#size-cells = <2>;
41e8020874SLiviu Dudau		interrupt-controller;
42e8020874SLiviu Dudau		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
439e6f374fSLiviu Dudau		ranges = <0 0 0 0x2c1c0000 0 0x40000>;
449e6f374fSLiviu Dudau		v2m_0: v2m@0 {
459e6f374fSLiviu Dudau			compatible = "arm,gic-v2m-frame";
469e6f374fSLiviu Dudau			msi-controller;
479e6f374fSLiviu Dudau			reg = <0 0 0 0x1000>;
489e6f374fSLiviu Dudau		};
49e8020874SLiviu Dudau	};
50e8020874SLiviu Dudau
51e8020874SLiviu Dudau	timer {
52e8020874SLiviu Dudau		compatible = "arm,armv8-timer";
53e8020874SLiviu Dudau		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
54e8020874SLiviu Dudau			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
55e8020874SLiviu Dudau			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
56e8020874SLiviu Dudau			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
57e8020874SLiviu Dudau	};
58e8020874SLiviu Dudau
59ff9a6262SSudeep Holla	sram: sram@2e000000 {
60ff9a6262SSudeep Holla		compatible = "arm,juno-sram-ns", "mmio-sram";
61ff9a6262SSudeep Holla		reg = <0x0 0x2e000000 0x0 0x8000>;
62ff9a6262SSudeep Holla
63ff9a6262SSudeep Holla		#address-cells = <1>;
64ff9a6262SSudeep Holla		#size-cells = <1>;
65ff9a6262SSudeep Holla		ranges = <0 0x0 0x2e000000 0x8000>;
66ff9a6262SSudeep Holla
67ff9a6262SSudeep Holla		cpu_scp_lpri: scp-shmem@0 {
68ff9a6262SSudeep Holla			compatible = "arm,juno-scp-shmem";
69ff9a6262SSudeep Holla			reg = <0x0 0x200>;
70ff9a6262SSudeep Holla		};
71ff9a6262SSudeep Holla
72ff9a6262SSudeep Holla		cpu_scp_hpri: scp-shmem@200 {
73ff9a6262SSudeep Holla			compatible = "arm,juno-scp-shmem";
74ff9a6262SSudeep Holla			reg = <0x200 0x200>;
75ff9a6262SSudeep Holla		};
76ff9a6262SSudeep Holla	};
77ff9a6262SSudeep Holla
7836582c60SSudeep Holla	pcie_ctlr: pcie-controller@40000000 {
7936582c60SSudeep Holla		compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
8036582c60SSudeep Holla		device_type = "pci";
8136582c60SSudeep Holla		reg = <0 0x40000000 0 0x10000000>;	/* ECAM config space */
8236582c60SSudeep Holla		bus-range = <0 255>;
8336582c60SSudeep Holla		linux,pci-domain = <0>;
8436582c60SSudeep Holla		#address-cells = <3>;
8536582c60SSudeep Holla		#size-cells = <2>;
8636582c60SSudeep Holla		dma-coherent;
8736582c60SSudeep Holla		ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,
8836582c60SSudeep Holla			 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
8936582c60SSudeep Holla			 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
9036582c60SSudeep Holla		#interrupt-cells = <1>;
9136582c60SSudeep Holla		interrupt-map-mask = <0 0 0 7>;
9236582c60SSudeep Holla		interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
9336582c60SSudeep Holla				<0 0 0 2 &gic 0 0 0 137 4>,
9436582c60SSudeep Holla				<0 0 0 3 &gic 0 0 0 138 4>,
9536582c60SSudeep Holla				<0 0 0 4 &gic 0 0 0 139 4>;
9636582c60SSudeep Holla		msi-parent = <&v2m_0>;
9736582c60SSudeep Holla		status = "disabled";
9836582c60SSudeep Holla	};
9936582c60SSudeep Holla
100ff9a6262SSudeep Holla	scpi {
101ff9a6262SSudeep Holla		compatible = "arm,scpi";
102ff9a6262SSudeep Holla		mboxes = <&mailbox 1>;
103ff9a6262SSudeep Holla		shmem = <&cpu_scp_hpri>;
104ff9a6262SSudeep Holla
105ff9a6262SSudeep Holla		clocks {
106ff9a6262SSudeep Holla			compatible = "arm,scpi-clocks";
107ff9a6262SSudeep Holla
108*6d6acd14SSudeep Holla			scpi_dvfs: scpi-dvfs {
109ff9a6262SSudeep Holla				compatible = "arm,scpi-dvfs-clocks";
110ff9a6262SSudeep Holla				#clock-cells = <1>;
111ff9a6262SSudeep Holla				clock-indices = <0>, <1>, <2>;
112ff9a6262SSudeep Holla				clock-output-names = "atlclk", "aplclk","gpuclk";
113ff9a6262SSudeep Holla			};
114*6d6acd14SSudeep Holla			scpi_clk: scpi-clk {
115ff9a6262SSudeep Holla				compatible = "arm,scpi-variable-clocks";
116ff9a6262SSudeep Holla				#clock-cells = <1>;
1179fd9288eSLiviu Dudau				clock-indices = <3>;
1189fd9288eSLiviu Dudau				clock-output-names = "pxlclk";
119ff9a6262SSudeep Holla			};
120ff9a6262SSudeep Holla		};
121dfacaf0eSPunit Agrawal
122dfacaf0eSPunit Agrawal		scpi_sensors0: sensors {
123dfacaf0eSPunit Agrawal			compatible = "arm,scpi-sensors";
124dfacaf0eSPunit Agrawal			#thermal-sensor-cells = <1>;
125dfacaf0eSPunit Agrawal		};
126ff9a6262SSudeep Holla	};
127ff9a6262SSudeep Holla
128e8020874SLiviu Dudau	/include/ "juno-clocks.dtsi"
129e8020874SLiviu Dudau
130e8020874SLiviu Dudau	dma@7ff00000 {
131e8020874SLiviu Dudau		compatible = "arm,pl330", "arm,primecell";
132e8020874SLiviu Dudau		reg = <0x0 0x7ff00000 0 0x1000>;
133e8020874SLiviu Dudau		#dma-cells = <1>;
134e8020874SLiviu Dudau		#dma-channels = <8>;
135e8020874SLiviu Dudau		#dma-requests = <32>;
136e8020874SLiviu Dudau		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
137e8020874SLiviu Dudau			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
138e8020874SLiviu Dudau			     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
139e8020874SLiviu Dudau			     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
140e8020874SLiviu Dudau			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
141e8020874SLiviu Dudau			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
142e8020874SLiviu Dudau			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
143e8020874SLiviu Dudau			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
144e8020874SLiviu Dudau		clocks = <&soc_faxiclk>;
145e8020874SLiviu Dudau		clock-names = "apb_pclk";
146e8020874SLiviu Dudau	};
147e8020874SLiviu Dudau
1489fd9288eSLiviu Dudau	hdlcd@7ff50000 {
1499fd9288eSLiviu Dudau		compatible = "arm,hdlcd";
1509fd9288eSLiviu Dudau		reg = <0 0x7ff50000 0 0x1000>;
1519fd9288eSLiviu Dudau		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1529fd9288eSLiviu Dudau		clocks = <&scpi_clk 3>;
1539fd9288eSLiviu Dudau		clock-names = "pxlclk";
1549fd9288eSLiviu Dudau
1559fd9288eSLiviu Dudau		port {
156*6d6acd14SSudeep Holla			hdlcd1_output: hdlcd1-endpoint {
1579fd9288eSLiviu Dudau				remote-endpoint = <&tda998x_1_input>;
1589fd9288eSLiviu Dudau			};
1599fd9288eSLiviu Dudau		};
1609fd9288eSLiviu Dudau	};
1619fd9288eSLiviu Dudau
1629fd9288eSLiviu Dudau	hdlcd@7ff60000 {
1639fd9288eSLiviu Dudau		compatible = "arm,hdlcd";
1649fd9288eSLiviu Dudau		reg = <0 0x7ff60000 0 0x1000>;
1659fd9288eSLiviu Dudau		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1669fd9288eSLiviu Dudau		clocks = <&scpi_clk 3>;
1679fd9288eSLiviu Dudau		clock-names = "pxlclk";
1689fd9288eSLiviu Dudau
1699fd9288eSLiviu Dudau		port {
170*6d6acd14SSudeep Holla			hdlcd0_output: hdlcd0-endpoint {
1719fd9288eSLiviu Dudau				remote-endpoint = <&tda998x_0_input>;
1729fd9288eSLiviu Dudau			};
1739fd9288eSLiviu Dudau		};
1749fd9288eSLiviu Dudau	};
1759fd9288eSLiviu Dudau
176e8020874SLiviu Dudau	soc_uart0: uart@7ff80000 {
177e8020874SLiviu Dudau		compatible = "arm,pl011", "arm,primecell";
178e8020874SLiviu Dudau		reg = <0x0 0x7ff80000 0x0 0x1000>;
179e8020874SLiviu Dudau		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
180e8020874SLiviu Dudau		clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
181e8020874SLiviu Dudau		clock-names = "uartclk", "apb_pclk";
182e8020874SLiviu Dudau	};
183e8020874SLiviu Dudau
184e8020874SLiviu Dudau	i2c@7ffa0000 {
185e8020874SLiviu Dudau		compatible = "snps,designware-i2c";
186e8020874SLiviu Dudau		reg = <0x0 0x7ffa0000 0x0 0x1000>;
187e8020874SLiviu Dudau		#address-cells = <1>;
188e8020874SLiviu Dudau		#size-cells = <0>;
189e8020874SLiviu Dudau		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
190e8020874SLiviu Dudau		clock-frequency = <400000>;
191e8020874SLiviu Dudau		i2c-sda-hold-time-ns = <500>;
192e8020874SLiviu Dudau		clocks = <&soc_smc50mhz>;
193e8020874SLiviu Dudau
1949fd9288eSLiviu Dudau		hdmi-transmitter@70 {
195e8020874SLiviu Dudau			compatible = "nxp,tda998x";
196e8020874SLiviu Dudau			reg = <0x70>;
1979fd9288eSLiviu Dudau			port {
198*6d6acd14SSudeep Holla				tda998x_0_input: tda998x-0-endpoint {
1999fd9288eSLiviu Dudau					remote-endpoint = <&hdlcd0_output>;
2009fd9288eSLiviu Dudau				};
2019fd9288eSLiviu Dudau			};
202e8020874SLiviu Dudau		};
203e8020874SLiviu Dudau
2049fd9288eSLiviu Dudau		hdmi-transmitter@71 {
205e8020874SLiviu Dudau			compatible = "nxp,tda998x";
206e8020874SLiviu Dudau			reg = <0x71>;
2079fd9288eSLiviu Dudau			port {
208*6d6acd14SSudeep Holla				tda998x_1_input: tda998x-1-endpoint {
2099fd9288eSLiviu Dudau					remote-endpoint = <&hdlcd1_output>;
2109fd9288eSLiviu Dudau				};
2119fd9288eSLiviu Dudau			};
212e8020874SLiviu Dudau		};
213e8020874SLiviu Dudau	};
214e8020874SLiviu Dudau
215e8020874SLiviu Dudau	ohci@7ffb0000 {
216e8020874SLiviu Dudau		compatible = "generic-ohci";
217e8020874SLiviu Dudau		reg = <0x0 0x7ffb0000 0x0 0x10000>;
218e8020874SLiviu Dudau		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
219e8020874SLiviu Dudau		clocks = <&soc_usb48mhz>;
220e8020874SLiviu Dudau	};
221e8020874SLiviu Dudau
222e8020874SLiviu Dudau	ehci@7ffc0000 {
223e8020874SLiviu Dudau		compatible = "generic-ehci";
224e8020874SLiviu Dudau		reg = <0x0 0x7ffc0000 0x0 0x10000>;
225e8020874SLiviu Dudau		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
226e8020874SLiviu Dudau		clocks = <&soc_usb48mhz>;
227e8020874SLiviu Dudau	};
228e8020874SLiviu Dudau
229e8020874SLiviu Dudau	memory-controller@7ffd0000 {
230e8020874SLiviu Dudau		compatible = "arm,pl354", "arm,primecell";
231e8020874SLiviu Dudau		reg = <0 0x7ffd0000 0 0x1000>;
232e8020874SLiviu Dudau		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
233e8020874SLiviu Dudau			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
234e8020874SLiviu Dudau		clocks = <&soc_smc50mhz>;
235e8020874SLiviu Dudau		clock-names = "apb_pclk";
236e8020874SLiviu Dudau	};
237e8020874SLiviu Dudau
238e8020874SLiviu Dudau	memory@80000000 {
239e8020874SLiviu Dudau		device_type = "memory";
240e8020874SLiviu Dudau		/* last 16MB of the first memory area is reserved for secure world use by firmware */
241e8020874SLiviu Dudau		reg = <0x00000000 0x80000000 0x0 0x7f000000>,
242e8020874SLiviu Dudau		      <0x00000008 0x80000000 0x1 0x80000000>;
243e8020874SLiviu Dudau	};
244e8020874SLiviu Dudau
245*6d6acd14SSudeep Holla	smb@08000000 {
246e8020874SLiviu Dudau		compatible = "simple-bus";
247e8020874SLiviu Dudau		#address-cells = <2>;
248e8020874SLiviu Dudau		#size-cells = <1>;
249e8020874SLiviu Dudau		ranges = <0 0 0 0x08000000 0x04000000>,
250e8020874SLiviu Dudau			 <1 0 0 0x14000000 0x04000000>,
251e8020874SLiviu Dudau			 <2 0 0 0x18000000 0x04000000>,
252e8020874SLiviu Dudau			 <3 0 0 0x1c000000 0x04000000>,
253e8020874SLiviu Dudau			 <4 0 0 0x0c000000 0x04000000>,
254e8020874SLiviu Dudau			 <5 0 0 0x10000000 0x04000000>;
255e8020874SLiviu Dudau
256e8020874SLiviu Dudau		#interrupt-cells = <1>;
257e8020874SLiviu Dudau		interrupt-map-mask = <0 0 15>;
2589e6f374fSLiviu Dudau		interrupt-map = <0 0  0 &gic 0 0 0  68 IRQ_TYPE_LEVEL_HIGH>,
2599e6f374fSLiviu Dudau				<0 0  1 &gic 0 0 0  69 IRQ_TYPE_LEVEL_HIGH>,
2609e6f374fSLiviu Dudau				<0 0  2 &gic 0 0 0  70 IRQ_TYPE_LEVEL_HIGH>,
2619e6f374fSLiviu Dudau				<0 0  3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
2629e6f374fSLiviu Dudau				<0 0  4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
2639e6f374fSLiviu Dudau				<0 0  5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
2649e6f374fSLiviu Dudau				<0 0  6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
2659e6f374fSLiviu Dudau				<0 0  7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
2669e6f374fSLiviu Dudau				<0 0  8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
2679e6f374fSLiviu Dudau				<0 0  9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
2689e6f374fSLiviu Dudau				<0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
2699e6f374fSLiviu Dudau				<0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
2709e6f374fSLiviu Dudau				<0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
271e8020874SLiviu Dudau
272e8020874SLiviu Dudau		/include/ "juno-motherboard.dtsi"
273e8020874SLiviu Dudau	};
274