1*05c618f3SKrzysztof Kozlowski// SPDX-License-Identifier: GPL-2.0 OR MIT 2a69d2774SRui Miguel Silva/* 3a69d2774SRui Miguel Silva * Copyright (c) 2022, Arm Limited. All rights reserved. 4a69d2774SRui Miguel Silva * Copyright (c) 2022, Linaro Limited. All rights reserved. 5a69d2774SRui Miguel Silva * 6a69d2774SRui Miguel Silva */ 7a69d2774SRui Miguel Silva 8a69d2774SRui Miguel Silva/dts-v1/; 9a69d2774SRui Miguel Silva 10a69d2774SRui Miguel Silva#include "corstone1000.dtsi" 11a69d2774SRui Miguel Silva 12a69d2774SRui Miguel Silva/ { 13a69d2774SRui Miguel Silva model = "ARM Corstone1000 FVP (Fixed Virtual Platform)"; 14a69d2774SRui Miguel Silva compatible = "arm,corstone1000-fvp"; 15a69d2774SRui Miguel Silva 16a69d2774SRui Miguel Silva smsc: ethernet@4010000 { 17a69d2774SRui Miguel Silva compatible = "smsc,lan91c111"; 18a69d2774SRui Miguel Silva reg = <0x40100000 0x10000>; 19a69d2774SRui Miguel Silva phy-mode = "mii"; 20a69d2774SRui Miguel Silva interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 21a69d2774SRui Miguel Silva reg-io-width = <2>; 22a69d2774SRui Miguel Silva }; 23a69d2774SRui Miguel Silva 24a69d2774SRui Miguel Silva vmmc_v3_3d: fixed_v3_3d { 25a69d2774SRui Miguel Silva compatible = "regulator-fixed"; 26a69d2774SRui Miguel Silva regulator-name = "vmmc_supply"; 27a69d2774SRui Miguel Silva regulator-min-microvolt = <3300000>; 28a69d2774SRui Miguel Silva regulator-max-microvolt = <3300000>; 29a69d2774SRui Miguel Silva regulator-always-on; 30a69d2774SRui Miguel Silva }; 31a69d2774SRui Miguel Silva 32a69d2774SRui Miguel Silva sdmmc0: mmc@40300000 { 33a69d2774SRui Miguel Silva compatible = "arm,pl18x", "arm,primecell"; 34a69d2774SRui Miguel Silva reg = <0x40300000 0x1000>; 35a69d2774SRui Miguel Silva interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 36a69d2774SRui Miguel Silva max-frequency = <12000000>; 37a69d2774SRui Miguel Silva vmmc-supply = <&vmmc_v3_3d>; 38a69d2774SRui Miguel Silva clocks = <&smbclk>, <&refclk100mhz>; 39a69d2774SRui Miguel Silva clock-names = "smclk", "apb_pclk"; 40a69d2774SRui Miguel Silva }; 41a69d2774SRui Miguel Silva 42a69d2774SRui Miguel Silva sdmmc1: mmc@50000000 { 43a69d2774SRui Miguel Silva compatible = "arm,pl18x", "arm,primecell"; 44a69d2774SRui Miguel Silva reg = <0x50000000 0x10000>; 45a69d2774SRui Miguel Silva interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 46a69d2774SRui Miguel Silva max-frequency = <12000000>; 47a69d2774SRui Miguel Silva vmmc-supply = <&vmmc_v3_3d>; 48a69d2774SRui Miguel Silva clocks = <&smbclk>, <&refclk100mhz>; 49a69d2774SRui Miguel Silva clock-names = "smclk", "apb_pclk"; 50a69d2774SRui Miguel Silva }; 51a69d2774SRui Miguel Silva}; 52