1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8103 "M1" SoC 4 * 5 * Other names: H13G, "Tonga" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/interrupt-controller/apple-aic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/pinctrl/apple.h> 13 14/ { 15 compatible = "apple,t8103", "apple,arm-platform"; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <2>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "apple,icestorm"; 26 device_type = "cpu"; 27 reg = <0x0 0x0>; 28 enable-method = "spin-table"; 29 cpu-release-addr = <0 0>; /* To be filled by loader */ 30 }; 31 32 cpu1: cpu@1 { 33 compatible = "apple,icestorm"; 34 device_type = "cpu"; 35 reg = <0x0 0x1>; 36 enable-method = "spin-table"; 37 cpu-release-addr = <0 0>; /* To be filled by loader */ 38 }; 39 40 cpu2: cpu@2 { 41 compatible = "apple,icestorm"; 42 device_type = "cpu"; 43 reg = <0x0 0x2>; 44 enable-method = "spin-table"; 45 cpu-release-addr = <0 0>; /* To be filled by loader */ 46 }; 47 48 cpu3: cpu@3 { 49 compatible = "apple,icestorm"; 50 device_type = "cpu"; 51 reg = <0x0 0x3>; 52 enable-method = "spin-table"; 53 cpu-release-addr = <0 0>; /* To be filled by loader */ 54 }; 55 56 cpu4: cpu@10100 { 57 compatible = "apple,firestorm"; 58 device_type = "cpu"; 59 reg = <0x0 0x10100>; 60 enable-method = "spin-table"; 61 cpu-release-addr = <0 0>; /* To be filled by loader */ 62 }; 63 64 cpu5: cpu@10101 { 65 compatible = "apple,firestorm"; 66 device_type = "cpu"; 67 reg = <0x0 0x10101>; 68 enable-method = "spin-table"; 69 cpu-release-addr = <0 0>; /* To be filled by loader */ 70 }; 71 72 cpu6: cpu@10102 { 73 compatible = "apple,firestorm"; 74 device_type = "cpu"; 75 reg = <0x0 0x10102>; 76 enable-method = "spin-table"; 77 cpu-release-addr = <0 0>; /* To be filled by loader */ 78 }; 79 80 cpu7: cpu@10103 { 81 compatible = "apple,firestorm"; 82 device_type = "cpu"; 83 reg = <0x0 0x10103>; 84 enable-method = "spin-table"; 85 cpu-release-addr = <0 0>; /* To be filled by loader */ 86 }; 87 }; 88 89 timer { 90 compatible = "arm,armv8-timer"; 91 interrupt-parent = <&aic>; 92 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 93 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 94 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 95 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 96 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 97 }; 98 99 clk24: clock-24m { 100 compatible = "fixed-clock"; 101 #clock-cells = <0>; 102 clock-frequency = <24000000>; 103 clock-output-names = "clk24"; 104 }; 105 106 soc { 107 compatible = "simple-bus"; 108 #address-cells = <2>; 109 #size-cells = <2>; 110 111 ranges; 112 nonposted-mmio; 113 114 i2c0: i2c@235010000 { 115 compatible = "apple,t8103-i2c", "apple,i2c"; 116 reg = <0x2 0x35010000 0x0 0x4000>; 117 clocks = <&clk24>; 118 interrupt-parent = <&aic>; 119 interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>; 120 pinctrl-0 = <&i2c0_pins>; 121 pinctrl-names = "default"; 122 #address-cells = <0x1>; 123 #size-cells = <0x0>; 124 }; 125 126 i2c1: i2c@235014000 { 127 compatible = "apple,t8103-i2c", "apple,i2c"; 128 reg = <0x2 0x35014000 0x0 0x4000>; 129 clocks = <&clk24>; 130 interrupt-parent = <&aic>; 131 interrupts = <AIC_IRQ 628 IRQ_TYPE_LEVEL_HIGH>; 132 pinctrl-0 = <&i2c1_pins>; 133 pinctrl-names = "default"; 134 #address-cells = <0x1>; 135 #size-cells = <0x0>; 136 }; 137 138 i2c2: i2c@235018000 { 139 compatible = "apple,t8103-i2c", "apple,i2c"; 140 reg = <0x2 0x35018000 0x0 0x4000>; 141 clocks = <&clk24>; 142 interrupt-parent = <&aic>; 143 interrupts = <AIC_IRQ 629 IRQ_TYPE_LEVEL_HIGH>; 144 pinctrl-0 = <&i2c2_pins>; 145 pinctrl-names = "default"; 146 #address-cells = <0x1>; 147 #size-cells = <0x0>; 148 status = "disabled"; /* not used in all devices */ 149 }; 150 151 i2c3: i2c@23501c000 { 152 compatible = "apple,t8103-i2c", "apple,i2c"; 153 reg = <0x2 0x3501c000 0x0 0x4000>; 154 clocks = <&clk24>; 155 interrupt-parent = <&aic>; 156 interrupts = <AIC_IRQ 630 IRQ_TYPE_LEVEL_HIGH>; 157 pinctrl-0 = <&i2c3_pins>; 158 pinctrl-names = "default"; 159 #address-cells = <0x1>; 160 #size-cells = <0x0>; 161 }; 162 163 i2c4: i2c@235020000 { 164 compatible = "apple,t8103-i2c", "apple,i2c"; 165 reg = <0x2 0x35020000 0x0 0x4000>; 166 clocks = <&clk24>; 167 interrupt-parent = <&aic>; 168 interrupts = <AIC_IRQ 631 IRQ_TYPE_LEVEL_HIGH>; 169 pinctrl-0 = <&i2c4_pins>; 170 pinctrl-names = "default"; 171 #address-cells = <0x1>; 172 #size-cells = <0x0>; 173 status = "disabled"; /* only used in J293 */ 174 }; 175 176 serial0: serial@235200000 { 177 compatible = "apple,s5l-uart"; 178 reg = <0x2 0x35200000 0x0 0x1000>; 179 reg-io-width = <4>; 180 interrupt-parent = <&aic>; 181 interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>; 182 /* 183 * TODO: figure out the clocking properly, there may 184 * be a third selectable clock. 185 */ 186 clocks = <&clk24>, <&clk24>; 187 clock-names = "uart", "clk_uart_baud0"; 188 status = "disabled"; 189 }; 190 191 aic: interrupt-controller@23b100000 { 192 compatible = "apple,t8103-aic", "apple,aic"; 193 #interrupt-cells = <3>; 194 interrupt-controller; 195 reg = <0x2 0x3b100000 0x0 0x8000>; 196 }; 197 198 pinctrl_ap: pinctrl@23c100000 { 199 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 200 reg = <0x2 0x3c100000 0x0 0x100000>; 201 202 gpio-controller; 203 #gpio-cells = <2>; 204 gpio-ranges = <&pinctrl_ap 0 0 212>; 205 apple,npins = <212>; 206 207 interrupt-controller; 208 #interrupt-cells = <2>; 209 interrupt-parent = <&aic>; 210 interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>, 211 <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>, 212 <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>, 213 <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>, 214 <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>, 215 <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, 216 <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>; 217 218 i2c0_pins: i2c0-pins { 219 pinmux = <APPLE_PINMUX(192, 1)>, 220 <APPLE_PINMUX(188, 1)>; 221 }; 222 223 i2c1_pins: i2c1-pins { 224 pinmux = <APPLE_PINMUX(201, 1)>, 225 <APPLE_PINMUX(199, 1)>; 226 }; 227 228 i2c2_pins: i2c2-pins { 229 pinmux = <APPLE_PINMUX(163, 1)>, 230 <APPLE_PINMUX(162, 1)>; 231 }; 232 233 i2c3_pins: i2c3-pins { 234 pinmux = <APPLE_PINMUX(73, 1)>, 235 <APPLE_PINMUX(72, 1)>; 236 }; 237 238 i2c4_pins: i2c4-pins { 239 pinmux = <APPLE_PINMUX(135, 1)>, 240 <APPLE_PINMUX(134, 1)>; 241 }; 242 243 pcie_pins: pcie-pins { 244 pinmux = <APPLE_PINMUX(150, 1)>, 245 <APPLE_PINMUX(151, 1)>, 246 <APPLE_PINMUX(32, 1)>; 247 }; 248 }; 249 250 pinctrl_aop: pinctrl@24a820000 { 251 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 252 reg = <0x2 0x4a820000 0x0 0x4000>; 253 254 gpio-controller; 255 #gpio-cells = <2>; 256 gpio-ranges = <&pinctrl_aop 0 0 42>; 257 apple,npins = <42>; 258 259 interrupt-controller; 260 #interrupt-cells = <2>; 261 interrupt-parent = <&aic>; 262 interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>, 263 <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>, 264 <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>, 265 <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>, 266 <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>, 267 <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, 268 <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>; 269 }; 270 271 pinctrl_nub: pinctrl@23d1f0000 { 272 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 273 reg = <0x2 0x3d1f0000 0x0 0x4000>; 274 275 gpio-controller; 276 #gpio-cells = <2>; 277 gpio-ranges = <&pinctrl_nub 0 0 23>; 278 apple,npins = <23>; 279 280 interrupt-controller; 281 #interrupt-cells = <2>; 282 interrupt-parent = <&aic>; 283 interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>, 284 <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>, 285 <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>, 286 <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>, 287 <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>, 288 <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>, 289 <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>; 290 }; 291 292 pinctrl_smc: pinctrl@23e820000 { 293 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 294 reg = <0x2 0x3e820000 0x0 0x4000>; 295 296 gpio-controller; 297 #gpio-cells = <2>; 298 gpio-ranges = <&pinctrl_smc 0 0 16>; 299 apple,npins = <16>; 300 301 interrupt-controller; 302 #interrupt-cells = <2>; 303 interrupt-parent = <&aic>; 304 interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>, 305 <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>, 306 <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>, 307 <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>, 308 <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>, 309 <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>, 310 <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>; 311 }; 312 313 pcie0_dart_0: dart@681008000 { 314 compatible = "apple,t8103-dart"; 315 reg = <0x6 0x81008000 0x0 0x4000>; 316 #iommu-cells = <1>; 317 interrupt-parent = <&aic>; 318 interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>; 319 }; 320 321 pcie0_dart_1: dart@682008000 { 322 compatible = "apple,t8103-dart"; 323 reg = <0x6 0x82008000 0x0 0x4000>; 324 #iommu-cells = <1>; 325 interrupt-parent = <&aic>; 326 interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>; 327 }; 328 329 pcie0_dart_2: dart@683008000 { 330 compatible = "apple,t8103-dart"; 331 reg = <0x6 0x83008000 0x0 0x4000>; 332 #iommu-cells = <1>; 333 interrupt-parent = <&aic>; 334 interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>; 335 }; 336 337 pcie0: pcie@690000000 { 338 compatible = "apple,t8103-pcie", "apple,pcie"; 339 device_type = "pci"; 340 341 reg = <0x6 0x90000000 0x0 0x1000000>, 342 <0x6 0x80000000 0x0 0x100000>, 343 <0x6 0x81000000 0x0 0x4000>, 344 <0x6 0x82000000 0x0 0x4000>, 345 <0x6 0x83000000 0x0 0x4000>; 346 reg-names = "config", "rc", "port0", "port1", "port2"; 347 348 interrupt-parent = <&aic>; 349 interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, 350 <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, 351 <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; 352 353 msi-controller; 354 msi-parent = <&pcie0>; 355 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; 356 357 358 iommu-map = <0x100 &pcie0_dart_0 1 1>, 359 <0x200 &pcie0_dart_1 1 1>, 360 <0x300 &pcie0_dart_2 1 1>; 361 iommu-map-mask = <0xff00>; 362 363 bus-range = <0 3>; 364 #address-cells = <3>; 365 #size-cells = <2>; 366 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, 367 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; 368 369 pinctrl-0 = <&pcie_pins>; 370 pinctrl-names = "default"; 371 372 port00: pci@0,0 { 373 device_type = "pci"; 374 reg = <0x0 0x0 0x0 0x0 0x0>; 375 reset-gpios = <&pinctrl_ap 152 0>; 376 max-link-speed = <2>; 377 378 #address-cells = <3>; 379 #size-cells = <2>; 380 ranges; 381 382 interrupt-controller; 383 #interrupt-cells = <1>; 384 385 interrupt-map-mask = <0 0 0 7>; 386 interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 387 <0 0 0 2 &port00 0 0 0 1>, 388 <0 0 0 3 &port00 0 0 0 2>, 389 <0 0 0 4 &port00 0 0 0 3>; 390 }; 391 392 port01: pci@1,0 { 393 device_type = "pci"; 394 reg = <0x800 0x0 0x0 0x0 0x0>; 395 reset-gpios = <&pinctrl_ap 153 0>; 396 max-link-speed = <2>; 397 398 #address-cells = <3>; 399 #size-cells = <2>; 400 ranges; 401 402 interrupt-controller; 403 #interrupt-cells = <1>; 404 405 interrupt-map-mask = <0 0 0 7>; 406 interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 407 <0 0 0 2 &port01 0 0 0 1>, 408 <0 0 0 3 &port01 0 0 0 2>, 409 <0 0 0 4 &port01 0 0 0 3>; 410 }; 411 412 port02: pci@2,0 { 413 device_type = "pci"; 414 reg = <0x1000 0x0 0x0 0x0 0x0>; 415 reset-gpios = <&pinctrl_ap 33 0>; 416 max-link-speed = <1>; 417 418 #address-cells = <3>; 419 #size-cells = <2>; 420 ranges; 421 422 interrupt-controller; 423 #interrupt-cells = <1>; 424 425 interrupt-map-mask = <0 0 0 7>; 426 interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 427 <0 0 0 2 &port02 0 0 0 1>, 428 <0 0 0 3 &port02 0 0 0 2>, 429 <0 0 0 4 &port02 0 0 0 3>; 430 }; 431 }; 432 }; 433}; 434