1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8103 "M1" SoC 4 * 5 * Other names: H13G, "Tonga" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 compatible = "apple,t8103", "apple,arm-platform"; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <2>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu_e0>; 29 }; 30 core1 { 31 cpu = <&cpu_e1>; 32 }; 33 core2 { 34 cpu = <&cpu_e2>; 35 }; 36 core3 { 37 cpu = <&cpu_e3>; 38 }; 39 }; 40 41 cluster1 { 42 core0 { 43 cpu = <&cpu_p0>; 44 }; 45 core1 { 46 cpu = <&cpu_p1>; 47 }; 48 core2 { 49 cpu = <&cpu_p2>; 50 }; 51 core3 { 52 cpu = <&cpu_p3>; 53 }; 54 }; 55 }; 56 57 cpu_e0: cpu@0 { 58 compatible = "apple,icestorm"; 59 device_type = "cpu"; 60 reg = <0x0 0x0>; 61 enable-method = "spin-table"; 62 cpu-release-addr = <0 0>; /* To be filled by loader */ 63 operating-points-v2 = <&ecluster_opp>; 64 capacity-dmips-mhz = <714>; 65 performance-domains = <&cpufreq_e>; 66 }; 67 68 cpu_e1: cpu@1 { 69 compatible = "apple,icestorm"; 70 device_type = "cpu"; 71 reg = <0x0 0x1>; 72 enable-method = "spin-table"; 73 cpu-release-addr = <0 0>; /* To be filled by loader */ 74 operating-points-v2 = <&ecluster_opp>; 75 capacity-dmips-mhz = <714>; 76 performance-domains = <&cpufreq_e>; 77 }; 78 79 cpu_e2: cpu@2 { 80 compatible = "apple,icestorm"; 81 device_type = "cpu"; 82 reg = <0x0 0x2>; 83 enable-method = "spin-table"; 84 cpu-release-addr = <0 0>; /* To be filled by loader */ 85 operating-points-v2 = <&ecluster_opp>; 86 capacity-dmips-mhz = <714>; 87 performance-domains = <&cpufreq_e>; 88 }; 89 90 cpu_e3: cpu@3 { 91 compatible = "apple,icestorm"; 92 device_type = "cpu"; 93 reg = <0x0 0x3>; 94 enable-method = "spin-table"; 95 cpu-release-addr = <0 0>; /* To be filled by loader */ 96 operating-points-v2 = <&ecluster_opp>; 97 capacity-dmips-mhz = <714>; 98 performance-domains = <&cpufreq_e>; 99 }; 100 101 cpu_p0: cpu@10100 { 102 compatible = "apple,firestorm"; 103 device_type = "cpu"; 104 reg = <0x0 0x10100>; 105 enable-method = "spin-table"; 106 cpu-release-addr = <0 0>; /* To be filled by loader */ 107 operating-points-v2 = <&pcluster_opp>; 108 capacity-dmips-mhz = <1024>; 109 performance-domains = <&cpufreq_p>; 110 }; 111 112 cpu_p1: cpu@10101 { 113 compatible = "apple,firestorm"; 114 device_type = "cpu"; 115 reg = <0x0 0x10101>; 116 enable-method = "spin-table"; 117 cpu-release-addr = <0 0>; /* To be filled by loader */ 118 operating-points-v2 = <&pcluster_opp>; 119 capacity-dmips-mhz = <1024>; 120 performance-domains = <&cpufreq_p>; 121 }; 122 123 cpu_p2: cpu@10102 { 124 compatible = "apple,firestorm"; 125 device_type = "cpu"; 126 reg = <0x0 0x10102>; 127 enable-method = "spin-table"; 128 cpu-release-addr = <0 0>; /* To be filled by loader */ 129 operating-points-v2 = <&pcluster_opp>; 130 capacity-dmips-mhz = <1024>; 131 performance-domains = <&cpufreq_p>; 132 }; 133 134 cpu_p3: cpu@10103 { 135 compatible = "apple,firestorm"; 136 device_type = "cpu"; 137 reg = <0x0 0x10103>; 138 enable-method = "spin-table"; 139 cpu-release-addr = <0 0>; /* To be filled by loader */ 140 operating-points-v2 = <&pcluster_opp>; 141 capacity-dmips-mhz = <1024>; 142 performance-domains = <&cpufreq_p>; 143 }; 144 }; 145 146 ecluster_opp: opp-table-0 { 147 compatible = "operating-points-v2"; 148 149 opp01 { 150 opp-hz = /bits/ 64 <600000000>; 151 opp-level = <1>; 152 clock-latency-ns = <7500>; 153 }; 154 opp02 { 155 opp-hz = /bits/ 64 <972000000>; 156 opp-level = <2>; 157 clock-latency-ns = <22000>; 158 }; 159 opp03 { 160 opp-hz = /bits/ 64 <1332000000>; 161 opp-level = <3>; 162 clock-latency-ns = <27000>; 163 }; 164 opp04 { 165 opp-hz = /bits/ 64 <1704000000>; 166 opp-level = <4>; 167 clock-latency-ns = <33000>; 168 }; 169 opp05 { 170 opp-hz = /bits/ 64 <2064000000>; 171 opp-level = <5>; 172 clock-latency-ns = <50000>; 173 }; 174 }; 175 176 pcluster_opp: opp-table-1 { 177 compatible = "operating-points-v2"; 178 179 opp01 { 180 opp-hz = /bits/ 64 <600000000>; 181 opp-level = <1>; 182 clock-latency-ns = <8000>; 183 }; 184 opp02 { 185 opp-hz = /bits/ 64 <828000000>; 186 opp-level = <2>; 187 clock-latency-ns = <19000>; 188 }; 189 opp03 { 190 opp-hz = /bits/ 64 <1056000000>; 191 opp-level = <3>; 192 clock-latency-ns = <21000>; 193 }; 194 opp04 { 195 opp-hz = /bits/ 64 <1284000000>; 196 opp-level = <4>; 197 clock-latency-ns = <23000>; 198 }; 199 opp05 { 200 opp-hz = /bits/ 64 <1500000000>; 201 opp-level = <5>; 202 clock-latency-ns = <24000>; 203 }; 204 opp06 { 205 opp-hz = /bits/ 64 <1728000000>; 206 opp-level = <6>; 207 clock-latency-ns = <29000>; 208 }; 209 opp07 { 210 opp-hz = /bits/ 64 <1956000000>; 211 opp-level = <7>; 212 clock-latency-ns = <31000>; 213 }; 214 opp08 { 215 opp-hz = /bits/ 64 <2184000000>; 216 opp-level = <8>; 217 clock-latency-ns = <34000>; 218 }; 219 opp09 { 220 opp-hz = /bits/ 64 <2388000000>; 221 opp-level = <9>; 222 clock-latency-ns = <36000>; 223 }; 224 opp10 { 225 opp-hz = /bits/ 64 <2592000000>; 226 opp-level = <10>; 227 clock-latency-ns = <51000>; 228 }; 229 opp11 { 230 opp-hz = /bits/ 64 <2772000000>; 231 opp-level = <11>; 232 clock-latency-ns = <54000>; 233 }; 234 opp12 { 235 opp-hz = /bits/ 64 <2988000000>; 236 opp-level = <12>; 237 clock-latency-ns = <55000>; 238 }; 239#if 0 240 /* Not available until CPU deep sleep is implemented */ 241 opp13 { 242 opp-hz = /bits/ 64 <3096000000>; 243 opp-level = <13>; 244 clock-latency-ns = <55000>; 245 turbo-mode; 246 }; 247 opp14 { 248 opp-hz = /bits/ 64 <3144000000>; 249 opp-level = <14>; 250 clock-latency-ns = <56000>; 251 turbo-mode; 252 }; 253 opp15 { 254 opp-hz = /bits/ 64 <3204000000>; 255 opp-level = <15>; 256 clock-latency-ns = <56000>; 257 turbo-mode; 258 }; 259#endif 260 }; 261 262 timer { 263 compatible = "arm,armv8-timer"; 264 interrupt-parent = <&aic>; 265 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 266 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 267 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 268 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 269 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 270 }; 271 272 pmu-e { 273 compatible = "apple,icestorm-pmu"; 274 interrupt-parent = <&aic>; 275 interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>; 276 }; 277 278 pmu-p { 279 compatible = "apple,firestorm-pmu"; 280 interrupt-parent = <&aic>; 281 interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>; 282 }; 283 284 clkref: clock-ref { 285 compatible = "fixed-clock"; 286 #clock-cells = <0>; 287 clock-frequency = <24000000>; 288 clock-output-names = "clkref"; 289 }; 290 291 /* 292 * This is a fabulated representation of the input clock 293 * to NCO since we don't know the true clock tree. 294 */ 295 nco_clkref: clock-ref-nco { 296 compatible = "fixed-clock"; 297 #clock-cells = <0>; 298 clock-output-names = "nco_ref"; 299 }; 300 301 soc { 302 compatible = "simple-bus"; 303 #address-cells = <2>; 304 #size-cells = <2>; 305 306 ranges; 307 nonposted-mmio; 308 309 cpufreq_e: performance-controller@210e20000 { 310 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 311 reg = <0x2 0x10e20000 0 0x1000>; 312 #performance-domain-cells = <0>; 313 }; 314 315 cpufreq_p: performance-controller@211e20000 { 316 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 317 reg = <0x2 0x11e20000 0 0x1000>; 318 #performance-domain-cells = <0>; 319 }; 320 321 sio_dart: iommu@235004000 { 322 compatible = "apple,t8103-dart"; 323 reg = <0x2 0x35004000 0x0 0x4000>; 324 interrupt-parent = <&aic>; 325 interrupts = <AIC_IRQ 635 IRQ_TYPE_LEVEL_HIGH>; 326 #iommu-cells = <1>; 327 power-domains = <&ps_sio_cpu>; 328 }; 329 330 i2c0: i2c@235010000 { 331 compatible = "apple,t8103-i2c", "apple,i2c"; 332 reg = <0x2 0x35010000 0x0 0x4000>; 333 clocks = <&clkref>; 334 interrupt-parent = <&aic>; 335 interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>; 336 pinctrl-0 = <&i2c0_pins>; 337 pinctrl-names = "default"; 338 #address-cells = <0x1>; 339 #size-cells = <0x0>; 340 power-domains = <&ps_i2c0>; 341 }; 342 343 i2c1: i2c@235014000 { 344 compatible = "apple,t8103-i2c", "apple,i2c"; 345 reg = <0x2 0x35014000 0x0 0x4000>; 346 clocks = <&clkref>; 347 interrupt-parent = <&aic>; 348 interrupts = <AIC_IRQ 628 IRQ_TYPE_LEVEL_HIGH>; 349 pinctrl-0 = <&i2c1_pins>; 350 pinctrl-names = "default"; 351 #address-cells = <0x1>; 352 #size-cells = <0x0>; 353 power-domains = <&ps_i2c1>; 354 }; 355 356 i2c2: i2c@235018000 { 357 compatible = "apple,t8103-i2c", "apple,i2c"; 358 reg = <0x2 0x35018000 0x0 0x4000>; 359 clocks = <&clkref>; 360 interrupt-parent = <&aic>; 361 interrupts = <AIC_IRQ 629 IRQ_TYPE_LEVEL_HIGH>; 362 pinctrl-0 = <&i2c2_pins>; 363 pinctrl-names = "default"; 364 #address-cells = <0x1>; 365 #size-cells = <0x0>; 366 status = "disabled"; /* not used in all devices */ 367 power-domains = <&ps_i2c2>; 368 }; 369 370 i2c3: i2c@23501c000 { 371 compatible = "apple,t8103-i2c", "apple,i2c"; 372 reg = <0x2 0x3501c000 0x0 0x4000>; 373 clocks = <&clkref>; 374 interrupt-parent = <&aic>; 375 interrupts = <AIC_IRQ 630 IRQ_TYPE_LEVEL_HIGH>; 376 pinctrl-0 = <&i2c3_pins>; 377 pinctrl-names = "default"; 378 #address-cells = <0x1>; 379 #size-cells = <0x0>; 380 power-domains = <&ps_i2c3>; 381 }; 382 383 i2c4: i2c@235020000 { 384 compatible = "apple,t8103-i2c", "apple,i2c"; 385 reg = <0x2 0x35020000 0x0 0x4000>; 386 clocks = <&clkref>; 387 interrupt-parent = <&aic>; 388 interrupts = <AIC_IRQ 631 IRQ_TYPE_LEVEL_HIGH>; 389 pinctrl-0 = <&i2c4_pins>; 390 pinctrl-names = "default"; 391 #address-cells = <0x1>; 392 #size-cells = <0x0>; 393 power-domains = <&ps_i2c4>; 394 status = "disabled"; /* only used in J293 */ 395 }; 396 397 serial0: serial@235200000 { 398 compatible = "apple,s5l-uart"; 399 reg = <0x2 0x35200000 0x0 0x1000>; 400 reg-io-width = <4>; 401 interrupt-parent = <&aic>; 402 interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>; 403 /* 404 * TODO: figure out the clocking properly, there may 405 * be a third selectable clock. 406 */ 407 clocks = <&clkref>, <&clkref>; 408 clock-names = "uart", "clk_uart_baud0"; 409 power-domains = <&ps_uart0>; 410 status = "disabled"; 411 }; 412 413 serial2: serial@235208000 { 414 compatible = "apple,s5l-uart"; 415 reg = <0x2 0x35208000 0x0 0x1000>; 416 reg-io-width = <4>; 417 interrupt-parent = <&aic>; 418 interrupts = <AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&clkref>, <&clkref>; 420 clock-names = "uart", "clk_uart_baud0"; 421 power-domains = <&ps_uart2>; 422 status = "disabled"; 423 }; 424 425 admac: dma-controller@238200000 { 426 compatible = "apple,t8103-admac", "apple,admac"; 427 reg = <0x2 0x38200000 0x0 0x34000>; 428 dma-channels = <24>; 429 interrupts-extended = <0>, 430 <&aic AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>, 431 <0>, 432 <0>; 433 #dma-cells = <1>; 434 iommus = <&sio_dart 2>; 435 power-domains = <&ps_sio_adma>; 436 resets = <&ps_audio_p>; 437 }; 438 439 mca: i2s@238400000 { 440 compatible = "apple,t8103-mca", "apple,mca"; 441 reg = <0x2 0x38400000 0x0 0x18000>, 442 <0x2 0x38300000 0x0 0x30000>; 443 444 interrupt-parent = <&aic>; 445 interrupts = <AIC_IRQ 619 IRQ_TYPE_LEVEL_HIGH>, 446 <AIC_IRQ 620 IRQ_TYPE_LEVEL_HIGH>, 447 <AIC_IRQ 621 IRQ_TYPE_LEVEL_HIGH>, 448 <AIC_IRQ 622 IRQ_TYPE_LEVEL_HIGH>, 449 <AIC_IRQ 623 IRQ_TYPE_LEVEL_HIGH>, 450 <AIC_IRQ 624 IRQ_TYPE_LEVEL_HIGH>; 451 452 resets = <&ps_audio_p>; 453 clocks = <&nco 0>, <&nco 1>, <&nco 2>, 454 <&nco 3>, <&nco 4>, <&nco 4>; 455 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, 456 <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; 457 dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, 458 <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, 459 <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, 460 <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>, 461 <&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>, 462 <&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>; 463 dma-names = "tx0a", "rx0a", "tx0b", "rx0b", 464 "tx1a", "rx1a", "tx1b", "rx1b", 465 "tx2a", "rx2a", "tx2b", "rx2b", 466 "tx3a", "rx3a", "tx3b", "rx3b", 467 "tx4a", "rx4a", "tx4b", "rx4b", 468 "tx5a", "rx5a", "tx5b", "rx5b"; 469 470 #sound-dai-cells = <1>; 471 }; 472 473 nco: clock-controller@23b044000 { 474 compatible = "apple,t8103-nco", "apple,nco"; 475 reg = <0x2 0x3b044000 0x0 0x14000>; 476 clocks = <&nco_clkref>; 477 #clock-cells = <1>; 478 }; 479 480 aic: interrupt-controller@23b100000 { 481 compatible = "apple,t8103-aic", "apple,aic"; 482 #interrupt-cells = <3>; 483 interrupt-controller; 484 reg = <0x2 0x3b100000 0x0 0x8000>; 485 power-domains = <&ps_aic>; 486 487 affinities { 488 e-core-pmu-affinity { 489 apple,fiq-index = <AIC_CPU_PMU_E>; 490 cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; 491 }; 492 493 p-core-pmu-affinity { 494 apple,fiq-index = <AIC_CPU_PMU_P>; 495 cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>; 496 }; 497 }; 498 }; 499 500 pmgr: power-management@23b700000 { 501 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 502 #address-cells = <1>; 503 #size-cells = <1>; 504 reg = <0x2 0x3b700000 0 0x14000>; 505 }; 506 507 pinctrl_ap: pinctrl@23c100000 { 508 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 509 reg = <0x2 0x3c100000 0x0 0x100000>; 510 power-domains = <&ps_gpio>; 511 512 gpio-controller; 513 #gpio-cells = <2>; 514 gpio-ranges = <&pinctrl_ap 0 0 212>; 515 apple,npins = <212>; 516 517 interrupt-controller; 518 #interrupt-cells = <2>; 519 interrupt-parent = <&aic>; 520 interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>, 521 <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>, 522 <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>, 523 <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>, 524 <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>, 525 <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, 526 <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>; 527 528 i2c0_pins: i2c0-pins { 529 pinmux = <APPLE_PINMUX(192, 1)>, 530 <APPLE_PINMUX(188, 1)>; 531 }; 532 533 i2c1_pins: i2c1-pins { 534 pinmux = <APPLE_PINMUX(201, 1)>, 535 <APPLE_PINMUX(199, 1)>; 536 }; 537 538 i2c2_pins: i2c2-pins { 539 pinmux = <APPLE_PINMUX(163, 1)>, 540 <APPLE_PINMUX(162, 1)>; 541 }; 542 543 i2c3_pins: i2c3-pins { 544 pinmux = <APPLE_PINMUX(73, 1)>, 545 <APPLE_PINMUX(72, 1)>; 546 }; 547 548 i2c4_pins: i2c4-pins { 549 pinmux = <APPLE_PINMUX(135, 1)>, 550 <APPLE_PINMUX(134, 1)>; 551 }; 552 553 pcie_pins: pcie-pins { 554 pinmux = <APPLE_PINMUX(150, 1)>, 555 <APPLE_PINMUX(151, 1)>, 556 <APPLE_PINMUX(32, 1)>; 557 }; 558 }; 559 560 pinctrl_nub: pinctrl@23d1f0000 { 561 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 562 reg = <0x2 0x3d1f0000 0x0 0x4000>; 563 power-domains = <&ps_nub_gpio>; 564 565 gpio-controller; 566 #gpio-cells = <2>; 567 gpio-ranges = <&pinctrl_nub 0 0 23>; 568 apple,npins = <23>; 569 570 interrupt-controller; 571 #interrupt-cells = <2>; 572 interrupt-parent = <&aic>; 573 interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>, 574 <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>, 575 <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>, 576 <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>, 577 <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>, 578 <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>, 579 <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>; 580 }; 581 582 pmgr_mini: power-management@23d280000 { 583 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 584 #address-cells = <1>; 585 #size-cells = <1>; 586 reg = <0x2 0x3d280000 0 0x4000>; 587 }; 588 589 wdt: watchdog@23d2b0000 { 590 compatible = "apple,t8103-wdt", "apple,wdt"; 591 reg = <0x2 0x3d2b0000 0x0 0x4000>; 592 clocks = <&clkref>; 593 interrupt-parent = <&aic>; 594 interrupts = <AIC_IRQ 338 IRQ_TYPE_LEVEL_HIGH>; 595 }; 596 597 pinctrl_smc: pinctrl@23e820000 { 598 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 599 reg = <0x2 0x3e820000 0x0 0x4000>; 600 601 gpio-controller; 602 #gpio-cells = <2>; 603 gpio-ranges = <&pinctrl_smc 0 0 16>; 604 apple,npins = <16>; 605 606 interrupt-controller; 607 #interrupt-cells = <2>; 608 interrupt-parent = <&aic>; 609 interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>, 610 <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>, 611 <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>, 612 <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>, 613 <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>, 614 <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>, 615 <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>; 616 }; 617 618 pinctrl_aop: pinctrl@24a820000 { 619 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 620 reg = <0x2 0x4a820000 0x0 0x4000>; 621 622 gpio-controller; 623 #gpio-cells = <2>; 624 gpio-ranges = <&pinctrl_aop 0 0 42>; 625 apple,npins = <42>; 626 627 interrupt-controller; 628 #interrupt-cells = <2>; 629 interrupt-parent = <&aic>; 630 interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>, 631 <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>, 632 <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>, 633 <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>, 634 <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>, 635 <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, 636 <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>; 637 }; 638 639 ans_mbox: mbox@277408000 { 640 compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4"; 641 reg = <0x2 0x77408000 0x0 0x4000>; 642 interrupt-parent = <&aic>; 643 interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>, 644 <AIC_IRQ 584 IRQ_TYPE_LEVEL_HIGH>, 645 <AIC_IRQ 585 IRQ_TYPE_LEVEL_HIGH>, 646 <AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>; 647 interrupt-names = "send-empty", "send-not-empty", 648 "recv-empty", "recv-not-empty"; 649 #mbox-cells = <0>; 650 power-domains = <&ps_ans2>; 651 }; 652 653 sart: iommu@27bc50000 { 654 compatible = "apple,t8103-sart"; 655 reg = <0x2 0x7bc50000 0x0 0x10000>; 656 power-domains = <&ps_ans2>; 657 }; 658 659 nvme@27bcc0000 { 660 compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2"; 661 reg = <0x2 0x7bcc0000 0x0 0x40000>, 662 <0x2 0x77400000 0x0 0x4000>; 663 reg-names = "nvme", "ans"; 664 interrupt-parent = <&aic>; 665 interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>; 666 mboxes = <&ans_mbox>; 667 apple,sart = <&sart>; 668 power-domains = <&ps_ans2>, <&ps_apcie_st>; 669 power-domain-names = "ans", "apcie0"; 670 resets = <&ps_ans2>; 671 }; 672 673 pcie0_dart_0: iommu@681008000 { 674 compatible = "apple,t8103-dart"; 675 reg = <0x6 0x81008000 0x0 0x4000>; 676 #iommu-cells = <1>; 677 interrupt-parent = <&aic>; 678 interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>; 679 power-domains = <&ps_apcie_gp>; 680 }; 681 682 pcie0_dart_1: iommu@682008000 { 683 compatible = "apple,t8103-dart"; 684 reg = <0x6 0x82008000 0x0 0x4000>; 685 #iommu-cells = <1>; 686 interrupt-parent = <&aic>; 687 interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>; 688 power-domains = <&ps_apcie_gp>; 689 }; 690 691 pcie0_dart_2: iommu@683008000 { 692 compatible = "apple,t8103-dart"; 693 reg = <0x6 0x83008000 0x0 0x4000>; 694 #iommu-cells = <1>; 695 interrupt-parent = <&aic>; 696 interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>; 697 power-domains = <&ps_apcie_gp>; 698 }; 699 700 pcie0: pcie@690000000 { 701 compatible = "apple,t8103-pcie", "apple,pcie"; 702 device_type = "pci"; 703 704 reg = <0x6 0x90000000 0x0 0x1000000>, 705 <0x6 0x80000000 0x0 0x100000>, 706 <0x6 0x81000000 0x0 0x4000>, 707 <0x6 0x82000000 0x0 0x4000>, 708 <0x6 0x83000000 0x0 0x4000>; 709 reg-names = "config", "rc", "port0", "port1", "port2"; 710 711 interrupt-parent = <&aic>; 712 interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, 713 <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, 714 <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; 715 716 msi-controller; 717 msi-parent = <&pcie0>; 718 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; 719 720 721 iommu-map = <0x100 &pcie0_dart_0 1 1>, 722 <0x200 &pcie0_dart_1 1 1>, 723 <0x300 &pcie0_dart_2 1 1>; 724 iommu-map-mask = <0xff00>; 725 726 bus-range = <0 3>; 727 #address-cells = <3>; 728 #size-cells = <2>; 729 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, 730 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; 731 732 power-domains = <&ps_apcie_gp>; 733 pinctrl-0 = <&pcie_pins>; 734 pinctrl-names = "default"; 735 736 port00: pci@0,0 { 737 device_type = "pci"; 738 reg = <0x0 0x0 0x0 0x0 0x0>; 739 reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>; 740 741 #address-cells = <3>; 742 #size-cells = <2>; 743 ranges; 744 745 interrupt-controller; 746 #interrupt-cells = <1>; 747 748 interrupt-map-mask = <0 0 0 7>; 749 interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 750 <0 0 0 2 &port00 0 0 0 1>, 751 <0 0 0 3 &port00 0 0 0 2>, 752 <0 0 0 4 &port00 0 0 0 3>; 753 }; 754 755 port01: pci@1,0 { 756 device_type = "pci"; 757 reg = <0x800 0x0 0x0 0x0 0x0>; 758 reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>; 759 760 #address-cells = <3>; 761 #size-cells = <2>; 762 ranges; 763 764 interrupt-controller; 765 #interrupt-cells = <1>; 766 767 interrupt-map-mask = <0 0 0 7>; 768 interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 769 <0 0 0 2 &port01 0 0 0 1>, 770 <0 0 0 3 &port01 0 0 0 2>, 771 <0 0 0 4 &port01 0 0 0 3>; 772 }; 773 774 port02: pci@2,0 { 775 device_type = "pci"; 776 reg = <0x1000 0x0 0x0 0x0 0x0>; 777 reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>; 778 779 #address-cells = <3>; 780 #size-cells = <2>; 781 ranges; 782 783 interrupt-controller; 784 #interrupt-cells = <1>; 785 786 interrupt-map-mask = <0 0 0 7>; 787 interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 788 <0 0 0 2 &port02 0 0 0 1>, 789 <0 0 0 3 &port02 0 0 0 2>, 790 <0 0 0 4 &port02 0 0 0 3>; 791 }; 792 }; 793 }; 794}; 795 796#include "t8103-pmgr.dtsi" 797