1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8103 "M1" SoC 4 * 5 * Other names: H13G, "Tonga" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 compatible = "apple,t8103", "apple,arm-platform"; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <2>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 compatible = "apple,icestorm"; 27 device_type = "cpu"; 28 reg = <0x0 0x0>; 29 enable-method = "spin-table"; 30 cpu-release-addr = <0 0>; /* To be filled by loader */ 31 }; 32 33 cpu1: cpu@1 { 34 compatible = "apple,icestorm"; 35 device_type = "cpu"; 36 reg = <0x0 0x1>; 37 enable-method = "spin-table"; 38 cpu-release-addr = <0 0>; /* To be filled by loader */ 39 }; 40 41 cpu2: cpu@2 { 42 compatible = "apple,icestorm"; 43 device_type = "cpu"; 44 reg = <0x0 0x2>; 45 enable-method = "spin-table"; 46 cpu-release-addr = <0 0>; /* To be filled by loader */ 47 }; 48 49 cpu3: cpu@3 { 50 compatible = "apple,icestorm"; 51 device_type = "cpu"; 52 reg = <0x0 0x3>; 53 enable-method = "spin-table"; 54 cpu-release-addr = <0 0>; /* To be filled by loader */ 55 }; 56 57 cpu4: cpu@10100 { 58 compatible = "apple,firestorm"; 59 device_type = "cpu"; 60 reg = <0x0 0x10100>; 61 enable-method = "spin-table"; 62 cpu-release-addr = <0 0>; /* To be filled by loader */ 63 }; 64 65 cpu5: cpu@10101 { 66 compatible = "apple,firestorm"; 67 device_type = "cpu"; 68 reg = <0x0 0x10101>; 69 enable-method = "spin-table"; 70 cpu-release-addr = <0 0>; /* To be filled by loader */ 71 }; 72 73 cpu6: cpu@10102 { 74 compatible = "apple,firestorm"; 75 device_type = "cpu"; 76 reg = <0x0 0x10102>; 77 enable-method = "spin-table"; 78 cpu-release-addr = <0 0>; /* To be filled by loader */ 79 }; 80 81 cpu7: cpu@10103 { 82 compatible = "apple,firestorm"; 83 device_type = "cpu"; 84 reg = <0x0 0x10103>; 85 enable-method = "spin-table"; 86 cpu-release-addr = <0 0>; /* To be filled by loader */ 87 }; 88 }; 89 90 timer { 91 compatible = "arm,armv8-timer"; 92 interrupt-parent = <&aic>; 93 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 94 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 95 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 96 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 97 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 98 }; 99 100 pmu-e { 101 compatible = "apple,icestorm-pmu"; 102 interrupt-parent = <&aic>; 103 interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>; 104 }; 105 106 pmu-p { 107 compatible = "apple,firestorm-pmu"; 108 interrupt-parent = <&aic>; 109 interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>; 110 }; 111 112 clkref: clock-ref { 113 compatible = "fixed-clock"; 114 #clock-cells = <0>; 115 clock-frequency = <24000000>; 116 clock-output-names = "clkref"; 117 }; 118 119 /* 120 * This is a fabulated representation of the input clock 121 * to NCO since we don't know the true clock tree. 122 */ 123 nco_clkref: clock-ref-nco { 124 compatible = "fixed-clock"; 125 #clock-cells = <0>; 126 clock-output-names = "nco_ref"; 127 }; 128 129 soc { 130 compatible = "simple-bus"; 131 #address-cells = <2>; 132 #size-cells = <2>; 133 134 ranges; 135 nonposted-mmio; 136 137 dart_sio: iommu@235004000 { 138 compatible = "apple,t8103-dart"; 139 reg = <0x2 0x35004000 0x0 0x4000>; 140 interrupt-parent = <&aic>; 141 interrupts = <AIC_IRQ 635 IRQ_TYPE_LEVEL_HIGH>; 142 #iommu-cells = <1>; 143 power-domains = <&ps_sio_cpu>; 144 }; 145 146 i2c0: i2c@235010000 { 147 compatible = "apple,t8103-i2c", "apple,i2c"; 148 reg = <0x2 0x35010000 0x0 0x4000>; 149 clocks = <&clkref>; 150 interrupt-parent = <&aic>; 151 interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>; 152 pinctrl-0 = <&i2c0_pins>; 153 pinctrl-names = "default"; 154 #address-cells = <0x1>; 155 #size-cells = <0x0>; 156 power-domains = <&ps_i2c0>; 157 }; 158 159 i2c1: i2c@235014000 { 160 compatible = "apple,t8103-i2c", "apple,i2c"; 161 reg = <0x2 0x35014000 0x0 0x4000>; 162 clocks = <&clkref>; 163 interrupt-parent = <&aic>; 164 interrupts = <AIC_IRQ 628 IRQ_TYPE_LEVEL_HIGH>; 165 pinctrl-0 = <&i2c1_pins>; 166 pinctrl-names = "default"; 167 #address-cells = <0x1>; 168 #size-cells = <0x0>; 169 power-domains = <&ps_i2c1>; 170 }; 171 172 i2c2: i2c@235018000 { 173 compatible = "apple,t8103-i2c", "apple,i2c"; 174 reg = <0x2 0x35018000 0x0 0x4000>; 175 clocks = <&clkref>; 176 interrupt-parent = <&aic>; 177 interrupts = <AIC_IRQ 629 IRQ_TYPE_LEVEL_HIGH>; 178 pinctrl-0 = <&i2c2_pins>; 179 pinctrl-names = "default"; 180 #address-cells = <0x1>; 181 #size-cells = <0x0>; 182 status = "disabled"; /* not used in all devices */ 183 power-domains = <&ps_i2c2>; 184 }; 185 186 i2c3: i2c@23501c000 { 187 compatible = "apple,t8103-i2c", "apple,i2c"; 188 reg = <0x2 0x3501c000 0x0 0x4000>; 189 clocks = <&clkref>; 190 interrupt-parent = <&aic>; 191 interrupts = <AIC_IRQ 630 IRQ_TYPE_LEVEL_HIGH>; 192 pinctrl-0 = <&i2c3_pins>; 193 pinctrl-names = "default"; 194 #address-cells = <0x1>; 195 #size-cells = <0x0>; 196 power-domains = <&ps_i2c3>; 197 }; 198 199 i2c4: i2c@235020000 { 200 compatible = "apple,t8103-i2c", "apple,i2c"; 201 reg = <0x2 0x35020000 0x0 0x4000>; 202 clocks = <&clkref>; 203 interrupt-parent = <&aic>; 204 interrupts = <AIC_IRQ 631 IRQ_TYPE_LEVEL_HIGH>; 205 pinctrl-0 = <&i2c4_pins>; 206 pinctrl-names = "default"; 207 #address-cells = <0x1>; 208 #size-cells = <0x0>; 209 power-domains = <&ps_i2c4>; 210 status = "disabled"; /* only used in J293 */ 211 }; 212 213 serial0: serial@235200000 { 214 compatible = "apple,s5l-uart"; 215 reg = <0x2 0x35200000 0x0 0x1000>; 216 reg-io-width = <4>; 217 interrupt-parent = <&aic>; 218 interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>; 219 /* 220 * TODO: figure out the clocking properly, there may 221 * be a third selectable clock. 222 */ 223 clocks = <&clkref>, <&clkref>; 224 clock-names = "uart", "clk_uart_baud0"; 225 power-domains = <&ps_uart0>; 226 status = "disabled"; 227 }; 228 229 serial2: serial@235208000 { 230 compatible = "apple,s5l-uart"; 231 reg = <0x2 0x35208000 0x0 0x1000>; 232 reg-io-width = <4>; 233 interrupt-parent = <&aic>; 234 interrupts = <AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&clkref>, <&clkref>; 236 clock-names = "uart", "clk_uart_baud0"; 237 power-domains = <&ps_uart2>; 238 status = "disabled"; 239 }; 240 241 admac: dma-controller@238200000 { 242 compatible = "apple,t8103-admac", "apple,admac"; 243 reg = <0x2 0x38200000 0x0 0x34000>; 244 dma-channels = <24>; 245 interrupts-extended = <0>, 246 <&aic AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>, 247 <0>, 248 <0>; 249 #dma-cells = <1>; 250 iommus = <&dart_sio 2>; 251 power-domains = <&ps_sio_adma>; 252 resets = <&ps_audio_p>; 253 }; 254 255 mca: i2s@238400000 { 256 compatible = "apple,t8103-mca", "apple,mca"; 257 reg = <0x2 0x38400000 0x0 0x18000>, 258 <0x2 0x38300000 0x0 0x30000>; 259 260 interrupt-parent = <&aic>; 261 interrupts = <AIC_IRQ 619 IRQ_TYPE_LEVEL_HIGH>, 262 <AIC_IRQ 620 IRQ_TYPE_LEVEL_HIGH>, 263 <AIC_IRQ 621 IRQ_TYPE_LEVEL_HIGH>, 264 <AIC_IRQ 622 IRQ_TYPE_LEVEL_HIGH>, 265 <AIC_IRQ 623 IRQ_TYPE_LEVEL_HIGH>, 266 <AIC_IRQ 624 IRQ_TYPE_LEVEL_HIGH>; 267 268 resets = <&ps_audio_p>; 269 clocks = <&nco 0>, <&nco 1>, <&nco 2>, 270 <&nco 3>, <&nco 4>, <&nco 4>; 271 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, 272 <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; 273 dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, 274 <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, 275 <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, 276 <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>, 277 <&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>, 278 <&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>; 279 dma-names = "tx0a", "rx0a", "tx0b", "rx0b", 280 "tx1a", "rx1a", "tx1b", "rx1b", 281 "tx2a", "rx2a", "tx2b", "rx2b", 282 "tx3a", "rx3a", "tx3b", "rx3b", 283 "tx4a", "rx4a", "tx4b", "rx4b", 284 "tx5a", "rx5a", "tx5b", "rx5b"; 285 286 #sound-dai-cells = <1>; 287 }; 288 289 nco: clock-controller@23b044000 { 290 compatible = "apple,t8103-nco", "apple,nco"; 291 reg = <0x2 0x3b044000 0x0 0x14000>; 292 clocks = <&nco_clkref>; 293 #clock-cells = <1>; 294 }; 295 296 aic: interrupt-controller@23b100000 { 297 compatible = "apple,t8103-aic", "apple,aic"; 298 #interrupt-cells = <3>; 299 interrupt-controller; 300 reg = <0x2 0x3b100000 0x0 0x8000>; 301 power-domains = <&ps_aic>; 302 303 affinities { 304 e-core-pmu-affinity { 305 apple,fiq-index = <AIC_CPU_PMU_E>; 306 cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; 307 }; 308 309 p-core-pmu-affinity { 310 apple,fiq-index = <AIC_CPU_PMU_P>; 311 cpus = <&cpu4 &cpu5 &cpu6 &cpu7>; 312 }; 313 }; 314 }; 315 316 pmgr: power-management@23b700000 { 317 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 318 #address-cells = <1>; 319 #size-cells = <1>; 320 reg = <0x2 0x3b700000 0 0x14000>; 321 }; 322 323 pinctrl_ap: pinctrl@23c100000 { 324 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 325 reg = <0x2 0x3c100000 0x0 0x100000>; 326 power-domains = <&ps_gpio>; 327 328 gpio-controller; 329 #gpio-cells = <2>; 330 gpio-ranges = <&pinctrl_ap 0 0 212>; 331 apple,npins = <212>; 332 333 interrupt-controller; 334 #interrupt-cells = <2>; 335 interrupt-parent = <&aic>; 336 interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>, 337 <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>, 338 <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>, 339 <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>, 340 <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>, 341 <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, 342 <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>; 343 344 i2c0_pins: i2c0-pins { 345 pinmux = <APPLE_PINMUX(192, 1)>, 346 <APPLE_PINMUX(188, 1)>; 347 }; 348 349 i2c1_pins: i2c1-pins { 350 pinmux = <APPLE_PINMUX(201, 1)>, 351 <APPLE_PINMUX(199, 1)>; 352 }; 353 354 i2c2_pins: i2c2-pins { 355 pinmux = <APPLE_PINMUX(163, 1)>, 356 <APPLE_PINMUX(162, 1)>; 357 }; 358 359 i2c3_pins: i2c3-pins { 360 pinmux = <APPLE_PINMUX(73, 1)>, 361 <APPLE_PINMUX(72, 1)>; 362 }; 363 364 i2c4_pins: i2c4-pins { 365 pinmux = <APPLE_PINMUX(135, 1)>, 366 <APPLE_PINMUX(134, 1)>; 367 }; 368 369 pcie_pins: pcie-pins { 370 pinmux = <APPLE_PINMUX(150, 1)>, 371 <APPLE_PINMUX(151, 1)>, 372 <APPLE_PINMUX(32, 1)>; 373 }; 374 }; 375 376 pinctrl_nub: pinctrl@23d1f0000 { 377 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 378 reg = <0x2 0x3d1f0000 0x0 0x4000>; 379 power-domains = <&ps_nub_gpio>; 380 381 gpio-controller; 382 #gpio-cells = <2>; 383 gpio-ranges = <&pinctrl_nub 0 0 23>; 384 apple,npins = <23>; 385 386 interrupt-controller; 387 #interrupt-cells = <2>; 388 interrupt-parent = <&aic>; 389 interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>, 390 <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>, 391 <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>, 392 <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>, 393 <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>, 394 <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>, 395 <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>; 396 }; 397 398 pmgr_mini: power-management@23d280000 { 399 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 400 #address-cells = <1>; 401 #size-cells = <1>; 402 reg = <0x2 0x3d280000 0 0x4000>; 403 }; 404 405 wdt: watchdog@23d2b0000 { 406 compatible = "apple,t8103-wdt", "apple,wdt"; 407 reg = <0x2 0x3d2b0000 0x0 0x4000>; 408 clocks = <&clkref>; 409 interrupt-parent = <&aic>; 410 interrupts = <AIC_IRQ 338 IRQ_TYPE_LEVEL_HIGH>; 411 }; 412 413 pinctrl_smc: pinctrl@23e820000 { 414 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 415 reg = <0x2 0x3e820000 0x0 0x4000>; 416 417 gpio-controller; 418 #gpio-cells = <2>; 419 gpio-ranges = <&pinctrl_smc 0 0 16>; 420 apple,npins = <16>; 421 422 interrupt-controller; 423 #interrupt-cells = <2>; 424 interrupt-parent = <&aic>; 425 interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>, 426 <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>, 427 <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>, 428 <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>, 429 <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>, 430 <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>, 431 <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>; 432 }; 433 434 pinctrl_aop: pinctrl@24a820000 { 435 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 436 reg = <0x2 0x4a820000 0x0 0x4000>; 437 438 gpio-controller; 439 #gpio-cells = <2>; 440 gpio-ranges = <&pinctrl_aop 0 0 42>; 441 apple,npins = <42>; 442 443 interrupt-controller; 444 #interrupt-cells = <2>; 445 interrupt-parent = <&aic>; 446 interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>, 447 <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>, 448 <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>, 449 <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>, 450 <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>, 451 <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, 452 <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>; 453 }; 454 455 ans_mbox: mbox@277408000 { 456 compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4"; 457 reg = <0x2 0x77408000 0x0 0x4000>; 458 interrupt-parent = <&aic>; 459 interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>, 460 <AIC_IRQ 584 IRQ_TYPE_LEVEL_HIGH>, 461 <AIC_IRQ 585 IRQ_TYPE_LEVEL_HIGH>, 462 <AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>; 463 interrupt-names = "send-empty", "send-not-empty", 464 "recv-empty", "recv-not-empty"; 465 #mbox-cells = <0>; 466 power-domains = <&ps_ans2>; 467 }; 468 469 sart: iommu@27bc50000 { 470 compatible = "apple,t8103-sart"; 471 reg = <0x2 0x7bc50000 0x0 0x10000>; 472 power-domains = <&ps_ans2>; 473 }; 474 475 nvme@27bcc0000 { 476 compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2"; 477 reg = <0x2 0x7bcc0000 0x0 0x40000>, 478 <0x2 0x77400000 0x0 0x4000>; 479 reg-names = "nvme", "ans"; 480 interrupt-parent = <&aic>; 481 interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>; 482 mboxes = <&ans_mbox>; 483 apple,sart = <&sart>; 484 power-domains = <&ps_ans2>, <&ps_apcie_st>; 485 power-domain-names = "ans", "apcie0"; 486 resets = <&ps_ans2>; 487 }; 488 489 pcie0_dart_0: dart@681008000 { 490 compatible = "apple,t8103-dart"; 491 reg = <0x6 0x81008000 0x0 0x4000>; 492 #iommu-cells = <1>; 493 interrupt-parent = <&aic>; 494 interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>; 495 power-domains = <&ps_apcie_gp>; 496 }; 497 498 pcie0_dart_1: dart@682008000 { 499 compatible = "apple,t8103-dart"; 500 reg = <0x6 0x82008000 0x0 0x4000>; 501 #iommu-cells = <1>; 502 interrupt-parent = <&aic>; 503 interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>; 504 power-domains = <&ps_apcie_gp>; 505 }; 506 507 pcie0_dart_2: dart@683008000 { 508 compatible = "apple,t8103-dart"; 509 reg = <0x6 0x83008000 0x0 0x4000>; 510 #iommu-cells = <1>; 511 interrupt-parent = <&aic>; 512 interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>; 513 power-domains = <&ps_apcie_gp>; 514 }; 515 516 pcie0: pcie@690000000 { 517 compatible = "apple,t8103-pcie", "apple,pcie"; 518 device_type = "pci"; 519 520 reg = <0x6 0x90000000 0x0 0x1000000>, 521 <0x6 0x80000000 0x0 0x100000>, 522 <0x6 0x81000000 0x0 0x4000>, 523 <0x6 0x82000000 0x0 0x4000>, 524 <0x6 0x83000000 0x0 0x4000>; 525 reg-names = "config", "rc", "port0", "port1", "port2"; 526 527 interrupt-parent = <&aic>; 528 interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, 529 <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, 530 <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; 531 532 msi-controller; 533 msi-parent = <&pcie0>; 534 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; 535 536 537 iommu-map = <0x100 &pcie0_dart_0 1 1>, 538 <0x200 &pcie0_dart_1 1 1>, 539 <0x300 &pcie0_dart_2 1 1>; 540 iommu-map-mask = <0xff00>; 541 542 bus-range = <0 3>; 543 #address-cells = <3>; 544 #size-cells = <2>; 545 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, 546 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; 547 548 power-domains = <&ps_apcie_gp>; 549 pinctrl-0 = <&pcie_pins>; 550 pinctrl-names = "default"; 551 552 port00: pci@0,0 { 553 device_type = "pci"; 554 reg = <0x0 0x0 0x0 0x0 0x0>; 555 reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>; 556 557 #address-cells = <3>; 558 #size-cells = <2>; 559 ranges; 560 561 interrupt-controller; 562 #interrupt-cells = <1>; 563 564 interrupt-map-mask = <0 0 0 7>; 565 interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 566 <0 0 0 2 &port00 0 0 0 1>, 567 <0 0 0 3 &port00 0 0 0 2>, 568 <0 0 0 4 &port00 0 0 0 3>; 569 }; 570 571 port01: pci@1,0 { 572 device_type = "pci"; 573 reg = <0x800 0x0 0x0 0x0 0x0>; 574 reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>; 575 576 #address-cells = <3>; 577 #size-cells = <2>; 578 ranges; 579 580 interrupt-controller; 581 #interrupt-cells = <1>; 582 583 interrupt-map-mask = <0 0 0 7>; 584 interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 585 <0 0 0 2 &port01 0 0 0 1>, 586 <0 0 0 3 &port01 0 0 0 2>, 587 <0 0 0 4 &port01 0 0 0 3>; 588 }; 589 590 port02: pci@2,0 { 591 device_type = "pci"; 592 reg = <0x1000 0x0 0x0 0x0 0x0>; 593 reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>; 594 595 #address-cells = <3>; 596 #size-cells = <2>; 597 ranges; 598 599 interrupt-controller; 600 #interrupt-cells = <1>; 601 602 interrupt-map-mask = <0 0 0 7>; 603 interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 604 <0 0 0 2 &port02 0 0 0 1>, 605 <0 0 0 3 &port02 0 0 0 2>, 606 <0 0 0 4 &port02 0 0 0 3>; 607 }; 608 }; 609 }; 610}; 611 612#include "t8103-pmgr.dtsi" 613