1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8103 "M1" SoC 4 * 5 * Other names: H13G, "Tonga" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 compatible = "apple,t8103", "apple,arm-platform"; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <2>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 compatible = "apple,icestorm"; 27 device_type = "cpu"; 28 reg = <0x0 0x0>; 29 enable-method = "spin-table"; 30 cpu-release-addr = <0 0>; /* To be filled by loader */ 31 }; 32 33 cpu1: cpu@1 { 34 compatible = "apple,icestorm"; 35 device_type = "cpu"; 36 reg = <0x0 0x1>; 37 enable-method = "spin-table"; 38 cpu-release-addr = <0 0>; /* To be filled by loader */ 39 }; 40 41 cpu2: cpu@2 { 42 compatible = "apple,icestorm"; 43 device_type = "cpu"; 44 reg = <0x0 0x2>; 45 enable-method = "spin-table"; 46 cpu-release-addr = <0 0>; /* To be filled by loader */ 47 }; 48 49 cpu3: cpu@3 { 50 compatible = "apple,icestorm"; 51 device_type = "cpu"; 52 reg = <0x0 0x3>; 53 enable-method = "spin-table"; 54 cpu-release-addr = <0 0>; /* To be filled by loader */ 55 }; 56 57 cpu4: cpu@10100 { 58 compatible = "apple,firestorm"; 59 device_type = "cpu"; 60 reg = <0x0 0x10100>; 61 enable-method = "spin-table"; 62 cpu-release-addr = <0 0>; /* To be filled by loader */ 63 }; 64 65 cpu5: cpu@10101 { 66 compatible = "apple,firestorm"; 67 device_type = "cpu"; 68 reg = <0x0 0x10101>; 69 enable-method = "spin-table"; 70 cpu-release-addr = <0 0>; /* To be filled by loader */ 71 }; 72 73 cpu6: cpu@10102 { 74 compatible = "apple,firestorm"; 75 device_type = "cpu"; 76 reg = <0x0 0x10102>; 77 enable-method = "spin-table"; 78 cpu-release-addr = <0 0>; /* To be filled by loader */ 79 }; 80 81 cpu7: cpu@10103 { 82 compatible = "apple,firestorm"; 83 device_type = "cpu"; 84 reg = <0x0 0x10103>; 85 enable-method = "spin-table"; 86 cpu-release-addr = <0 0>; /* To be filled by loader */ 87 }; 88 }; 89 90 timer { 91 compatible = "arm,armv8-timer"; 92 interrupt-parent = <&aic>; 93 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 94 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 95 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 96 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 97 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 98 }; 99 100 clkref: clock-ref { 101 compatible = "fixed-clock"; 102 #clock-cells = <0>; 103 clock-frequency = <24000000>; 104 clock-output-names = "clkref"; 105 }; 106 107 soc { 108 compatible = "simple-bus"; 109 #address-cells = <2>; 110 #size-cells = <2>; 111 112 ranges; 113 nonposted-mmio; 114 115 i2c0: i2c@235010000 { 116 compatible = "apple,t8103-i2c", "apple,i2c"; 117 reg = <0x2 0x35010000 0x0 0x4000>; 118 clocks = <&clkref>; 119 interrupt-parent = <&aic>; 120 interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>; 121 pinctrl-0 = <&i2c0_pins>; 122 pinctrl-names = "default"; 123 #address-cells = <0x1>; 124 #size-cells = <0x0>; 125 power-domains = <&ps_i2c0>; 126 }; 127 128 i2c1: i2c@235014000 { 129 compatible = "apple,t8103-i2c", "apple,i2c"; 130 reg = <0x2 0x35014000 0x0 0x4000>; 131 clocks = <&clkref>; 132 interrupt-parent = <&aic>; 133 interrupts = <AIC_IRQ 628 IRQ_TYPE_LEVEL_HIGH>; 134 pinctrl-0 = <&i2c1_pins>; 135 pinctrl-names = "default"; 136 #address-cells = <0x1>; 137 #size-cells = <0x0>; 138 power-domains = <&ps_i2c1>; 139 }; 140 141 i2c2: i2c@235018000 { 142 compatible = "apple,t8103-i2c", "apple,i2c"; 143 reg = <0x2 0x35018000 0x0 0x4000>; 144 clocks = <&clkref>; 145 interrupt-parent = <&aic>; 146 interrupts = <AIC_IRQ 629 IRQ_TYPE_LEVEL_HIGH>; 147 pinctrl-0 = <&i2c2_pins>; 148 pinctrl-names = "default"; 149 #address-cells = <0x1>; 150 #size-cells = <0x0>; 151 status = "disabled"; /* not used in all devices */ 152 power-domains = <&ps_i2c2>; 153 }; 154 155 i2c3: i2c@23501c000 { 156 compatible = "apple,t8103-i2c", "apple,i2c"; 157 reg = <0x2 0x3501c000 0x0 0x4000>; 158 clocks = <&clkref>; 159 interrupt-parent = <&aic>; 160 interrupts = <AIC_IRQ 630 IRQ_TYPE_LEVEL_HIGH>; 161 pinctrl-0 = <&i2c3_pins>; 162 pinctrl-names = "default"; 163 #address-cells = <0x1>; 164 #size-cells = <0x0>; 165 power-domains = <&ps_i2c3>; 166 }; 167 168 i2c4: i2c@235020000 { 169 compatible = "apple,t8103-i2c", "apple,i2c"; 170 reg = <0x2 0x35020000 0x0 0x4000>; 171 clocks = <&clkref>; 172 interrupt-parent = <&aic>; 173 interrupts = <AIC_IRQ 631 IRQ_TYPE_LEVEL_HIGH>; 174 pinctrl-0 = <&i2c4_pins>; 175 pinctrl-names = "default"; 176 #address-cells = <0x1>; 177 #size-cells = <0x0>; 178 power-domains = <&ps_i2c4>; 179 status = "disabled"; /* only used in J293 */ 180 }; 181 182 serial0: serial@235200000 { 183 compatible = "apple,s5l-uart"; 184 reg = <0x2 0x35200000 0x0 0x1000>; 185 reg-io-width = <4>; 186 interrupt-parent = <&aic>; 187 interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>; 188 /* 189 * TODO: figure out the clocking properly, there may 190 * be a third selectable clock. 191 */ 192 clocks = <&clkref>, <&clkref>; 193 clock-names = "uart", "clk_uart_baud0"; 194 power-domains = <&ps_uart0>; 195 status = "disabled"; 196 }; 197 198 serial2: serial@235208000 { 199 compatible = "apple,s5l-uart"; 200 reg = <0x2 0x35208000 0x0 0x1000>; 201 reg-io-width = <4>; 202 interrupt-parent = <&aic>; 203 interrupts = <AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&clkref>, <&clkref>; 205 clock-names = "uart", "clk_uart_baud0"; 206 power-domains = <&ps_uart2>; 207 status = "disabled"; 208 }; 209 210 aic: interrupt-controller@23b100000 { 211 compatible = "apple,t8103-aic", "apple,aic"; 212 #interrupt-cells = <3>; 213 interrupt-controller; 214 reg = <0x2 0x3b100000 0x0 0x8000>; 215 power-domains = <&ps_aic>; 216 217 affinities { 218 e-core-pmu-affinity { 219 apple,fiq-index = <AIC_CPU_PMU_E>; 220 cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; 221 }; 222 223 p-core-pmu-affinity { 224 apple,fiq-index = <AIC_CPU_PMU_P>; 225 cpus = <&cpu4 &cpu5 &cpu6 &cpu7>; 226 }; 227 }; 228 }; 229 230 pmgr: power-management@23b700000 { 231 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 232 #address-cells = <1>; 233 #size-cells = <1>; 234 reg = <0x2 0x3b700000 0 0x14000>; 235 }; 236 237 pinctrl_ap: pinctrl@23c100000 { 238 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 239 reg = <0x2 0x3c100000 0x0 0x100000>; 240 power-domains = <&ps_gpio>; 241 242 gpio-controller; 243 #gpio-cells = <2>; 244 gpio-ranges = <&pinctrl_ap 0 0 212>; 245 apple,npins = <212>; 246 247 interrupt-controller; 248 #interrupt-cells = <2>; 249 interrupt-parent = <&aic>; 250 interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>, 251 <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>, 252 <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>, 253 <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>, 254 <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>, 255 <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, 256 <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>; 257 258 i2c0_pins: i2c0-pins { 259 pinmux = <APPLE_PINMUX(192, 1)>, 260 <APPLE_PINMUX(188, 1)>; 261 }; 262 263 i2c1_pins: i2c1-pins { 264 pinmux = <APPLE_PINMUX(201, 1)>, 265 <APPLE_PINMUX(199, 1)>; 266 }; 267 268 i2c2_pins: i2c2-pins { 269 pinmux = <APPLE_PINMUX(163, 1)>, 270 <APPLE_PINMUX(162, 1)>; 271 }; 272 273 i2c3_pins: i2c3-pins { 274 pinmux = <APPLE_PINMUX(73, 1)>, 275 <APPLE_PINMUX(72, 1)>; 276 }; 277 278 i2c4_pins: i2c4-pins { 279 pinmux = <APPLE_PINMUX(135, 1)>, 280 <APPLE_PINMUX(134, 1)>; 281 }; 282 283 pcie_pins: pcie-pins { 284 pinmux = <APPLE_PINMUX(150, 1)>, 285 <APPLE_PINMUX(151, 1)>, 286 <APPLE_PINMUX(32, 1)>; 287 }; 288 }; 289 290 pinctrl_nub: pinctrl@23d1f0000 { 291 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 292 reg = <0x2 0x3d1f0000 0x0 0x4000>; 293 power-domains = <&ps_nub_gpio>; 294 295 gpio-controller; 296 #gpio-cells = <2>; 297 gpio-ranges = <&pinctrl_nub 0 0 23>; 298 apple,npins = <23>; 299 300 interrupt-controller; 301 #interrupt-cells = <2>; 302 interrupt-parent = <&aic>; 303 interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>, 304 <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>, 305 <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>, 306 <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>, 307 <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>, 308 <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>, 309 <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>; 310 }; 311 312 pmgr_mini: power-management@23d280000 { 313 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 314 #address-cells = <1>; 315 #size-cells = <1>; 316 reg = <0x2 0x3d280000 0 0x4000>; 317 }; 318 319 wdt: watchdog@23d2b0000 { 320 compatible = "apple,t8103-wdt", "apple,wdt"; 321 reg = <0x2 0x3d2b0000 0x0 0x4000>; 322 clocks = <&clkref>; 323 interrupt-parent = <&aic>; 324 interrupts = <AIC_IRQ 338 IRQ_TYPE_LEVEL_HIGH>; 325 }; 326 327 pinctrl_smc: pinctrl@23e820000 { 328 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 329 reg = <0x2 0x3e820000 0x0 0x4000>; 330 331 gpio-controller; 332 #gpio-cells = <2>; 333 gpio-ranges = <&pinctrl_smc 0 0 16>; 334 apple,npins = <16>; 335 336 interrupt-controller; 337 #interrupt-cells = <2>; 338 interrupt-parent = <&aic>; 339 interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>, 340 <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>, 341 <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>, 342 <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>, 343 <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>, 344 <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>, 345 <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>; 346 }; 347 348 pinctrl_aop: pinctrl@24a820000 { 349 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 350 reg = <0x2 0x4a820000 0x0 0x4000>; 351 352 gpio-controller; 353 #gpio-cells = <2>; 354 gpio-ranges = <&pinctrl_aop 0 0 42>; 355 apple,npins = <42>; 356 357 interrupt-controller; 358 #interrupt-cells = <2>; 359 interrupt-parent = <&aic>; 360 interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>, 361 <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>, 362 <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>, 363 <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>, 364 <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>, 365 <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, 366 <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>; 367 }; 368 369 pcie0_dart_0: dart@681008000 { 370 compatible = "apple,t8103-dart"; 371 reg = <0x6 0x81008000 0x0 0x4000>; 372 #iommu-cells = <1>; 373 interrupt-parent = <&aic>; 374 interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>; 375 power-domains = <&ps_apcie_gp>; 376 }; 377 378 pcie0_dart_1: dart@682008000 { 379 compatible = "apple,t8103-dart"; 380 reg = <0x6 0x82008000 0x0 0x4000>; 381 #iommu-cells = <1>; 382 interrupt-parent = <&aic>; 383 interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>; 384 power-domains = <&ps_apcie_gp>; 385 }; 386 387 pcie0_dart_2: dart@683008000 { 388 compatible = "apple,t8103-dart"; 389 reg = <0x6 0x83008000 0x0 0x4000>; 390 #iommu-cells = <1>; 391 interrupt-parent = <&aic>; 392 interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>; 393 power-domains = <&ps_apcie_gp>; 394 }; 395 396 pcie0: pcie@690000000 { 397 compatible = "apple,t8103-pcie", "apple,pcie"; 398 device_type = "pci"; 399 400 reg = <0x6 0x90000000 0x0 0x1000000>, 401 <0x6 0x80000000 0x0 0x100000>, 402 <0x6 0x81000000 0x0 0x4000>, 403 <0x6 0x82000000 0x0 0x4000>, 404 <0x6 0x83000000 0x0 0x4000>; 405 reg-names = "config", "rc", "port0", "port1", "port2"; 406 407 interrupt-parent = <&aic>; 408 interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, 409 <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, 410 <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; 411 412 msi-controller; 413 msi-parent = <&pcie0>; 414 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; 415 416 417 iommu-map = <0x100 &pcie0_dart_0 1 1>, 418 <0x200 &pcie0_dart_1 1 1>, 419 <0x300 &pcie0_dart_2 1 1>; 420 iommu-map-mask = <0xff00>; 421 422 bus-range = <0 3>; 423 #address-cells = <3>; 424 #size-cells = <2>; 425 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, 426 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; 427 428 power-domains = <&ps_apcie_gp>; 429 pinctrl-0 = <&pcie_pins>; 430 pinctrl-names = "default"; 431 432 port00: pci@0,0 { 433 device_type = "pci"; 434 reg = <0x0 0x0 0x0 0x0 0x0>; 435 reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>; 436 437 #address-cells = <3>; 438 #size-cells = <2>; 439 ranges; 440 441 interrupt-controller; 442 #interrupt-cells = <1>; 443 444 interrupt-map-mask = <0 0 0 7>; 445 interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 446 <0 0 0 2 &port00 0 0 0 1>, 447 <0 0 0 3 &port00 0 0 0 2>, 448 <0 0 0 4 &port00 0 0 0 3>; 449 }; 450 451 port01: pci@1,0 { 452 device_type = "pci"; 453 reg = <0x800 0x0 0x0 0x0 0x0>; 454 reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>; 455 456 #address-cells = <3>; 457 #size-cells = <2>; 458 ranges; 459 460 interrupt-controller; 461 #interrupt-cells = <1>; 462 463 interrupt-map-mask = <0 0 0 7>; 464 interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 465 <0 0 0 2 &port01 0 0 0 1>, 466 <0 0 0 3 &port01 0 0 0 2>, 467 <0 0 0 4 &port01 0 0 0 3>; 468 }; 469 470 port02: pci@2,0 { 471 device_type = "pci"; 472 reg = <0x1000 0x0 0x0 0x0 0x0>; 473 reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>; 474 475 #address-cells = <3>; 476 #size-cells = <2>; 477 ranges; 478 479 interrupt-controller; 480 #interrupt-cells = <1>; 481 482 interrupt-map-mask = <0 0 0 7>; 483 interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 484 <0 0 0 2 &port02 0 0 0 1>, 485 <0 0 0 3 &port02 0 0 0 2>, 486 <0 0 0 4 &port02 0 0 0 3>; 487 }; 488 }; 489 }; 490}; 491 492#include "t8103-pmgr.dtsi" 493