1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8103 "M1" SoC 4 * 5 * Other names: H13G, "Tonga" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/interrupt-controller/apple-aic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/pinctrl/apple.h> 13 14/ { 15 compatible = "apple,t8103", "apple,arm-platform"; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <2>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "apple,icestorm"; 26 device_type = "cpu"; 27 reg = <0x0 0x0>; 28 enable-method = "spin-table"; 29 cpu-release-addr = <0 0>; /* To be filled by loader */ 30 }; 31 32 cpu1: cpu@1 { 33 compatible = "apple,icestorm"; 34 device_type = "cpu"; 35 reg = <0x0 0x1>; 36 enable-method = "spin-table"; 37 cpu-release-addr = <0 0>; /* To be filled by loader */ 38 }; 39 40 cpu2: cpu@2 { 41 compatible = "apple,icestorm"; 42 device_type = "cpu"; 43 reg = <0x0 0x2>; 44 enable-method = "spin-table"; 45 cpu-release-addr = <0 0>; /* To be filled by loader */ 46 }; 47 48 cpu3: cpu@3 { 49 compatible = "apple,icestorm"; 50 device_type = "cpu"; 51 reg = <0x0 0x3>; 52 enable-method = "spin-table"; 53 cpu-release-addr = <0 0>; /* To be filled by loader */ 54 }; 55 56 cpu4: cpu@10100 { 57 compatible = "apple,firestorm"; 58 device_type = "cpu"; 59 reg = <0x0 0x10100>; 60 enable-method = "spin-table"; 61 cpu-release-addr = <0 0>; /* To be filled by loader */ 62 }; 63 64 cpu5: cpu@10101 { 65 compatible = "apple,firestorm"; 66 device_type = "cpu"; 67 reg = <0x0 0x10101>; 68 enable-method = "spin-table"; 69 cpu-release-addr = <0 0>; /* To be filled by loader */ 70 }; 71 72 cpu6: cpu@10102 { 73 compatible = "apple,firestorm"; 74 device_type = "cpu"; 75 reg = <0x0 0x10102>; 76 enable-method = "spin-table"; 77 cpu-release-addr = <0 0>; /* To be filled by loader */ 78 }; 79 80 cpu7: cpu@10103 { 81 compatible = "apple,firestorm"; 82 device_type = "cpu"; 83 reg = <0x0 0x10103>; 84 enable-method = "spin-table"; 85 cpu-release-addr = <0 0>; /* To be filled by loader */ 86 }; 87 }; 88 89 timer { 90 compatible = "arm,armv8-timer"; 91 interrupt-parent = <&aic>; 92 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 93 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 94 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 95 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 96 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 97 }; 98 99 clk24: clock-24m { 100 compatible = "fixed-clock"; 101 #clock-cells = <0>; 102 clock-frequency = <24000000>; 103 clock-output-names = "clk24"; 104 }; 105 106 soc { 107 compatible = "simple-bus"; 108 #address-cells = <2>; 109 #size-cells = <2>; 110 111 ranges; 112 nonposted-mmio; 113 114 i2c0: i2c@235010000 { 115 compatible = "apple,t8103-i2c", "apple,i2c"; 116 reg = <0x2 0x35010000 0x0 0x4000>; 117 clocks = <&clk24>; 118 interrupt-parent = <&aic>; 119 interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>; 120 pinctrl-0 = <&i2c0_pins>; 121 pinctrl-names = "default"; 122 #address-cells = <0x1>; 123 #size-cells = <0x0>; 124 power-domains = <&ps_i2c0>; 125 }; 126 127 i2c1: i2c@235014000 { 128 compatible = "apple,t8103-i2c", "apple,i2c"; 129 reg = <0x2 0x35014000 0x0 0x4000>; 130 clocks = <&clk24>; 131 interrupt-parent = <&aic>; 132 interrupts = <AIC_IRQ 628 IRQ_TYPE_LEVEL_HIGH>; 133 pinctrl-0 = <&i2c1_pins>; 134 pinctrl-names = "default"; 135 #address-cells = <0x1>; 136 #size-cells = <0x0>; 137 power-domains = <&ps_i2c1>; 138 }; 139 140 i2c2: i2c@235018000 { 141 compatible = "apple,t8103-i2c", "apple,i2c"; 142 reg = <0x2 0x35018000 0x0 0x4000>; 143 clocks = <&clk24>; 144 interrupt-parent = <&aic>; 145 interrupts = <AIC_IRQ 629 IRQ_TYPE_LEVEL_HIGH>; 146 pinctrl-0 = <&i2c2_pins>; 147 pinctrl-names = "default"; 148 #address-cells = <0x1>; 149 #size-cells = <0x0>; 150 status = "disabled"; /* not used in all devices */ 151 power-domains = <&ps_i2c2>; 152 }; 153 154 i2c3: i2c@23501c000 { 155 compatible = "apple,t8103-i2c", "apple,i2c"; 156 reg = <0x2 0x3501c000 0x0 0x4000>; 157 clocks = <&clk24>; 158 interrupt-parent = <&aic>; 159 interrupts = <AIC_IRQ 630 IRQ_TYPE_LEVEL_HIGH>; 160 pinctrl-0 = <&i2c3_pins>; 161 pinctrl-names = "default"; 162 #address-cells = <0x1>; 163 #size-cells = <0x0>; 164 power-domains = <&ps_i2c3>; 165 }; 166 167 i2c4: i2c@235020000 { 168 compatible = "apple,t8103-i2c", "apple,i2c"; 169 reg = <0x2 0x35020000 0x0 0x4000>; 170 clocks = <&clk24>; 171 interrupt-parent = <&aic>; 172 interrupts = <AIC_IRQ 631 IRQ_TYPE_LEVEL_HIGH>; 173 pinctrl-0 = <&i2c4_pins>; 174 pinctrl-names = "default"; 175 #address-cells = <0x1>; 176 #size-cells = <0x0>; 177 power-domains = <&ps_i2c4>; 178 status = "disabled"; /* only used in J293 */ 179 }; 180 181 serial0: serial@235200000 { 182 compatible = "apple,s5l-uart"; 183 reg = <0x2 0x35200000 0x0 0x1000>; 184 reg-io-width = <4>; 185 interrupt-parent = <&aic>; 186 interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>; 187 /* 188 * TODO: figure out the clocking properly, there may 189 * be a third selectable clock. 190 */ 191 clocks = <&clk24>, <&clk24>; 192 clock-names = "uart", "clk_uart_baud0"; 193 power-domains = <&ps_uart0>; 194 status = "disabled"; 195 }; 196 197 serial2: serial@235208000 { 198 compatible = "apple,s5l-uart"; 199 reg = <0x2 0x35208000 0x0 0x1000>; 200 reg-io-width = <4>; 201 interrupt-parent = <&aic>; 202 interrupts = <AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&clk24>, <&clk24>; 204 clock-names = "uart", "clk_uart_baud0"; 205 power-domains = <&ps_uart2>; 206 status = "disabled"; 207 }; 208 209 aic: interrupt-controller@23b100000 { 210 compatible = "apple,t8103-aic", "apple,aic"; 211 #interrupt-cells = <3>; 212 interrupt-controller; 213 reg = <0x2 0x3b100000 0x0 0x8000>; 214 power-domains = <&ps_aic>; 215 }; 216 217 pmgr: power-management@23b700000 { 218 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 219 #address-cells = <1>; 220 #size-cells = <1>; 221 reg = <0x2 0x3b700000 0 0x14000>; 222 }; 223 224 pinctrl_ap: pinctrl@23c100000 { 225 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 226 reg = <0x2 0x3c100000 0x0 0x100000>; 227 power-domains = <&ps_gpio>; 228 229 gpio-controller; 230 #gpio-cells = <2>; 231 gpio-ranges = <&pinctrl_ap 0 0 212>; 232 apple,npins = <212>; 233 234 interrupt-controller; 235 #interrupt-cells = <2>; 236 interrupt-parent = <&aic>; 237 interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>, 238 <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>, 239 <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>, 240 <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>, 241 <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>, 242 <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, 243 <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>; 244 245 i2c0_pins: i2c0-pins { 246 pinmux = <APPLE_PINMUX(192, 1)>, 247 <APPLE_PINMUX(188, 1)>; 248 }; 249 250 i2c1_pins: i2c1-pins { 251 pinmux = <APPLE_PINMUX(201, 1)>, 252 <APPLE_PINMUX(199, 1)>; 253 }; 254 255 i2c2_pins: i2c2-pins { 256 pinmux = <APPLE_PINMUX(163, 1)>, 257 <APPLE_PINMUX(162, 1)>; 258 }; 259 260 i2c3_pins: i2c3-pins { 261 pinmux = <APPLE_PINMUX(73, 1)>, 262 <APPLE_PINMUX(72, 1)>; 263 }; 264 265 i2c4_pins: i2c4-pins { 266 pinmux = <APPLE_PINMUX(135, 1)>, 267 <APPLE_PINMUX(134, 1)>; 268 }; 269 270 pcie_pins: pcie-pins { 271 pinmux = <APPLE_PINMUX(150, 1)>, 272 <APPLE_PINMUX(151, 1)>, 273 <APPLE_PINMUX(32, 1)>; 274 }; 275 }; 276 277 pmgr_mini: power-management@23d280000 { 278 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 279 #address-cells = <1>; 280 #size-cells = <1>; 281 reg = <0x2 0x3d280000 0 0x4000>; 282 }; 283 284 pinctrl_aop: pinctrl@24a820000 { 285 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 286 reg = <0x2 0x4a820000 0x0 0x4000>; 287 288 gpio-controller; 289 #gpio-cells = <2>; 290 gpio-ranges = <&pinctrl_aop 0 0 42>; 291 apple,npins = <42>; 292 293 interrupt-controller; 294 #interrupt-cells = <2>; 295 interrupt-parent = <&aic>; 296 interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>, 297 <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>, 298 <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>, 299 <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>, 300 <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>, 301 <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, 302 <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>; 303 }; 304 305 pinctrl_nub: pinctrl@23d1f0000 { 306 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 307 reg = <0x2 0x3d1f0000 0x0 0x4000>; 308 power-domains = <&ps_nub_gpio>; 309 310 gpio-controller; 311 #gpio-cells = <2>; 312 gpio-ranges = <&pinctrl_nub 0 0 23>; 313 apple,npins = <23>; 314 315 interrupt-controller; 316 #interrupt-cells = <2>; 317 interrupt-parent = <&aic>; 318 interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>, 319 <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>, 320 <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>, 321 <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>, 322 <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>, 323 <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>, 324 <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>; 325 }; 326 327 pinctrl_smc: pinctrl@23e820000 { 328 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 329 reg = <0x2 0x3e820000 0x0 0x4000>; 330 331 gpio-controller; 332 #gpio-cells = <2>; 333 gpio-ranges = <&pinctrl_smc 0 0 16>; 334 apple,npins = <16>; 335 336 interrupt-controller; 337 #interrupt-cells = <2>; 338 interrupt-parent = <&aic>; 339 interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>, 340 <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>, 341 <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>, 342 <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>, 343 <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>, 344 <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>, 345 <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>; 346 }; 347 348 pcie0_dart_0: dart@681008000 { 349 compatible = "apple,t8103-dart"; 350 reg = <0x6 0x81008000 0x0 0x4000>; 351 #iommu-cells = <1>; 352 interrupt-parent = <&aic>; 353 interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>; 354 power-domains = <&ps_apcie_gp>; 355 }; 356 357 pcie0_dart_1: dart@682008000 { 358 compatible = "apple,t8103-dart"; 359 reg = <0x6 0x82008000 0x0 0x4000>; 360 #iommu-cells = <1>; 361 interrupt-parent = <&aic>; 362 interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>; 363 power-domains = <&ps_apcie_gp>; 364 }; 365 366 pcie0_dart_2: dart@683008000 { 367 compatible = "apple,t8103-dart"; 368 reg = <0x6 0x83008000 0x0 0x4000>; 369 #iommu-cells = <1>; 370 interrupt-parent = <&aic>; 371 interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>; 372 power-domains = <&ps_apcie_gp>; 373 }; 374 375 pcie0: pcie@690000000 { 376 compatible = "apple,t8103-pcie", "apple,pcie"; 377 device_type = "pci"; 378 379 reg = <0x6 0x90000000 0x0 0x1000000>, 380 <0x6 0x80000000 0x0 0x100000>, 381 <0x6 0x81000000 0x0 0x4000>, 382 <0x6 0x82000000 0x0 0x4000>, 383 <0x6 0x83000000 0x0 0x4000>; 384 reg-names = "config", "rc", "port0", "port1", "port2"; 385 386 interrupt-parent = <&aic>; 387 interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, 388 <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, 389 <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; 390 391 msi-controller; 392 msi-parent = <&pcie0>; 393 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; 394 395 396 iommu-map = <0x100 &pcie0_dart_0 1 1>, 397 <0x200 &pcie0_dart_1 1 1>, 398 <0x300 &pcie0_dart_2 1 1>; 399 iommu-map-mask = <0xff00>; 400 401 bus-range = <0 3>; 402 #address-cells = <3>; 403 #size-cells = <2>; 404 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, 405 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; 406 407 power-domains = <&ps_apcie_gp>; 408 pinctrl-0 = <&pcie_pins>; 409 pinctrl-names = "default"; 410 411 port00: pci@0,0 { 412 device_type = "pci"; 413 reg = <0x0 0x0 0x0 0x0 0x0>; 414 reset-gpios = <&pinctrl_ap 152 0>; 415 416 #address-cells = <3>; 417 #size-cells = <2>; 418 ranges; 419 420 interrupt-controller; 421 #interrupt-cells = <1>; 422 423 interrupt-map-mask = <0 0 0 7>; 424 interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 425 <0 0 0 2 &port00 0 0 0 1>, 426 <0 0 0 3 &port00 0 0 0 2>, 427 <0 0 0 4 &port00 0 0 0 3>; 428 }; 429 430 port01: pci@1,0 { 431 device_type = "pci"; 432 reg = <0x800 0x0 0x0 0x0 0x0>; 433 reset-gpios = <&pinctrl_ap 153 0>; 434 435 #address-cells = <3>; 436 #size-cells = <2>; 437 ranges; 438 439 interrupt-controller; 440 #interrupt-cells = <1>; 441 442 interrupt-map-mask = <0 0 0 7>; 443 interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 444 <0 0 0 2 &port01 0 0 0 1>, 445 <0 0 0 3 &port01 0 0 0 2>, 446 <0 0 0 4 &port01 0 0 0 3>; 447 }; 448 449 port02: pci@2,0 { 450 device_type = "pci"; 451 reg = <0x1000 0x0 0x0 0x0 0x0>; 452 reset-gpios = <&pinctrl_ap 33 0>; 453 454 #address-cells = <3>; 455 #size-cells = <2>; 456 ranges; 457 458 interrupt-controller; 459 #interrupt-cells = <1>; 460 461 interrupt-map-mask = <0 0 0 7>; 462 interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 463 <0 0 0 2 &port02 0 0 0 1>, 464 <0 0 0 3 &port02 0 0 0 2>, 465 <0 0 0 4 &port02 0 0 0 3>; 466 }; 467 }; 468 }; 469}; 470 471#include "t8103-pmgr.dtsi" 472