1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8103 "M1" SoC 4 * 5 * Other names: H13G, "Tonga" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/interrupt-controller/apple-aic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/pinctrl/apple.h> 13 14/ { 15 compatible = "apple,t8103", "apple,arm-platform"; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <2>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "apple,icestorm"; 26 device_type = "cpu"; 27 reg = <0x0 0x0>; 28 enable-method = "spin-table"; 29 cpu-release-addr = <0 0>; /* To be filled by loader */ 30 }; 31 32 cpu1: cpu@1 { 33 compatible = "apple,icestorm"; 34 device_type = "cpu"; 35 reg = <0x0 0x1>; 36 enable-method = "spin-table"; 37 cpu-release-addr = <0 0>; /* To be filled by loader */ 38 }; 39 40 cpu2: cpu@2 { 41 compatible = "apple,icestorm"; 42 device_type = "cpu"; 43 reg = <0x0 0x2>; 44 enable-method = "spin-table"; 45 cpu-release-addr = <0 0>; /* To be filled by loader */ 46 }; 47 48 cpu3: cpu@3 { 49 compatible = "apple,icestorm"; 50 device_type = "cpu"; 51 reg = <0x0 0x3>; 52 enable-method = "spin-table"; 53 cpu-release-addr = <0 0>; /* To be filled by loader */ 54 }; 55 56 cpu4: cpu@10100 { 57 compatible = "apple,firestorm"; 58 device_type = "cpu"; 59 reg = <0x0 0x10100>; 60 enable-method = "spin-table"; 61 cpu-release-addr = <0 0>; /* To be filled by loader */ 62 }; 63 64 cpu5: cpu@10101 { 65 compatible = "apple,firestorm"; 66 device_type = "cpu"; 67 reg = <0x0 0x10101>; 68 enable-method = "spin-table"; 69 cpu-release-addr = <0 0>; /* To be filled by loader */ 70 }; 71 72 cpu6: cpu@10102 { 73 compatible = "apple,firestorm"; 74 device_type = "cpu"; 75 reg = <0x0 0x10102>; 76 enable-method = "spin-table"; 77 cpu-release-addr = <0 0>; /* To be filled by loader */ 78 }; 79 80 cpu7: cpu@10103 { 81 compatible = "apple,firestorm"; 82 device_type = "cpu"; 83 reg = <0x0 0x10103>; 84 enable-method = "spin-table"; 85 cpu-release-addr = <0 0>; /* To be filled by loader */ 86 }; 87 }; 88 89 timer { 90 compatible = "arm,armv8-timer"; 91 interrupt-parent = <&aic>; 92 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 93 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 94 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 95 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 96 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 97 }; 98 99 clk24: clock-24m { 100 compatible = "fixed-clock"; 101 #clock-cells = <0>; 102 clock-frequency = <24000000>; 103 clock-output-names = "clk24"; 104 }; 105 106 soc { 107 compatible = "simple-bus"; 108 #address-cells = <2>; 109 #size-cells = <2>; 110 111 ranges; 112 nonposted-mmio; 113 114 i2c0: i2c@235010000 { 115 compatible = "apple,t8103-i2c", "apple,i2c"; 116 reg = <0x2 0x35010000 0x0 0x4000>; 117 clocks = <&clk24>; 118 interrupt-parent = <&aic>; 119 interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>; 120 pinctrl-0 = <&i2c0_pins>; 121 pinctrl-names = "default"; 122 #address-cells = <0x1>; 123 #size-cells = <0x0>; 124 power-domains = <&ps_i2c0>; 125 }; 126 127 i2c1: i2c@235014000 { 128 compatible = "apple,t8103-i2c", "apple,i2c"; 129 reg = <0x2 0x35014000 0x0 0x4000>; 130 clocks = <&clk24>; 131 interrupt-parent = <&aic>; 132 interrupts = <AIC_IRQ 628 IRQ_TYPE_LEVEL_HIGH>; 133 pinctrl-0 = <&i2c1_pins>; 134 pinctrl-names = "default"; 135 #address-cells = <0x1>; 136 #size-cells = <0x0>; 137 power-domains = <&ps_i2c1>; 138 }; 139 140 i2c2: i2c@235018000 { 141 compatible = "apple,t8103-i2c", "apple,i2c"; 142 reg = <0x2 0x35018000 0x0 0x4000>; 143 clocks = <&clk24>; 144 interrupt-parent = <&aic>; 145 interrupts = <AIC_IRQ 629 IRQ_TYPE_LEVEL_HIGH>; 146 pinctrl-0 = <&i2c2_pins>; 147 pinctrl-names = "default"; 148 #address-cells = <0x1>; 149 #size-cells = <0x0>; 150 status = "disabled"; /* not used in all devices */ 151 power-domains = <&ps_i2c2>; 152 }; 153 154 i2c3: i2c@23501c000 { 155 compatible = "apple,t8103-i2c", "apple,i2c"; 156 reg = <0x2 0x3501c000 0x0 0x4000>; 157 clocks = <&clk24>; 158 interrupt-parent = <&aic>; 159 interrupts = <AIC_IRQ 630 IRQ_TYPE_LEVEL_HIGH>; 160 pinctrl-0 = <&i2c3_pins>; 161 pinctrl-names = "default"; 162 #address-cells = <0x1>; 163 #size-cells = <0x0>; 164 power-domains = <&ps_i2c3>; 165 }; 166 167 i2c4: i2c@235020000 { 168 compatible = "apple,t8103-i2c", "apple,i2c"; 169 reg = <0x2 0x35020000 0x0 0x4000>; 170 clocks = <&clk24>; 171 interrupt-parent = <&aic>; 172 interrupts = <AIC_IRQ 631 IRQ_TYPE_LEVEL_HIGH>; 173 pinctrl-0 = <&i2c4_pins>; 174 pinctrl-names = "default"; 175 #address-cells = <0x1>; 176 #size-cells = <0x0>; 177 power-domains = <&ps_i2c4>; 178 status = "disabled"; /* only used in J293 */ 179 }; 180 181 serial0: serial@235200000 { 182 compatible = "apple,s5l-uart"; 183 reg = <0x2 0x35200000 0x0 0x1000>; 184 reg-io-width = <4>; 185 interrupt-parent = <&aic>; 186 interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>; 187 /* 188 * TODO: figure out the clocking properly, there may 189 * be a third selectable clock. 190 */ 191 clocks = <&clk24>, <&clk24>; 192 clock-names = "uart", "clk_uart_baud0"; 193 power-domains = <&ps_uart0>; 194 status = "disabled"; 195 }; 196 197 aic: interrupt-controller@23b100000 { 198 compatible = "apple,t8103-aic", "apple,aic"; 199 #interrupt-cells = <3>; 200 interrupt-controller; 201 reg = <0x2 0x3b100000 0x0 0x8000>; 202 power-domains = <&ps_aic>; 203 }; 204 205 pmgr: power-management@23b700000 { 206 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 207 #address-cells = <1>; 208 #size-cells = <1>; 209 reg = <0x2 0x3b700000 0 0x14000>; 210 }; 211 212 pinctrl_ap: pinctrl@23c100000 { 213 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 214 reg = <0x2 0x3c100000 0x0 0x100000>; 215 power-domains = <&ps_gpio>; 216 217 gpio-controller; 218 #gpio-cells = <2>; 219 gpio-ranges = <&pinctrl_ap 0 0 212>; 220 apple,npins = <212>; 221 222 interrupt-controller; 223 #interrupt-cells = <2>; 224 interrupt-parent = <&aic>; 225 interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>, 226 <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>, 227 <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>, 228 <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>, 229 <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>, 230 <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, 231 <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>; 232 233 i2c0_pins: i2c0-pins { 234 pinmux = <APPLE_PINMUX(192, 1)>, 235 <APPLE_PINMUX(188, 1)>; 236 }; 237 238 i2c1_pins: i2c1-pins { 239 pinmux = <APPLE_PINMUX(201, 1)>, 240 <APPLE_PINMUX(199, 1)>; 241 }; 242 243 i2c2_pins: i2c2-pins { 244 pinmux = <APPLE_PINMUX(163, 1)>, 245 <APPLE_PINMUX(162, 1)>; 246 }; 247 248 i2c3_pins: i2c3-pins { 249 pinmux = <APPLE_PINMUX(73, 1)>, 250 <APPLE_PINMUX(72, 1)>; 251 }; 252 253 i2c4_pins: i2c4-pins { 254 pinmux = <APPLE_PINMUX(135, 1)>, 255 <APPLE_PINMUX(134, 1)>; 256 }; 257 258 pcie_pins: pcie-pins { 259 pinmux = <APPLE_PINMUX(150, 1)>, 260 <APPLE_PINMUX(151, 1)>, 261 <APPLE_PINMUX(32, 1)>; 262 }; 263 }; 264 265 pmgr_mini: power-management@23d280000 { 266 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 267 #address-cells = <1>; 268 #size-cells = <1>; 269 reg = <0x2 0x3d280000 0 0x4000>; 270 }; 271 272 pinctrl_aop: pinctrl@24a820000 { 273 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 274 reg = <0x2 0x4a820000 0x0 0x4000>; 275 276 gpio-controller; 277 #gpio-cells = <2>; 278 gpio-ranges = <&pinctrl_aop 0 0 42>; 279 apple,npins = <42>; 280 281 interrupt-controller; 282 #interrupt-cells = <2>; 283 interrupt-parent = <&aic>; 284 interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>, 285 <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>, 286 <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>, 287 <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>, 288 <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>, 289 <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, 290 <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>; 291 }; 292 293 pinctrl_nub: pinctrl@23d1f0000 { 294 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 295 reg = <0x2 0x3d1f0000 0x0 0x4000>; 296 power-domains = <&ps_nub_gpio>; 297 298 gpio-controller; 299 #gpio-cells = <2>; 300 gpio-ranges = <&pinctrl_nub 0 0 23>; 301 apple,npins = <23>; 302 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 interrupt-parent = <&aic>; 306 interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>, 307 <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>, 308 <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>, 309 <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>, 310 <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>, 311 <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>, 312 <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>; 313 }; 314 315 pinctrl_smc: pinctrl@23e820000 { 316 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 317 reg = <0x2 0x3e820000 0x0 0x4000>; 318 319 gpio-controller; 320 #gpio-cells = <2>; 321 gpio-ranges = <&pinctrl_smc 0 0 16>; 322 apple,npins = <16>; 323 324 interrupt-controller; 325 #interrupt-cells = <2>; 326 interrupt-parent = <&aic>; 327 interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>, 328 <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>, 329 <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>, 330 <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>, 331 <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>, 332 <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>, 333 <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>; 334 }; 335 336 pcie0_dart_0: dart@681008000 { 337 compatible = "apple,t8103-dart"; 338 reg = <0x6 0x81008000 0x0 0x4000>; 339 #iommu-cells = <1>; 340 interrupt-parent = <&aic>; 341 interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>; 342 power-domains = <&ps_apcie_gp>; 343 }; 344 345 pcie0_dart_1: dart@682008000 { 346 compatible = "apple,t8103-dart"; 347 reg = <0x6 0x82008000 0x0 0x4000>; 348 #iommu-cells = <1>; 349 interrupt-parent = <&aic>; 350 interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>; 351 power-domains = <&ps_apcie_gp>; 352 }; 353 354 pcie0_dart_2: dart@683008000 { 355 compatible = "apple,t8103-dart"; 356 reg = <0x6 0x83008000 0x0 0x4000>; 357 #iommu-cells = <1>; 358 interrupt-parent = <&aic>; 359 interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>; 360 power-domains = <&ps_apcie_gp>; 361 }; 362 363 pcie0: pcie@690000000 { 364 compatible = "apple,t8103-pcie", "apple,pcie"; 365 device_type = "pci"; 366 367 reg = <0x6 0x90000000 0x0 0x1000000>, 368 <0x6 0x80000000 0x0 0x100000>, 369 <0x6 0x81000000 0x0 0x4000>, 370 <0x6 0x82000000 0x0 0x4000>, 371 <0x6 0x83000000 0x0 0x4000>; 372 reg-names = "config", "rc", "port0", "port1", "port2"; 373 374 interrupt-parent = <&aic>; 375 interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, 376 <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, 377 <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; 378 379 msi-controller; 380 msi-parent = <&pcie0>; 381 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; 382 383 384 iommu-map = <0x100 &pcie0_dart_0 1 1>, 385 <0x200 &pcie0_dart_1 1 1>, 386 <0x300 &pcie0_dart_2 1 1>; 387 iommu-map-mask = <0xff00>; 388 389 bus-range = <0 3>; 390 #address-cells = <3>; 391 #size-cells = <2>; 392 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, 393 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; 394 395 power-domains = <&ps_apcie_gp>; 396 pinctrl-0 = <&pcie_pins>; 397 pinctrl-names = "default"; 398 399 port00: pci@0,0 { 400 device_type = "pci"; 401 reg = <0x0 0x0 0x0 0x0 0x0>; 402 reset-gpios = <&pinctrl_ap 152 0>; 403 max-link-speed = <2>; 404 405 #address-cells = <3>; 406 #size-cells = <2>; 407 ranges; 408 409 interrupt-controller; 410 #interrupt-cells = <1>; 411 412 interrupt-map-mask = <0 0 0 7>; 413 interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 414 <0 0 0 2 &port00 0 0 0 1>, 415 <0 0 0 3 &port00 0 0 0 2>, 416 <0 0 0 4 &port00 0 0 0 3>; 417 }; 418 419 port01: pci@1,0 { 420 device_type = "pci"; 421 reg = <0x800 0x0 0x0 0x0 0x0>; 422 reset-gpios = <&pinctrl_ap 153 0>; 423 max-link-speed = <2>; 424 425 #address-cells = <3>; 426 #size-cells = <2>; 427 ranges; 428 429 interrupt-controller; 430 #interrupt-cells = <1>; 431 432 interrupt-map-mask = <0 0 0 7>; 433 interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 434 <0 0 0 2 &port01 0 0 0 1>, 435 <0 0 0 3 &port01 0 0 0 2>, 436 <0 0 0 4 &port01 0 0 0 3>; 437 }; 438 439 port02: pci@2,0 { 440 device_type = "pci"; 441 reg = <0x1000 0x0 0x0 0x0 0x0>; 442 reset-gpios = <&pinctrl_ap 33 0>; 443 max-link-speed = <1>; 444 445 #address-cells = <3>; 446 #size-cells = <2>; 447 ranges; 448 449 interrupt-controller; 450 #interrupt-cells = <1>; 451 452 interrupt-map-mask = <0 0 0 7>; 453 interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 454 <0 0 0 2 &port02 0 0 0 1>, 455 <0 0 0 3 &port02 0 0 0 2>, 456 <0 0 0 4 &port02 0 0 0 3>; 457 }; 458 }; 459 }; 460}; 461 462#include "t8103-pmgr.dtsi" 463