1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Apple T8103 "M1" SoC
4 *
5 * Other names: H13G, "Tonga"
6 *
7 * Copyright The Asahi Linux Contributors
8 */
9
10#include <dt-bindings/interrupt-controller/apple-aic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/pinctrl/apple.h>
13
14/ {
15	compatible = "apple,t8103", "apple,arm-platform";
16
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	cpus {
21		#address-cells = <2>;
22		#size-cells = <0>;
23
24		cpu0: cpu@0 {
25			compatible = "apple,icestorm";
26			device_type = "cpu";
27			reg = <0x0 0x0>;
28			enable-method = "spin-table";
29			cpu-release-addr = <0 0>; /* To be filled by loader */
30		};
31
32		cpu1: cpu@1 {
33			compatible = "apple,icestorm";
34			device_type = "cpu";
35			reg = <0x0 0x1>;
36			enable-method = "spin-table";
37			cpu-release-addr = <0 0>; /* To be filled by loader */
38		};
39
40		cpu2: cpu@2 {
41			compatible = "apple,icestorm";
42			device_type = "cpu";
43			reg = <0x0 0x2>;
44			enable-method = "spin-table";
45			cpu-release-addr = <0 0>; /* To be filled by loader */
46		};
47
48		cpu3: cpu@3 {
49			compatible = "apple,icestorm";
50			device_type = "cpu";
51			reg = <0x0 0x3>;
52			enable-method = "spin-table";
53			cpu-release-addr = <0 0>; /* To be filled by loader */
54		};
55
56		cpu4: cpu@10100 {
57			compatible = "apple,firestorm";
58			device_type = "cpu";
59			reg = <0x0 0x10100>;
60			enable-method = "spin-table";
61			cpu-release-addr = <0 0>; /* To be filled by loader */
62		};
63
64		cpu5: cpu@10101 {
65			compatible = "apple,firestorm";
66			device_type = "cpu";
67			reg = <0x0 0x10101>;
68			enable-method = "spin-table";
69			cpu-release-addr = <0 0>; /* To be filled by loader */
70		};
71
72		cpu6: cpu@10102 {
73			compatible = "apple,firestorm";
74			device_type = "cpu";
75			reg = <0x0 0x10102>;
76			enable-method = "spin-table";
77			cpu-release-addr = <0 0>; /* To be filled by loader */
78		};
79
80		cpu7: cpu@10103 {
81			compatible = "apple,firestorm";
82			device_type = "cpu";
83			reg = <0x0 0x10103>;
84			enable-method = "spin-table";
85			cpu-release-addr = <0 0>; /* To be filled by loader */
86		};
87	};
88
89	timer {
90		compatible = "arm,armv8-timer";
91		interrupt-parent = <&aic>;
92		interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
93		interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
94			     <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
95			     <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
96			     <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
97	};
98
99	clk24: clock-24m {
100		compatible = "fixed-clock";
101		#clock-cells = <0>;
102		clock-frequency = <24000000>;
103		clock-output-names = "clk24";
104	};
105
106	soc {
107		compatible = "simple-bus";
108		#address-cells = <2>;
109		#size-cells = <2>;
110
111		ranges;
112		nonposted-mmio;
113
114		serial0: serial@235200000 {
115			compatible = "apple,s5l-uart";
116			reg = <0x2 0x35200000 0x0 0x1000>;
117			reg-io-width = <4>;
118			interrupt-parent = <&aic>;
119			interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>;
120			/*
121			 * TODO: figure out the clocking properly, there may
122			 * be a third selectable clock.
123			 */
124			clocks = <&clk24>, <&clk24>;
125			clock-names = "uart", "clk_uart_baud0";
126			status = "disabled";
127		};
128
129		aic: interrupt-controller@23b100000 {
130			compatible = "apple,t8103-aic", "apple,aic";
131			#interrupt-cells = <3>;
132			interrupt-controller;
133			reg = <0x2 0x3b100000 0x0 0x8000>;
134		};
135
136		pinctrl_ap: pinctrl@23c100000 {
137			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
138			reg = <0x2 0x3c100000 0x0 0x100000>;
139
140			gpio-controller;
141			#gpio-cells = <2>;
142			gpio-ranges = <&pinctrl_ap 0 0 212>;
143			apple,npins = <212>;
144
145			interrupt-controller;
146			#interrupt-cells = <2>;
147			interrupt-parent = <&aic>;
148			interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>,
149				     <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>,
150				     <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>,
151				     <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>,
152				     <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>,
153				     <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>,
154				     <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>;
155
156			pcie_pins: pcie-pins {
157				pinmux = <APPLE_PINMUX(150, 1)>,
158					 <APPLE_PINMUX(151, 1)>,
159					 <APPLE_PINMUX(32, 1)>;
160			};
161		};
162
163		pinctrl_aop: pinctrl@24a820000 {
164			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
165			reg = <0x2 0x4a820000 0x0 0x4000>;
166
167			gpio-controller;
168			#gpio-cells = <2>;
169			gpio-ranges = <&pinctrl_aop 0 0 42>;
170			apple,npins = <42>;
171
172			interrupt-controller;
173			#interrupt-cells = <2>;
174			interrupt-parent = <&aic>;
175			interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>,
176				     <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>,
177				     <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>,
178				     <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>,
179				     <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>,
180				     <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>,
181				     <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>;
182		};
183
184		pinctrl_nub: pinctrl@23d1f0000 {
185			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
186			reg = <0x2 0x3d1f0000 0x0 0x4000>;
187
188			gpio-controller;
189			#gpio-cells = <2>;
190			gpio-ranges = <&pinctrl_nub 0 0 23>;
191			apple,npins = <23>;
192
193			interrupt-controller;
194			#interrupt-cells = <2>;
195			interrupt-parent = <&aic>;
196			interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>,
197				     <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>,
198				     <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>,
199				     <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>,
200				     <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>,
201				     <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>,
202				     <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>;
203		};
204
205		pinctrl_smc: pinctrl@23e820000 {
206			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
207			reg = <0x2 0x3e820000 0x0 0x4000>;
208
209			gpio-controller;
210			#gpio-cells = <2>;
211			gpio-ranges = <&pinctrl_smc 0 0 16>;
212			apple,npins = <16>;
213
214			interrupt-controller;
215			#interrupt-cells = <2>;
216			interrupt-parent = <&aic>;
217			interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>,
218				     <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>,
219				     <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>,
220				     <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>,
221				     <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>,
222				     <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>,
223				     <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>;
224		};
225
226		pcie0_dart_0: dart@681008000 {
227			compatible = "apple,t8103-dart";
228			reg = <0x6 0x81008000 0x0 0x4000>;
229			#iommu-cells = <1>;
230			interrupt-parent = <&aic>;
231			interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>;
232		};
233
234		pcie0_dart_1: dart@682008000 {
235			compatible = "apple,t8103-dart";
236			reg = <0x6 0x82008000 0x0 0x4000>;
237			#iommu-cells = <1>;
238			interrupt-parent = <&aic>;
239			interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>;
240		};
241
242		pcie0_dart_2: dart@683008000 {
243			compatible = "apple,t8103-dart";
244			reg = <0x6 0x83008000 0x0 0x4000>;
245			#iommu-cells = <1>;
246			interrupt-parent = <&aic>;
247			interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>;
248		};
249
250		pcie0: pcie@690000000 {
251			compatible = "apple,t8103-pcie", "apple,pcie";
252			device_type = "pci";
253
254			reg = <0x6 0x90000000 0x0 0x1000000>,
255			      <0x6 0x80000000 0x0 0x100000>,
256			      <0x6 0x81000000 0x0 0x4000>,
257			      <0x6 0x82000000 0x0 0x4000>,
258			      <0x6 0x83000000 0x0 0x4000>;
259			reg-names = "config", "rc", "port0", "port1", "port2";
260
261			interrupt-parent = <&aic>;
262			interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
263				     <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
264				     <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;
265
266			msi-controller;
267			msi-parent = <&pcie0>;
268			msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
269
270
271			iommu-map = <0x100 &pcie0_dart_0 1 1>,
272				    <0x200 &pcie0_dart_1 1 1>,
273				    <0x300 &pcie0_dart_2 1 1>;
274			iommu-map-mask = <0xff00>;
275
276			bus-range = <0 3>;
277			#address-cells = <3>;
278			#size-cells = <2>;
279			ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
280				 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
281
282			pinctrl-0 = <&pcie_pins>;
283			pinctrl-names = "default";
284
285			port00: pci@0,0 {
286				device_type = "pci";
287				reg = <0x0 0x0 0x0 0x0 0x0>;
288				reset-gpios = <&pinctrl_ap 152 0>;
289				max-link-speed = <2>;
290
291				#address-cells = <3>;
292				#size-cells = <2>;
293				ranges;
294
295				interrupt-controller;
296				#interrupt-cells = <1>;
297
298				interrupt-map-mask = <0 0 0 7>;
299				interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
300						<0 0 0 2 &port00 0 0 0 1>,
301						<0 0 0 3 &port00 0 0 0 2>,
302						<0 0 0 4 &port00 0 0 0 3>;
303			};
304
305			port01: pci@1,0 {
306				device_type = "pci";
307				reg = <0x800 0x0 0x0 0x0 0x0>;
308				reset-gpios = <&pinctrl_ap 153 0>;
309				max-link-speed = <2>;
310
311				#address-cells = <3>;
312				#size-cells = <2>;
313				ranges;
314
315				interrupt-controller;
316				#interrupt-cells = <1>;
317
318				interrupt-map-mask = <0 0 0 7>;
319				interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
320						<0 0 0 2 &port01 0 0 0 1>,
321						<0 0 0 3 &port01 0 0 0 2>,
322						<0 0 0 4 &port01 0 0 0 3>;
323			};
324
325			port02: pci@2,0 {
326				device_type = "pci";
327				reg = <0x1000 0x0 0x0 0x0 0x0>;
328				reset-gpios = <&pinctrl_ap 33 0>;
329				max-link-speed = <1>;
330
331				#address-cells = <3>;
332				#size-cells = <2>;
333				ranges;
334
335				interrupt-controller;
336				#interrupt-cells = <1>;
337
338				interrupt-map-mask = <0 0 0 7>;
339				interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
340						<0 0 0 2 &port02 0 0 0 1>,
341						<0 0 0 3 &port02 0 0 0 2>,
342						<0 0 0 4 &port02 0 0 0 3>;
343			};
344		};
345	};
346};
347