1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Devices used on die 0 on the Apple T6002 "M1 Ultra" SoC and present on 4 * Apple T6000 / T6001 "M1 Pro" / "M1 Max". 5 * 6 * Copyright The Asahi Linux Contributors 7 */ 8 9 10 aic: interrupt-controller@28e100000 { 11 compatible = "apple,t6000-aic", "apple,aic2"; 12 #interrupt-cells = <4>; 13 interrupt-controller; 14 reg = <0x2 0x8e100000 0x0 0xc000>, 15 <0x2 0x8e10c000 0x0 0x4>; 16 reg-names = "core", "event"; 17 power-domains = <&ps_aic>; 18 }; 19 20 pinctrl_smc: pinctrl@290820000 { 21 compatible = "apple,t6000-pinctrl", "apple,pinctrl"; 22 reg = <0x2 0x90820000 0x0 0x4000>; 23 24 gpio-controller; 25 #gpio-cells = <2>; 26 gpio-ranges = <&pinctrl_smc 0 0 30>; 27 apple,npins = <30>; 28 29 interrupt-controller; 30 #interrupt-cells = <2>; 31 interrupt-parent = <&aic>; 32 interrupts = <AIC_IRQ 0 743 IRQ_TYPE_LEVEL_HIGH>, 33 <AIC_IRQ 0 744 IRQ_TYPE_LEVEL_HIGH>, 34 <AIC_IRQ 0 745 IRQ_TYPE_LEVEL_HIGH>, 35 <AIC_IRQ 0 746 IRQ_TYPE_LEVEL_HIGH>, 36 <AIC_IRQ 0 747 IRQ_TYPE_LEVEL_HIGH>, 37 <AIC_IRQ 0 748 IRQ_TYPE_LEVEL_HIGH>, 38 <AIC_IRQ 0 749 IRQ_TYPE_LEVEL_HIGH>; 39 }; 40 41 wdt: watchdog@2922b0000 { 42 compatible = "apple,t6000-wdt", "apple,wdt"; 43 reg = <0x2 0x922b0000 0x0 0x4000>; 44 clocks = <&clkref>; 45 interrupt-parent = <&aic>; 46 interrupts = <AIC_IRQ 0 631 IRQ_TYPE_LEVEL_HIGH>; 47 }; 48 49 i2c0: i2c@39b040000 { 50 compatible = "apple,t6000-i2c", "apple,i2c"; 51 reg = <0x3 0x9b040000 0x0 0x4000>; 52 clocks = <&clkref>; 53 interrupt-parent = <&aic>; 54 interrupts = <AIC_IRQ 0 1119 IRQ_TYPE_LEVEL_HIGH>; 55 pinctrl-0 = <&i2c0_pins>; 56 pinctrl-names = "default"; 57 power-domains = <&ps_i2c0>; 58 #address-cells = <0x1>; 59 #size-cells = <0x0>; 60 }; 61 62 i2c1: i2c@39b044000 { 63 compatible = "apple,t6000-i2c", "apple,i2c"; 64 reg = <0x3 0x9b044000 0x0 0x4000>; 65 clocks = <&clkref>; 66 interrupt-parent = <&aic>; 67 interrupts = <AIC_IRQ 0 1120 IRQ_TYPE_LEVEL_HIGH>; 68 pinctrl-0 = <&i2c1_pins>; 69 pinctrl-names = "default"; 70 power-domains = <&ps_i2c1>; 71 #address-cells = <0x1>; 72 #size-cells = <0x0>; 73 status = "disabled"; 74 }; 75 76 i2c2: i2c@39b048000 { 77 compatible = "apple,t6000-i2c", "apple,i2c"; 78 reg = <0x3 0x9b048000 0x0 0x4000>; 79 clocks = <&clkref>; 80 interrupt-parent = <&aic>; 81 interrupts = <AIC_IRQ 0 1121 IRQ_TYPE_LEVEL_HIGH>; 82 pinctrl-0 = <&i2c2_pins>; 83 pinctrl-names = "default"; 84 power-domains = <&ps_i2c2>; 85 #address-cells = <0x1>; 86 #size-cells = <0x0>; 87 status = "disabled"; 88 }; 89 90 i2c3: i2c@39b04c000 { 91 compatible = "apple,t6000-i2c", "apple,i2c"; 92 reg = <0x3 0x9b04c000 0x0 0x4000>; 93 clocks = <&clkref>; 94 interrupt-parent = <&aic>; 95 interrupts = <AIC_IRQ 0 1122 IRQ_TYPE_LEVEL_HIGH>; 96 pinctrl-0 = <&i2c3_pins>; 97 pinctrl-names = "default"; 98 power-domains = <&ps_i2c3>; 99 #address-cells = <0x1>; 100 #size-cells = <0x0>; 101 status = "disabled"; 102 }; 103 104 i2c4: i2c@39b050000 { 105 compatible = "apple,t6000-i2c", "apple,i2c"; 106 reg = <0x3 0x9b050000 0x0 0x4000>; 107 clocks = <&clkref>; 108 interrupt-parent = <&aic>; 109 interrupts = <AIC_IRQ 0 1123 IRQ_TYPE_LEVEL_HIGH>; 110 pinctrl-0 = <&i2c4_pins>; 111 pinctrl-names = "default"; 112 power-domains = <&ps_i2c4>; 113 #address-cells = <0x1>; 114 #size-cells = <0x0>; 115 status = "disabled"; 116 }; 117 118 i2c5: i2c@39b054000 { 119 compatible = "apple,t6000-i2c", "apple,i2c"; 120 reg = <0x3 0x9b054000 0x0 0x4000>; 121 clocks = <&clkref>; 122 interrupt-parent = <&aic>; 123 interrupts = <AIC_IRQ 0 1124 IRQ_TYPE_LEVEL_HIGH>; 124 pinctrl-0 = <&i2c5_pins>; 125 pinctrl-names = "default"; 126 power-domains = <&ps_i2c5>; 127 #address-cells = <0x1>; 128 #size-cells = <0x0>; 129 status = "disabled"; 130 }; 131 132 serial0: serial@39b200000 { 133 compatible = "apple,s5l-uart"; 134 reg = <0x3 0x9b200000 0x0 0x1000>; 135 reg-io-width = <4>; 136 interrupt-parent = <&aic>; 137 interrupts = <AIC_IRQ 0 1097 IRQ_TYPE_LEVEL_HIGH>; 138 /* 139 * TODO: figure out the clocking properly, there may 140 * be a third selectable clock. 141 */ 142 clocks = <&clkref>, <&clkref>; 143 clock-names = "uart", "clk_uart_baud0"; 144 power-domains = <&ps_uart0>; 145 status = "disabled"; 146 }; 147 148 pcie0_dart_0: dart@581008000 { 149 compatible = "apple,t6000-dart"; 150 reg = <0x5 0x81008000 0x0 0x4000>; 151 #iommu-cells = <1>; 152 interrupt-parent = <&aic>; 153 interrupts = <AIC_IRQ 0 1271 IRQ_TYPE_LEVEL_HIGH>; 154 power-domains = <&ps_apcie_gp_sys>; 155 }; 156 157 pcie0_dart_1: dart@582008000 { 158 compatible = "apple,t6000-dart"; 159 reg = <0x5 0x82008000 0x0 0x4000>; 160 #iommu-cells = <1>; 161 interrupt-parent = <&aic>; 162 interrupts = <AIC_IRQ 0 1274 IRQ_TYPE_LEVEL_HIGH>; 163 power-domains = <&ps_apcie_gp_sys>; 164 }; 165 166 pcie0_dart_2: dart@583008000 { 167 compatible = "apple,t6000-dart"; 168 reg = <0x5 0x83008000 0x0 0x4000>; 169 #iommu-cells = <1>; 170 interrupt-parent = <&aic>; 171 interrupts = <AIC_IRQ 0 1277 IRQ_TYPE_LEVEL_HIGH>; 172 power-domains = <&ps_apcie_gp_sys>; 173 }; 174 175 pcie0_dart_3: dart@584008000 { 176 compatible = "apple,t6000-dart"; 177 reg = <0x5 0x84008000 0x0 0x4000>; 178 #iommu-cells = <1>; 179 interrupt-parent = <&aic>; 180 interrupts = <AIC_IRQ 0 1280 IRQ_TYPE_LEVEL_HIGH>; 181 power-domains = <&ps_apcie_gp_sys>; 182 }; 183 184 pcie0: pcie@590000000 { 185 compatible = "apple,t6000-pcie", "apple,pcie"; 186 device_type = "pci"; 187 188 reg = <0x5 0x90000000 0x0 0x1000000>, 189 <0x5 0x80000000 0x0 0x100000>, 190 <0x5 0x81000000 0x0 0x4000>, 191 <0x5 0x82000000 0x0 0x4000>, 192 <0x5 0x83000000 0x0 0x4000>, 193 <0x5 0x84000000 0x0 0x4000>; 194 reg-names = "config", "rc", "port0", "port1", "port2", "port3"; 195 196 interrupt-parent = <&aic>; 197 interrupts = <AIC_IRQ 0 1270 IRQ_TYPE_LEVEL_HIGH>, 198 <AIC_IRQ 0 1273 IRQ_TYPE_LEVEL_HIGH>, 199 <AIC_IRQ 0 1276 IRQ_TYPE_LEVEL_HIGH>, 200 <AIC_IRQ 0 1279 IRQ_TYPE_LEVEL_HIGH>; 201 202 msi-controller; 203 msi-parent = <&pcie0>; 204 msi-ranges = <&aic AIC_IRQ 0 1581 IRQ_TYPE_EDGE_RISING 32>; 205 206 207 iommu-map = <0x100 &pcie0_dart_0 1 1>, 208 <0x200 &pcie0_dart_1 1 1>, 209 <0x300 &pcie0_dart_2 1 1>, 210 <0x400 &pcie0_dart_3 1 1>; 211 iommu-map-mask = <0xff00>; 212 213 bus-range = <0 4>; 214 #address-cells = <3>; 215 #size-cells = <2>; 216 ranges = <0x43000000 0x5 0xa0000000 0x5 0xa0000000 0x0 0x20000000>, 217 <0x02000000 0x0 0xc0000000 0x5 0xc0000000 0x0 0x40000000>; 218 219 power-domains = <&ps_apcie_gp_sys>; 220 pinctrl-0 = <&pcie_pins>; 221 pinctrl-names = "default"; 222 223 port00: pci@0,0 { 224 device_type = "pci"; 225 reg = <0x0 0x0 0x0 0x0 0x0>; 226 reset-gpios = <&pinctrl_ap 4 GPIO_ACTIVE_LOW>; 227 228 #address-cells = <3>; 229 #size-cells = <2>; 230 ranges; 231 232 interrupt-controller; 233 #interrupt-cells = <1>; 234 235 interrupt-map-mask = <0 0 0 7>; 236 interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 237 <0 0 0 2 &port00 0 0 0 1>, 238 <0 0 0 3 &port00 0 0 0 2>, 239 <0 0 0 4 &port00 0 0 0 3>; 240 }; 241 242 port01: pci@1,0 { 243 device_type = "pci"; 244 reg = <0x800 0x0 0x0 0x0 0x0>; 245 reset-gpios = <&pinctrl_ap 5 GPIO_ACTIVE_LOW>; 246 247 #address-cells = <3>; 248 #size-cells = <2>; 249 ranges; 250 251 interrupt-controller; 252 #interrupt-cells = <1>; 253 254 interrupt-map-mask = <0 0 0 7>; 255 interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 256 <0 0 0 2 &port01 0 0 0 1>, 257 <0 0 0 3 &port01 0 0 0 2>, 258 <0 0 0 4 &port01 0 0 0 3>; 259 }; 260 261 port02: pci@2,0 { 262 device_type = "pci"; 263 reg = <0x1000 0x0 0x0 0x0 0x0>; 264 reset-gpios = <&pinctrl_ap 6 GPIO_ACTIVE_LOW>; 265 266 #address-cells = <3>; 267 #size-cells = <2>; 268 ranges; 269 270 interrupt-controller; 271 #interrupt-cells = <1>; 272 273 interrupt-map-mask = <0 0 0 7>; 274 interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 275 <0 0 0 2 &port02 0 0 0 1>, 276 <0 0 0 3 &port02 0 0 0 2>, 277 <0 0 0 4 &port02 0 0 0 3>; 278 }; 279 280 port03: pci@3,0 { 281 device_type = "pci"; 282 reg = <0x1800 0x0 0x0 0x0 0x0>; 283 reset-gpios = <&pinctrl_ap 7 GPIO_ACTIVE_LOW>; 284 285 #address-cells = <3>; 286 #size-cells = <2>; 287 ranges; 288 289 interrupt-controller; 290 #interrupt-cells = <1>; 291 292 interrupt-map-mask = <0 0 0 7>; 293 interrupt-map = <0 0 0 1 &port03 0 0 0 0>, 294 <0 0 0 2 &port03 0 0 0 1>, 295 <0 0 0 3 &port03 0 0 0 2>, 296 <0 0 0 4 &port03 0 0 0 3>; 297 }; 298 }; 299