1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Common Apple T6000 / T6001 / T6002 "M1 Pro/Max/Ultra" SoC 4 * 5 * Other names: H13J, "Jade Chop", "Jade", "Jade 2C" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10/ { 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 cpus { 15 #address-cells = <2>; 16 #size-cells = <0>; 17 18 cpu_e00: cpu@0 { 19 compatible = "apple,icestorm"; 20 device_type = "cpu"; 21 reg = <0x0 0x0>; 22 enable-method = "spin-table"; 23 cpu-release-addr = <0 0>; /* To be filled by loader */ 24 next-level-cache = <&l2_cache_0>; 25 i-cache-size = <0x20000>; 26 d-cache-size = <0x10000>; 27 }; 28 29 cpu_e01: cpu@1 { 30 compatible = "apple,icestorm"; 31 device_type = "cpu"; 32 reg = <0x0 0x1>; 33 enable-method = "spin-table"; 34 cpu-release-addr = <0 0>; /* To be filled by loader */ 35 next-level-cache = <&l2_cache_0>; 36 i-cache-size = <0x20000>; 37 d-cache-size = <0x10000>; 38 }; 39 40 cpu_p00: cpu@10100 { 41 compatible = "apple,firestorm"; 42 device_type = "cpu"; 43 reg = <0x0 0x10100>; 44 enable-method = "spin-table"; 45 cpu-release-addr = <0 0>; /* To be filled by loader */ 46 next-level-cache = <&l2_cache_1>; 47 i-cache-size = <0x30000>; 48 d-cache-size = <0x20000>; 49 }; 50 51 cpu_p01: cpu@10101 { 52 compatible = "apple,firestorm"; 53 device_type = "cpu"; 54 reg = <0x0 0x10101>; 55 enable-method = "spin-table"; 56 cpu-release-addr = <0 0>; /* To be filled by loader */ 57 next-level-cache = <&l2_cache_1>; 58 i-cache-size = <0x30000>; 59 d-cache-size = <0x20000>; 60 }; 61 62 cpu_p02: cpu@10102 { 63 compatible = "apple,firestorm"; 64 device_type = "cpu"; 65 reg = <0x0 0x10102>; 66 enable-method = "spin-table"; 67 cpu-release-addr = <0 0>; /* To be filled by loader */ 68 next-level-cache = <&l2_cache_1>; 69 i-cache-size = <0x30000>; 70 d-cache-size = <0x20000>; 71 }; 72 73 cpu_p03: cpu@10103 { 74 compatible = "apple,firestorm"; 75 device_type = "cpu"; 76 reg = <0x0 0x10103>; 77 enable-method = "spin-table"; 78 cpu-release-addr = <0 0>; /* To be filled by loader */ 79 next-level-cache = <&l2_cache_1>; 80 i-cache-size = <0x30000>; 81 d-cache-size = <0x20000>; 82 }; 83 84 cpu_p10: cpu@10200 { 85 compatible = "apple,firestorm"; 86 device_type = "cpu"; 87 reg = <0x0 0x10200>; 88 enable-method = "spin-table"; 89 cpu-release-addr = <0 0>; /* To be filled by loader */ 90 next-level-cache = <&l2_cache_2>; 91 i-cache-size = <0x30000>; 92 d-cache-size = <0x20000>; 93 }; 94 95 cpu_p11: cpu@10201 { 96 compatible = "apple,firestorm"; 97 device_type = "cpu"; 98 reg = <0x0 0x10201>; 99 enable-method = "spin-table"; 100 cpu-release-addr = <0 0>; /* To be filled by loader */ 101 next-level-cache = <&l2_cache_2>; 102 i-cache-size = <0x30000>; 103 d-cache-size = <0x20000>; 104 }; 105 106 cpu_p12: cpu@10202 { 107 compatible = "apple,firestorm"; 108 device_type = "cpu"; 109 reg = <0x0 0x10202>; 110 enable-method = "spin-table"; 111 cpu-release-addr = <0 0>; /* To be filled by loader */ 112 next-level-cache = <&l2_cache_2>; 113 i-cache-size = <0x30000>; 114 d-cache-size = <0x20000>; 115 }; 116 117 cpu_p13: cpu@10203 { 118 compatible = "apple,firestorm"; 119 device_type = "cpu"; 120 reg = <0x0 0x10203>; 121 enable-method = "spin-table"; 122 cpu-release-addr = <0 0>; /* To be filled by loader */ 123 next-level-cache = <&l2_cache_2>; 124 i-cache-size = <0x30000>; 125 d-cache-size = <0x20000>; 126 }; 127 128 l2_cache_0: l2-cache-0 { 129 compatible = "cache"; 130 cache-level = <2>; 131 cache-unified; 132 cache-size = <0x400000>; 133 }; 134 135 l2_cache_1: l2-cache-1 { 136 compatible = "cache"; 137 cache-level = <2>; 138 cache-unified; 139 cache-size = <0xc00000>; 140 }; 141 142 l2_cache_2: l2-cache-2 { 143 compatible = "cache"; 144 cache-level = <2>; 145 cache-unified; 146 cache-size = <0xc00000>; 147 }; 148 }; 149 150 pmu-e { 151 compatible = "apple,icestorm-pmu"; 152 interrupt-parent = <&aic>; 153 interrupts = <AIC_FIQ 0 AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>; 154 }; 155 156 pmu-p { 157 compatible = "apple,firestorm-pmu"; 158 interrupt-parent = <&aic>; 159 interrupts = <AIC_FIQ 0 AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>; 160 }; 161 162 timer { 163 compatible = "arm,armv8-timer"; 164 interrupt-parent = <&aic>; 165 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 166 interrupts = <AIC_FIQ 0 AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 167 <AIC_FIQ 0 AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 168 <AIC_FIQ 0 AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 169 <AIC_FIQ 0 AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 170 }; 171 172 clkref: clock-ref { 173 compatible = "fixed-clock"; 174 #clock-cells = <0>; 175 clock-frequency = <24000000>; 176 clock-output-names = "clkref"; 177 }; 178 179 /* 180 * This is a fabulated representation of the input clock 181 * to NCO since we don't know the true clock tree. 182 */ 183 nco_clkref: clock-ref-nco { 184 compatible = "fixed-clock"; 185 #clock-cells = <0>; 186 clock-output-names = "nco_ref"; 187 }; 188}; 189