1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Apple T6002 "M1 Ultra" SoC
4 *
5 * Other names: H13J, "Jade 2C"
6 *
7 * Copyright The Asahi Linux Contributors
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/apple-aic.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/pinctrl/apple.h>
14
15#include "multi-die-cpp.h"
16
17#include "t600x-common.dtsi"
18
19/ {
20	compatible = "apple,t6002", "apple,arm-platform";
21
22	#address-cells = <2>;
23	#size-cells = <2>;
24
25	cpus {
26		cpu_e10: cpu@800 {
27			compatible = "apple,icestorm";
28			device_type = "cpu";
29			reg = <0x0 0x800>;
30			enable-method = "spin-table";
31			cpu-release-addr = <0 0>; /* To be filled by loader */
32			next-level-cache = <&l2_cache_3>;
33			i-cache-size = <0x20000>;
34			d-cache-size = <0x10000>;
35		};
36
37		cpu_e11: cpu@801 {
38			compatible = "apple,icestorm";
39			device_type = "cpu";
40			reg = <0x0 0x801>;
41			enable-method = "spin-table";
42			cpu-release-addr = <0 0>; /* To be filled by loader */
43			next-level-cache = <&l2_cache_3>;
44			i-cache-size = <0x20000>;
45			d-cache-size = <0x10000>;
46		};
47
48		cpu_p20: cpu@10900 {
49			compatible = "apple,firestorm";
50			device_type = "cpu";
51			reg = <0x0 0x10900>;
52			enable-method = "spin-table";
53			cpu-release-addr = <0 0>; /* To be filled by loader */
54			next-level-cache = <&l2_cache_4>;
55			i-cache-size = <0x30000>;
56			d-cache-size = <0x20000>;
57		};
58
59		cpu_p21: cpu@10901 {
60			compatible = "apple,firestorm";
61			device_type = "cpu";
62			reg = <0x0 0x10901>;
63			enable-method = "spin-table";
64			cpu-release-addr = <0 0>; /* To be filled by loader */
65			next-level-cache = <&l2_cache_4>;
66			i-cache-size = <0x30000>;
67			d-cache-size = <0x20000>;
68		};
69
70		cpu_p22: cpu@10902 {
71			compatible = "apple,firestorm";
72			device_type = "cpu";
73			reg = <0x0 0x10902>;
74			enable-method = "spin-table";
75			cpu-release-addr = <0 0>; /* To be filled by loader */
76			next-level-cache = <&l2_cache_4>;
77			i-cache-size = <0x30000>;
78			d-cache-size = <0x20000>;
79		};
80
81		cpu_p23: cpu@10903 {
82			compatible = "apple,firestorm";
83			device_type = "cpu";
84			reg = <0x0 0x10903>;
85			enable-method = "spin-table";
86			cpu-release-addr = <0 0>; /* To be filled by loader */
87			next-level-cache = <&l2_cache_4>;
88			i-cache-size = <0x30000>;
89			d-cache-size = <0x20000>;
90		};
91
92		cpu_p30: cpu@10a00 {
93			compatible = "apple,firestorm";
94			device_type = "cpu";
95			reg = <0x0 0x10a00>;
96			enable-method = "spin-table";
97			cpu-release-addr = <0 0>; /* To be filled by loader */
98			next-level-cache = <&l2_cache_5>;
99			i-cache-size = <0x30000>;
100			d-cache-size = <0x20000>;
101		};
102
103		cpu_p31: cpu@10a01 {
104			compatible = "apple,firestorm";
105			device_type = "cpu";
106			reg = <0x0 0x10a01>;
107			enable-method = "spin-table";
108			cpu-release-addr = <0 0>; /* To be filled by loader */
109			next-level-cache = <&l2_cache_5>;
110			i-cache-size = <0x30000>;
111			d-cache-size = <0x20000>;
112		};
113
114		cpu_p32: cpu@10a02 {
115			compatible = "apple,firestorm";
116			device_type = "cpu";
117			reg = <0x0 0x10a02>;
118			enable-method = "spin-table";
119			cpu-release-addr = <0 0>; /* To be filled by loader */
120			next-level-cache = <&l2_cache_5>;
121			i-cache-size = <0x30000>;
122			d-cache-size = <0x20000>;
123		};
124
125		cpu_p33: cpu@10a03 {
126			compatible = "apple,firestorm";
127			device_type = "cpu";
128			reg = <0x0 0x10a03>;
129			enable-method = "spin-table";
130			cpu-release-addr = <0 0>; /* To be filled by loader */
131			next-level-cache = <&l2_cache_5>;
132			i-cache-size = <0x30000>;
133			d-cache-size = <0x20000>;
134		};
135
136		l2_cache_3: l2-cache-3 {
137			compatible = "cache";
138			cache-level = <2>;
139			cache-unified;
140			cache-size = <0x400000>;
141		};
142
143		l2_cache_4: l2-cache-4 {
144			compatible = "cache";
145			cache-level = <2>;
146			cache-unified;
147			cache-size = <0xc00000>;
148		};
149
150		l2_cache_5: l2-cache-5 {
151			compatible = "cache";
152			cache-level = <2>;
153			cache-unified;
154			cache-size = <0xc00000>;
155		};
156	};
157
158	die0: soc@200000000 {
159		compatible = "simple-bus";
160		#address-cells = <2>;
161		#size-cells = <2>;
162		ranges = <0x2 0x0 0x2 0x0 0x4 0x0>,
163			 <0x5 0x80000000 0x5 0x80000000 0x1 0x80000000>,
164			 <0x7 0x0 0x7 0x0 0xf 0x80000000>;
165		nonposted-mmio;
166
167		// filled via templated includes at the end of the file
168	};
169
170	die1: soc@2200000000 {
171		compatible = "simple-bus";
172		#address-cells = <2>;
173		#size-cells = <2>;
174		ranges = <0x2 0x0 0x22 0x0 0x4 0x0>,
175			 <0x7 0x0 0x27 0x0 0xf 0x80000000>;
176		nonposted-mmio;
177
178		// filled via templated includes at the end of the file
179	};
180};
181
182#define DIE
183#define DIE_NO 0
184
185&die0 {
186	#include "t600x-die0.dtsi"
187	#include "t600x-dieX.dtsi"
188};
189
190#include "t600x-pmgr.dtsi"
191#include "t600x-gpio-pins.dtsi"
192
193#undef DIE
194#undef DIE_NO
195
196#define DIE _die1
197#define DIE_NO 1
198
199&die1 {
200	#include "t600x-dieX.dtsi"
201	#include "t600x-nvme.dtsi"
202};
203
204#include "t600x-pmgr.dtsi"
205
206#undef DIE
207#undef DIE_NO
208
209
210&aic {
211	affinities {
212		e-core-pmu-affinity {
213			apple,fiq-index = <AIC_CPU_PMU_E>;
214			cpus = <&cpu_e00 &cpu_e01
215				&cpu_e10 &cpu_e11>;
216		};
217
218		p-core-pmu-affinity {
219			apple,fiq-index = <AIC_CPU_PMU_P>;
220			cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03
221				&cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13
222				&cpu_p20 &cpu_p21 &cpu_p22 &cpu_p23
223				&cpu_p30 &cpu_p31 &cpu_p32 &cpu_p33>;
224		};
225	};
226};
227