1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 */
6
7/dts-v1/;
8
9#include "meson-sm1.dtsi"
10#include "meson-khadas-vim3.dtsi"
11#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
12
13/ {
14	compatible = "khadas,vim3l", "amlogic,sm1";
15	model = "Khadas VIM3L";
16
17	vddcpu: regulator-vddcpu {
18		/*
19		 * Silergy SY8030DEC Regulator.
20		 */
21		compatible = "pwm-regulator";
22
23		regulator-name = "VDDCPU";
24		regulator-min-microvolt = <690000>;
25		regulator-max-microvolt = <1050000>;
26
27		vin-supply = <&vsys_3v3>;
28
29		pwms = <&pwm_AO_cd 1 1250 0>;
30		pwm-dutycycle-range = <100 0>;
31
32		regulator-boot-on;
33		regulator-always-on;
34	};
35
36	sound {
37		compatible = "amlogic,axg-sound-card";
38		model = "SM1-KHADAS-VIM3L";
39		audio-aux-devs = <&tdmout_a>;
40		audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
41				"TDMOUT_A IN 1", "FRDDR_B OUT 0",
42				"TDMOUT_A IN 2", "FRDDR_C OUT 0",
43				"TDM_A Playback", "TDMOUT_A OUT";
44
45		assigned-clocks = <&clkc CLKID_MPLL2>,
46				  <&clkc CLKID_MPLL0>,
47				  <&clkc CLKID_MPLL1>;
48		assigned-clock-parents = <0>, <0>, <0>;
49		assigned-clock-rates = <294912000>,
50				       <270950400>,
51				       <393216000>;
52		status = "okay";
53
54		dai-link-0 {
55			sound-dai = <&frddr_a>;
56		};
57
58		dai-link-1 {
59			sound-dai = <&frddr_b>;
60		};
61
62		dai-link-2 {
63			sound-dai = <&frddr_c>;
64		};
65
66		/* 8ch hdmi interface */
67		dai-link-3 {
68			sound-dai = <&tdmif_a>;
69			dai-format = "i2s";
70			dai-tdm-slot-tx-mask-0 = <1 1>;
71			dai-tdm-slot-tx-mask-1 = <1 1>;
72			dai-tdm-slot-tx-mask-2 = <1 1>;
73			dai-tdm-slot-tx-mask-3 = <1 1>;
74			mclk-fs = <256>;
75
76			codec {
77				sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
78			};
79		};
80
81		/* hdmi glue */
82		dai-link-4 {
83			sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
84
85			codec {
86				sound-dai = <&hdmi_tx>;
87			};
88		};
89	};
90};
91
92&arb {
93	status = "okay";
94};
95
96&clkc_audio {
97	status = "okay";
98};
99
100&cpu0 {
101	cpu-supply = <&vddcpu>;
102	operating-points-v2 = <&cpu_opp_table>;
103	clocks = <&clkc CLKID_CPU_CLK>;
104	clock-latency = <50000>;
105};
106
107&cpu1 {
108	cpu-supply = <&vddcpu>;
109	operating-points-v2 = <&cpu_opp_table>;
110	clocks = <&clkc CLKID_CPU1_CLK>;
111	clock-latency = <50000>;
112};
113
114&cpu2 {
115	cpu-supply = <&vddcpu>;
116	operating-points-v2 = <&cpu_opp_table>;
117	clocks = <&clkc CLKID_CPU2_CLK>;
118	clock-latency = <50000>;
119};
120
121&cpu3 {
122	cpu-supply = <&vddcpu>;
123	operating-points-v2 = <&cpu_opp_table>;
124	clocks = <&clkc CLKID_CPU3_CLK>;
125	clock-latency = <50000>;
126};
127
128&frddr_a {
129	status = "okay";
130};
131
132&frddr_b {
133	status = "okay";
134};
135
136&frddr_c {
137	status = "okay";
138};
139
140&pwm_AO_cd {
141	pinctrl-0 = <&pwm_ao_d_e_pins>;
142	pinctrl-names = "default";
143	clocks = <&xtal>;
144	clock-names = "clkin1";
145	status = "okay";
146};
147
148/*
149 * The VIM3 on-board  MCU can mux the PCIe/USB3.0 shared differential
150 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
151 * an USB3.0 Type A connector and a M.2 Key M slot.
152 * The PHY driving these differential lines is shared between
153 * the USB3.0 controller and the PCIe Controller, thus only
154 * a single controller can use it.
155 * If the MCU is configured to mux the PCIe/USB3.0 differential lines
156 * to the M.2 Key M slot, uncomment the following block to disable
157 * USB3.0 from the USB Complex and enable the PCIe controller.
158 * The End User is not expected to uncomment the following except for
159 * testing purposes, but instead rely on the firmware/bootloader to
160 * update these nodes accordingly if PCIe mode is selected by the MCU.
161 */
162/*
163&pcie {
164	status = "okay";
165};
166
167&sd_emmc_a {
168	sd-uhs-sdr50;
169};
170
171&usb {
172	phys = <&usb2_phy0>, <&usb2_phy1>;
173	phy-names = "usb2-phy0", "usb2-phy1";
174};
175 */
176
177&tdmif_a {
178	status = "okay";
179};
180
181&tdmout_a {
182	status = "okay";
183};
184
185&tohdmitx {
186	status = "okay";
187};
188