1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 */
6
7/dts-v1/;
8
9#include "meson-sm1.dtsi"
10#include "meson-khadas-vim3.dtsi"
11
12/ {
13	compatible = "khadas,vim3l", "amlogic,sm1";
14	model = "Khadas VIM3L";
15
16	vddcpu: regulator-vddcpu {
17		/*
18		 * Silergy SY8030DEC Regulator.
19		 */
20		compatible = "pwm-regulator";
21
22		regulator-name = "VDDCPU";
23		regulator-min-microvolt = <690000>;
24		regulator-max-microvolt = <1050000>;
25
26		vin-supply = <&vsys_3v3>;
27
28		pwms = <&pwm_AO_cd 1 1250 0>;
29		pwm-dutycycle-range = <100 0>;
30
31		regulator-boot-on;
32		regulator-always-on;
33	};
34};
35
36&cpu0 {
37	cpu-supply = <&vddcpu>;
38	operating-points-v2 = <&cpu_opp_table>;
39	clocks = <&clkc CLKID_CPU_CLK>;
40	clock-latency = <50000>;
41};
42
43&cpu1 {
44	cpu-supply = <&vddcpu>;
45	operating-points-v2 = <&cpu_opp_table>;
46	clocks = <&clkc CLKID_CPU1_CLK>;
47	clock-latency = <50000>;
48};
49
50&cpu2 {
51	cpu-supply = <&vddcpu>;
52	operating-points-v2 = <&cpu_opp_table>;
53	clocks = <&clkc CLKID_CPU2_CLK>;
54	clock-latency = <50000>;
55};
56
57&cpu3 {
58	cpu-supply = <&vddcpu>;
59	operating-points-v2 = <&cpu_opp_table>;
60	clocks = <&clkc CLKID_CPU3_CLK>;
61	clock-latency = <50000>;
62};
63
64&pwm_AO_cd {
65	pinctrl-0 = <&pwm_ao_d_e_pins>;
66	pinctrl-names = "default";
67	clocks = <&xtal>;
68	clock-names = "clkin1";
69	status = "okay";
70};
71
72/*
73 * The VIM3 on-board  MCU can mux the PCIe/USB3.0 shared differential
74 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
75 * an USB3.0 Type A connector and a M.2 Key M slot.
76 * The PHY driving these differential lines is shared between
77 * the USB3.0 controller and the PCIe Controller, thus only
78 * a single controller can use it.
79 * If the MCU is configured to mux the PCIe/USB3.0 differential lines
80 * to the M.2 Key M slot, uncomment the following block to disable
81 * USB3.0 from the USB Complex and enable the PCIe controller.
82 * The End User is not expected to uncomment the following except for
83 * testing purposes, but instead rely on the firmware/bootloader to
84 * update these nodes accordingly if PCIe mode is selected by the MCU.
85 */
86/*
87&pcie {
88	status = "okay";
89};
90
91&usb {
92	phys = <&usb2_phy0>, <&usb2_phy1>;
93	phy-names = "usb2-phy0", "usb2-phy1";
94};
95 */
96