1700ab8d8SNeil Armstrong// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2700ab8d8SNeil Armstrong/* 3700ab8d8SNeil Armstrong * Copyright (c) 2019 BayLibre, SAS 4700ab8d8SNeil Armstrong * Author: Neil Armstrong <narmstrong@baylibre.com> 5700ab8d8SNeil Armstrong */ 6700ab8d8SNeil Armstrong 7700ab8d8SNeil Armstrong/dts-v1/; 8700ab8d8SNeil Armstrong 9700ab8d8SNeil Armstrong#include "meson-sm1.dtsi" 10700ab8d8SNeil Armstrong#include "meson-khadas-vim3.dtsi" 11700ab8d8SNeil Armstrong 12700ab8d8SNeil Armstrong/ { 13700ab8d8SNeil Armstrong compatible = "khadas,vim3l", "amlogic,sm1"; 14700ab8d8SNeil Armstrong model = "Khadas VIM3L"; 15700ab8d8SNeil Armstrong 16700ab8d8SNeil Armstrong vddcpu: regulator-vddcpu { 17700ab8d8SNeil Armstrong /* 18700ab8d8SNeil Armstrong * Silergy SY8030DEC Regulator. 19700ab8d8SNeil Armstrong */ 20700ab8d8SNeil Armstrong compatible = "pwm-regulator"; 21700ab8d8SNeil Armstrong 22700ab8d8SNeil Armstrong regulator-name = "VDDCPU"; 23700ab8d8SNeil Armstrong regulator-min-microvolt = <690000>; 24700ab8d8SNeil Armstrong regulator-max-microvolt = <1050000>; 25700ab8d8SNeil Armstrong 26700ab8d8SNeil Armstrong vin-supply = <&vsys_3v3>; 27700ab8d8SNeil Armstrong 28700ab8d8SNeil Armstrong pwms = <&pwm_AO_cd 1 1250 0>; 29700ab8d8SNeil Armstrong pwm-dutycycle-range = <100 0>; 30700ab8d8SNeil Armstrong 31700ab8d8SNeil Armstrong regulator-boot-on; 32700ab8d8SNeil Armstrong regulator-always-on; 33700ab8d8SNeil Armstrong }; 34700ab8d8SNeil Armstrong}; 35700ab8d8SNeil Armstrong 36700ab8d8SNeil Armstrong&cpu0 { 37700ab8d8SNeil Armstrong cpu-supply = <&vddcpu>; 38700ab8d8SNeil Armstrong operating-points-v2 = <&cpu_opp_table>; 39700ab8d8SNeil Armstrong clocks = <&clkc CLKID_CPU_CLK>; 40700ab8d8SNeil Armstrong clock-latency = <50000>; 41700ab8d8SNeil Armstrong}; 42700ab8d8SNeil Armstrong 43700ab8d8SNeil Armstrong&cpu1 { 44700ab8d8SNeil Armstrong cpu-supply = <&vddcpu>; 45700ab8d8SNeil Armstrong operating-points-v2 = <&cpu_opp_table>; 46700ab8d8SNeil Armstrong clocks = <&clkc CLKID_CPU1_CLK>; 47700ab8d8SNeil Armstrong clock-latency = <50000>; 48700ab8d8SNeil Armstrong}; 49700ab8d8SNeil Armstrong 50700ab8d8SNeil Armstrong&cpu2 { 51700ab8d8SNeil Armstrong cpu-supply = <&vddcpu>; 52700ab8d8SNeil Armstrong operating-points-v2 = <&cpu_opp_table>; 53700ab8d8SNeil Armstrong clocks = <&clkc CLKID_CPU2_CLK>; 54700ab8d8SNeil Armstrong clock-latency = <50000>; 55700ab8d8SNeil Armstrong}; 56700ab8d8SNeil Armstrong 57700ab8d8SNeil Armstrong&cpu3 { 58700ab8d8SNeil Armstrong cpu-supply = <&vddcpu>; 59700ab8d8SNeil Armstrong operating-points-v2 = <&cpu_opp_table>; 60700ab8d8SNeil Armstrong clocks = <&clkc CLKID_CPU3_CLK>; 61700ab8d8SNeil Armstrong clock-latency = <50000>; 62700ab8d8SNeil Armstrong}; 63700ab8d8SNeil Armstrong 64700ab8d8SNeil Armstrong&pwm_AO_cd { 65700ab8d8SNeil Armstrong pinctrl-0 = <&pwm_ao_d_e_pins>; 66700ab8d8SNeil Armstrong pinctrl-names = "default"; 67700ab8d8SNeil Armstrong clocks = <&xtal>; 68700ab8d8SNeil Armstrong clock-names = "clkin1"; 69700ab8d8SNeil Armstrong status = "okay"; 70700ab8d8SNeil Armstrong}; 71