1700ab8d8SNeil Armstrong// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2700ab8d8SNeil Armstrong/* 3700ab8d8SNeil Armstrong * Copyright (c) 2019 BayLibre, SAS 4700ab8d8SNeil Armstrong * Author: Neil Armstrong <narmstrong@baylibre.com> 5700ab8d8SNeil Armstrong */ 6700ab8d8SNeil Armstrong 7700ab8d8SNeil Armstrong/dts-v1/; 8700ab8d8SNeil Armstrong 9700ab8d8SNeil Armstrong#include "meson-sm1.dtsi" 10700ab8d8SNeil Armstrong#include "meson-khadas-vim3.dtsi" 11b8b85d01SChristian Hewitt#include <dt-bindings/sound/meson-g12a-tohdmitx.h> 12700ab8d8SNeil Armstrong 13700ab8d8SNeil Armstrong/ { 14700ab8d8SNeil Armstrong compatible = "khadas,vim3l", "amlogic,sm1"; 15700ab8d8SNeil Armstrong model = "Khadas VIM3L"; 16700ab8d8SNeil Armstrong 17700ab8d8SNeil Armstrong vddcpu: regulator-vddcpu { 18700ab8d8SNeil Armstrong /* 19700ab8d8SNeil Armstrong * Silergy SY8030DEC Regulator. 20700ab8d8SNeil Armstrong */ 21700ab8d8SNeil Armstrong compatible = "pwm-regulator"; 22700ab8d8SNeil Armstrong 23700ab8d8SNeil Armstrong regulator-name = "VDDCPU"; 24700ab8d8SNeil Armstrong regulator-min-microvolt = <690000>; 25700ab8d8SNeil Armstrong regulator-max-microvolt = <1050000>; 26700ab8d8SNeil Armstrong 27700ab8d8SNeil Armstrong vin-supply = <&vsys_3v3>; 28700ab8d8SNeil Armstrong 29700ab8d8SNeil Armstrong pwms = <&pwm_AO_cd 1 1250 0>; 30700ab8d8SNeil Armstrong pwm-dutycycle-range = <100 0>; 31700ab8d8SNeil Armstrong 32700ab8d8SNeil Armstrong regulator-boot-on; 33700ab8d8SNeil Armstrong regulator-always-on; 34700ab8d8SNeil Armstrong }; 35700ab8d8SNeil Armstrong}; 36700ab8d8SNeil Armstrong 37700ab8d8SNeil Armstrong&cpu0 { 38700ab8d8SNeil Armstrong cpu-supply = <&vddcpu>; 39700ab8d8SNeil Armstrong operating-points-v2 = <&cpu_opp_table>; 40700ab8d8SNeil Armstrong clocks = <&clkc CLKID_CPU_CLK>; 41700ab8d8SNeil Armstrong clock-latency = <50000>; 42700ab8d8SNeil Armstrong}; 43700ab8d8SNeil Armstrong 44700ab8d8SNeil Armstrong&cpu1 { 45700ab8d8SNeil Armstrong cpu-supply = <&vddcpu>; 46700ab8d8SNeil Armstrong operating-points-v2 = <&cpu_opp_table>; 47700ab8d8SNeil Armstrong clocks = <&clkc CLKID_CPU1_CLK>; 48700ab8d8SNeil Armstrong clock-latency = <50000>; 49700ab8d8SNeil Armstrong}; 50700ab8d8SNeil Armstrong 51700ab8d8SNeil Armstrong&cpu2 { 52700ab8d8SNeil Armstrong cpu-supply = <&vddcpu>; 53700ab8d8SNeil Armstrong operating-points-v2 = <&cpu_opp_table>; 54700ab8d8SNeil Armstrong clocks = <&clkc CLKID_CPU2_CLK>; 55700ab8d8SNeil Armstrong clock-latency = <50000>; 56700ab8d8SNeil Armstrong}; 57700ab8d8SNeil Armstrong 58700ab8d8SNeil Armstrong&cpu3 { 59700ab8d8SNeil Armstrong cpu-supply = <&vddcpu>; 60700ab8d8SNeil Armstrong operating-points-v2 = <&cpu_opp_table>; 61700ab8d8SNeil Armstrong clocks = <&clkc CLKID_CPU3_CLK>; 62700ab8d8SNeil Armstrong clock-latency = <50000>; 63700ab8d8SNeil Armstrong}; 64700ab8d8SNeil Armstrong 65700ab8d8SNeil Armstrong&pwm_AO_cd { 66700ab8d8SNeil Armstrong pinctrl-0 = <&pwm_ao_d_e_pins>; 67700ab8d8SNeil Armstrong pinctrl-names = "default"; 68700ab8d8SNeil Armstrong clocks = <&xtal>; 69700ab8d8SNeil Armstrong clock-names = "clkin1"; 70700ab8d8SNeil Armstrong status = "okay"; 71700ab8d8SNeil Armstrong}; 72ba1f8af7SNeil Armstrong 73ba1f8af7SNeil Armstrong/* 74ba1f8af7SNeil Armstrong * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential 75ba1f8af7SNeil Armstrong * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between 76ba1f8af7SNeil Armstrong * an USB3.0 Type A connector and a M.2 Key M slot. 77ba1f8af7SNeil Armstrong * The PHY driving these differential lines is shared between 78ba1f8af7SNeil Armstrong * the USB3.0 controller and the PCIe Controller, thus only 79ba1f8af7SNeil Armstrong * a single controller can use it. 80ba1f8af7SNeil Armstrong * If the MCU is configured to mux the PCIe/USB3.0 differential lines 81ba1f8af7SNeil Armstrong * to the M.2 Key M slot, uncomment the following block to disable 82ba1f8af7SNeil Armstrong * USB3.0 from the USB Complex and enable the PCIe controller. 83ba1f8af7SNeil Armstrong * The End User is not expected to uncomment the following except for 84ba1f8af7SNeil Armstrong * testing purposes, but instead rely on the firmware/bootloader to 85ba1f8af7SNeil Armstrong * update these nodes accordingly if PCIe mode is selected by the MCU. 86ba1f8af7SNeil Armstrong */ 87ba1f8af7SNeil Armstrong/* 88ba1f8af7SNeil Armstrong&pcie { 89ba1f8af7SNeil Armstrong status = "okay"; 90ba1f8af7SNeil Armstrong}; 91ba1f8af7SNeil Armstrong 92ba1f8af7SNeil Armstrong&usb { 93ba1f8af7SNeil Armstrong phys = <&usb2_phy0>, <&usb2_phy1>; 94ba1f8af7SNeil Armstrong phy-names = "usb2-phy0", "usb2-phy1"; 95ba1f8af7SNeil Armstrong}; 96ba1f8af7SNeil Armstrong */ 97b8b85d01SChristian Hewitt 98*39be8f44SArtem Lapkin&sd_emmc_a { 99*39be8f44SArtem Lapkin sd-uhs-sdr50; 100*39be8f44SArtem Lapkin}; 101