1700ab8d8SNeil Armstrong// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2700ab8d8SNeil Armstrong/* 3700ab8d8SNeil Armstrong * Copyright (c) 2019 BayLibre, SAS 4700ab8d8SNeil Armstrong * Author: Neil Armstrong <narmstrong@baylibre.com> 5700ab8d8SNeil Armstrong */ 6700ab8d8SNeil Armstrong 7700ab8d8SNeil Armstrong/dts-v1/; 8700ab8d8SNeil Armstrong 9700ab8d8SNeil Armstrong#include "meson-sm1.dtsi" 10700ab8d8SNeil Armstrong#include "meson-khadas-vim3.dtsi" 11b8b85d01SChristian Hewitt#include <dt-bindings/sound/meson-g12a-tohdmitx.h> 12700ab8d8SNeil Armstrong 13700ab8d8SNeil Armstrong/ { 14700ab8d8SNeil Armstrong compatible = "khadas,vim3l", "amlogic,sm1"; 15700ab8d8SNeil Armstrong model = "Khadas VIM3L"; 16700ab8d8SNeil Armstrong 17700ab8d8SNeil Armstrong vddcpu: regulator-vddcpu { 18700ab8d8SNeil Armstrong /* 19700ab8d8SNeil Armstrong * Silergy SY8030DEC Regulator. 20700ab8d8SNeil Armstrong */ 21700ab8d8SNeil Armstrong compatible = "pwm-regulator"; 22700ab8d8SNeil Armstrong 23700ab8d8SNeil Armstrong regulator-name = "VDDCPU"; 24700ab8d8SNeil Armstrong regulator-min-microvolt = <690000>; 25700ab8d8SNeil Armstrong regulator-max-microvolt = <1050000>; 26700ab8d8SNeil Armstrong 27*876ba79cSAnand Moon pwm-supply = <&vsys_3v3>; 28700ab8d8SNeil Armstrong 29700ab8d8SNeil Armstrong pwms = <&pwm_AO_cd 1 1250 0>; 30700ab8d8SNeil Armstrong pwm-dutycycle-range = <100 0>; 31700ab8d8SNeil Armstrong 32700ab8d8SNeil Armstrong regulator-boot-on; 33700ab8d8SNeil Armstrong regulator-always-on; 34700ab8d8SNeil Armstrong }; 3543ffb528SJerome Brunet 3643ffb528SJerome Brunet sound { 3743ffb528SJerome Brunet model = "G12B-KHADAS-VIM3L"; 3843ffb528SJerome Brunet audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", 3943ffb528SJerome Brunet "TDMOUT_A IN 1", "FRDDR_B OUT 0", 4043ffb528SJerome Brunet "TDMOUT_A IN 2", "FRDDR_C OUT 0", 4143ffb528SJerome Brunet "TDM_A Playback", "TDMOUT_A OUT", 4243ffb528SJerome Brunet "TDMIN_A IN 0", "TDM_A Capture", 4343ffb528SJerome Brunet "TDMIN_A IN 13", "TDM_A Loopback", 4443ffb528SJerome Brunet "TODDR_A IN 0", "TDMIN_A OUT", 4543ffb528SJerome Brunet "TODDR_B IN 0", "TDMIN_A OUT", 4643ffb528SJerome Brunet "TODDR_C IN 0", "TDMIN_A OUT"; 4743ffb528SJerome Brunet }; 48700ab8d8SNeil Armstrong}; 49700ab8d8SNeil Armstrong 50700ab8d8SNeil Armstrong&cpu0 { 51700ab8d8SNeil Armstrong cpu-supply = <&vddcpu>; 52700ab8d8SNeil Armstrong operating-points-v2 = <&cpu_opp_table>; 53700ab8d8SNeil Armstrong clocks = <&clkc CLKID_CPU_CLK>; 54700ab8d8SNeil Armstrong clock-latency = <50000>; 55700ab8d8SNeil Armstrong}; 56700ab8d8SNeil Armstrong 57700ab8d8SNeil Armstrong&cpu1 { 58700ab8d8SNeil Armstrong cpu-supply = <&vddcpu>; 59700ab8d8SNeil Armstrong operating-points-v2 = <&cpu_opp_table>; 60700ab8d8SNeil Armstrong clocks = <&clkc CLKID_CPU1_CLK>; 61700ab8d8SNeil Armstrong clock-latency = <50000>; 62700ab8d8SNeil Armstrong}; 63700ab8d8SNeil Armstrong 64700ab8d8SNeil Armstrong&cpu2 { 65700ab8d8SNeil Armstrong cpu-supply = <&vddcpu>; 66700ab8d8SNeil Armstrong operating-points-v2 = <&cpu_opp_table>; 67700ab8d8SNeil Armstrong clocks = <&clkc CLKID_CPU2_CLK>; 68700ab8d8SNeil Armstrong clock-latency = <50000>; 69700ab8d8SNeil Armstrong}; 70700ab8d8SNeil Armstrong 71700ab8d8SNeil Armstrong&cpu3 { 72700ab8d8SNeil Armstrong cpu-supply = <&vddcpu>; 73700ab8d8SNeil Armstrong operating-points-v2 = <&cpu_opp_table>; 74700ab8d8SNeil Armstrong clocks = <&clkc CLKID_CPU3_CLK>; 75700ab8d8SNeil Armstrong clock-latency = <50000>; 76700ab8d8SNeil Armstrong}; 77700ab8d8SNeil Armstrong 78700ab8d8SNeil Armstrong&pwm_AO_cd { 79700ab8d8SNeil Armstrong pinctrl-0 = <&pwm_ao_d_e_pins>; 80700ab8d8SNeil Armstrong pinctrl-names = "default"; 81700ab8d8SNeil Armstrong clocks = <&xtal>; 82700ab8d8SNeil Armstrong clock-names = "clkin1"; 83700ab8d8SNeil Armstrong status = "okay"; 84700ab8d8SNeil Armstrong}; 85ba1f8af7SNeil Armstrong 86ba1f8af7SNeil Armstrong/* 87ba1f8af7SNeil Armstrong * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential 88ba1f8af7SNeil Armstrong * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between 89ba1f8af7SNeil Armstrong * an USB3.0 Type A connector and a M.2 Key M slot. 90ba1f8af7SNeil Armstrong * The PHY driving these differential lines is shared between 91ba1f8af7SNeil Armstrong * the USB3.0 controller and the PCIe Controller, thus only 92ba1f8af7SNeil Armstrong * a single controller can use it. 93ba1f8af7SNeil Armstrong * If the MCU is configured to mux the PCIe/USB3.0 differential lines 94ba1f8af7SNeil Armstrong * to the M.2 Key M slot, uncomment the following block to disable 95ba1f8af7SNeil Armstrong * USB3.0 from the USB Complex and enable the PCIe controller. 96ba1f8af7SNeil Armstrong * The End User is not expected to uncomment the following except for 97ba1f8af7SNeil Armstrong * testing purposes, but instead rely on the firmware/bootloader to 98ba1f8af7SNeil Armstrong * update these nodes accordingly if PCIe mode is selected by the MCU. 99ba1f8af7SNeil Armstrong */ 100ba1f8af7SNeil Armstrong/* 101ba1f8af7SNeil Armstrong&pcie { 102ba1f8af7SNeil Armstrong status = "okay"; 103ba1f8af7SNeil Armstrong}; 104ba1f8af7SNeil Armstrong 105ba1f8af7SNeil Armstrong&usb { 106ba1f8af7SNeil Armstrong phys = <&usb2_phy0>, <&usb2_phy1>; 107ba1f8af7SNeil Armstrong phy-names = "usb2-phy0", "usb2-phy1"; 108ba1f8af7SNeil Armstrong}; 109ba1f8af7SNeil Armstrong */ 110b8b85d01SChristian Hewitt 11139be8f44SArtem Lapkin&sd_emmc_a { 11239be8f44SArtem Lapkin sd-uhs-sdr50; 11339be8f44SArtem Lapkin}; 114