1*8b749a02SChristian Hewitt// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*8b749a02SChristian Hewitt/* 3*8b749a02SChristian Hewitt * Copyright (c) 2019 BayLibre SAS. All rights reserved. 4*8b749a02SChristian Hewitt * Copyright (c) 2020 Christian Hewitt <christianshewitt@gmail.com> 5*8b749a02SChristian Hewitt */ 6*8b749a02SChristian Hewitt 7*8b749a02SChristian Hewitt/dts-v1/; 8*8b749a02SChristian Hewitt 9*8b749a02SChristian Hewitt#include "meson-sm1-ac2xx.dtsi" 10*8b749a02SChristian Hewitt#include <dt-bindings/sound/meson-g12a-tohdmitx.h> 11*8b749a02SChristian Hewitt 12*8b749a02SChristian Hewitt/ { 13*8b749a02SChristian Hewitt compatible = "cyx,a95xf3-air-gbit", "amlogic,sm1"; 14*8b749a02SChristian Hewitt model = "Shenzhen CYX Industrial Co., Ltd A95XF3-AIR"; 15*8b749a02SChristian Hewitt 16*8b749a02SChristian Hewitt sound { 17*8b749a02SChristian Hewitt compatible = "amlogic,axg-sound-card"; 18*8b749a02SChristian Hewitt model = "A95XF3-AIR"; 19*8b749a02SChristian Hewitt audio-aux-devs = <&tdmout_b>; 20*8b749a02SChristian Hewitt audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", 21*8b749a02SChristian Hewitt "TDMOUT_B IN 1", "FRDDR_B OUT 1", 22*8b749a02SChristian Hewitt "TDMOUT_B IN 2", "FRDDR_C OUT 1", 23*8b749a02SChristian Hewitt "TDM_B Playback", "TDMOUT_B OUT"; 24*8b749a02SChristian Hewitt 25*8b749a02SChristian Hewitt assigned-clocks = <&clkc CLKID_MPLL2>, 26*8b749a02SChristian Hewitt <&clkc CLKID_MPLL0>, 27*8b749a02SChristian Hewitt <&clkc CLKID_MPLL1>; 28*8b749a02SChristian Hewitt assigned-clock-parents = <0>, <0>, <0>; 29*8b749a02SChristian Hewitt assigned-clock-rates = <294912000>, 30*8b749a02SChristian Hewitt <270950400>, 31*8b749a02SChristian Hewitt <393216000>; 32*8b749a02SChristian Hewitt status = "okay"; 33*8b749a02SChristian Hewitt 34*8b749a02SChristian Hewitt dai-link-0 { 35*8b749a02SChristian Hewitt sound-dai = <&frddr_a>; 36*8b749a02SChristian Hewitt }; 37*8b749a02SChristian Hewitt 38*8b749a02SChristian Hewitt dai-link-1 { 39*8b749a02SChristian Hewitt sound-dai = <&frddr_b>; 40*8b749a02SChristian Hewitt }; 41*8b749a02SChristian Hewitt 42*8b749a02SChristian Hewitt dai-link-2 { 43*8b749a02SChristian Hewitt sound-dai = <&frddr_c>; 44*8b749a02SChristian Hewitt }; 45*8b749a02SChristian Hewitt 46*8b749a02SChristian Hewitt /* 8ch hdmi interface */ 47*8b749a02SChristian Hewitt dai-link-3 { 48*8b749a02SChristian Hewitt sound-dai = <&tdmif_b>; 49*8b749a02SChristian Hewitt dai-format = "i2s"; 50*8b749a02SChristian Hewitt dai-tdm-slot-tx-mask-0 = <1 1>; 51*8b749a02SChristian Hewitt dai-tdm-slot-tx-mask-1 = <1 1>; 52*8b749a02SChristian Hewitt dai-tdm-slot-tx-mask-2 = <1 1>; 53*8b749a02SChristian Hewitt dai-tdm-slot-tx-mask-3 = <1 1>; 54*8b749a02SChristian Hewitt mclk-fs = <256>; 55*8b749a02SChristian Hewitt 56*8b749a02SChristian Hewitt codec { 57*8b749a02SChristian Hewitt sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; 58*8b749a02SChristian Hewitt }; 59*8b749a02SChristian Hewitt }; 60*8b749a02SChristian Hewitt 61*8b749a02SChristian Hewitt /* hdmi glue */ 62*8b749a02SChristian Hewitt dai-link-4 { 63*8b749a02SChristian Hewitt sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; 64*8b749a02SChristian Hewitt 65*8b749a02SChristian Hewitt codec { 66*8b749a02SChristian Hewitt sound-dai = <&hdmi_tx>; 67*8b749a02SChristian Hewitt }; 68*8b749a02SChristian Hewitt }; 69*8b749a02SChristian Hewitt }; 70*8b749a02SChristian Hewitt}; 71*8b749a02SChristian Hewitt 72*8b749a02SChristian Hewitt&arb { 73*8b749a02SChristian Hewitt status = "okay"; 74*8b749a02SChristian Hewitt}; 75*8b749a02SChristian Hewitt 76*8b749a02SChristian Hewitt&clkc_audio { 77*8b749a02SChristian Hewitt status = "okay"; 78*8b749a02SChristian Hewitt}; 79*8b749a02SChristian Hewitt 80*8b749a02SChristian Hewittðmac { 81*8b749a02SChristian Hewitt status = "okay"; 82*8b749a02SChristian Hewitt 83*8b749a02SChristian Hewitt pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; 84*8b749a02SChristian Hewitt pinctrl-names = "default"; 85*8b749a02SChristian Hewitt phy-mode = "rgmii-txid"; 86*8b749a02SChristian Hewitt phy-handle = <&external_phy>; 87*8b749a02SChristian Hewitt 88*8b749a02SChristian Hewitt rx-internal-delay-ps = <800>; 89*8b749a02SChristian Hewitt}; 90*8b749a02SChristian Hewitt 91*8b749a02SChristian Hewitt&ext_mdio { 92*8b749a02SChristian Hewitt external_phy: ethernet-phy@0 { 93*8b749a02SChristian Hewitt /* Realtek RTL8211F (0x001cc916) */ 94*8b749a02SChristian Hewitt reg = <0>; 95*8b749a02SChristian Hewitt max-speed = <1000>; 96*8b749a02SChristian Hewitt 97*8b749a02SChristian Hewitt reset-assert-us = <10000>; 98*8b749a02SChristian Hewitt reset-deassert-us = <80000>; 99*8b749a02SChristian Hewitt reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; 100*8b749a02SChristian Hewitt 101*8b749a02SChristian Hewitt interrupt-parent = <&gpio_intc>; 102*8b749a02SChristian Hewitt /* MAC_INTR on GPIOZ_14 */ 103*8b749a02SChristian Hewitt interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 104*8b749a02SChristian Hewitt }; 105*8b749a02SChristian Hewitt}; 106*8b749a02SChristian Hewitt 107*8b749a02SChristian Hewitt&frddr_a { 108*8b749a02SChristian Hewitt status = "okay"; 109*8b749a02SChristian Hewitt}; 110*8b749a02SChristian Hewitt 111*8b749a02SChristian Hewitt&frddr_b { 112*8b749a02SChristian Hewitt status = "okay"; 113*8b749a02SChristian Hewitt}; 114*8b749a02SChristian Hewitt 115*8b749a02SChristian Hewitt&frddr_c { 116*8b749a02SChristian Hewitt status = "okay"; 117*8b749a02SChristian Hewitt}; 118*8b749a02SChristian Hewitt 119*8b749a02SChristian Hewitt&tdmif_b { 120*8b749a02SChristian Hewitt status = "okay"; 121*8b749a02SChristian Hewitt}; 122*8b749a02SChristian Hewitt 123*8b749a02SChristian Hewitt&tdmout_b { 124*8b749a02SChristian Hewitt status = "okay"; 125*8b749a02SChristian Hewitt}; 126*8b749a02SChristian Hewitt 127*8b749a02SChristian Hewitt&tohdmitx { 128*8b749a02SChristian Hewitt status = "okay"; 129*8b749a02SChristian Hewitt}; 130