1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11	cpus {
12		#address-cells = <2>;
13		#size-cells = <0>;
14
15		cpu0: cpu@0 {
16			device_type = "cpu";
17			compatible = "arm,cortex-a35";
18			reg = <0x0 0x0>;
19			enable-method = "psci";
20		};
21
22		cpu1: cpu@1 {
23			device_type = "cpu";
24			compatible = "arm,cortex-a35";
25			reg = <0x0 0x1>;
26			enable-method = "psci";
27		};
28
29		cpu2: cpu@2 {
30			device_type = "cpu";
31			compatible = "arm,cortex-a35";
32			reg = <0x0 0x2>;
33			enable-method = "psci";
34		};
35
36		cpu3: cpu@3 {
37			device_type = "cpu";
38			compatible = "arm,cortex-a35";
39			reg = <0x0 0x3>;
40			enable-method = "psci";
41		};
42	};
43
44	timer {
45		compatible = "arm,armv8-timer";
46		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
47			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
48			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
49			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
50	};
51
52	psci {
53		compatible = "arm,psci-1.0";
54		method = "smc";
55	};
56
57	xtal: xtal-clk {
58		compatible = "fixed-clock";
59		clock-frequency = <24000000>;
60		clock-output-names = "xtal";
61		#clock-cells = <0>;
62	};
63
64	firmware {
65		sm: secure-monitor {
66			compatible = "amlogic,meson-gxbb-sm";
67
68			pwrc: power-controller {
69				compatible = "amlogic,meson-s4-pwrc";
70				#power-domain-cells = <1>;
71			};
72		};
73	};
74
75	soc {
76		compatible = "simple-bus";
77		#address-cells = <2>;
78		#size-cells = <2>;
79		ranges;
80
81		gic: interrupt-controller@fff01000 {
82			compatible = "arm,gic-400";
83			#interrupt-cells = <3>;
84			#address-cells = <0>;
85			interrupt-controller;
86			reg = <0x0 0xfff01000 0 0x1000>,
87			      <0x0 0xfff02000 0 0x2000>,
88			      <0x0 0xfff04000 0 0x2000>,
89			      <0x0 0xfff06000 0 0x2000>;
90			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
91		};
92
93		apb4: bus@fe000000 {
94			compatible = "simple-bus";
95			reg = <0x0 0xfe000000 0x0 0x480000>;
96			#address-cells = <2>;
97			#size-cells = <2>;
98			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
99
100			periphs_pinctrl: pinctrl@4000 {
101				compatible = "amlogic,meson-s4-periphs-pinctrl";
102				#address-cells = <2>;
103				#size-cells = <2>;
104				ranges;
105
106				gpio: bank@4000 {
107					reg = <0x0 0x4000 0x0 0x004c>,
108					      <0x0 0x40c0 0x0 0x0220>;
109					reg-names = "mux", "gpio";
110					gpio-controller;
111					#gpio-cells = <2>;
112					gpio-ranges = <&periphs_pinctrl 0 0 82>;
113				};
114			};
115
116			gpio_intc: interrupt-controller@4080 {
117				compatible = "amlogic,meson-s4-gpio-intc",
118					     "amlogic,meson-gpio-intc";
119				reg = <0x0 0x4080 0x0 0x20>;
120				interrupt-controller;
121				#interrupt-cells = <2>;
122				amlogic,channel-interrupts =
123					<10 11 12 13 14 15 16 17 18 19 20 21>;
124			};
125
126			uart_b: serial@7a000 {
127				compatible = "amlogic,meson-s4-uart",
128					     "amlogic,meson-ao-uart";
129				reg = <0x0 0x7a000 0x0 0x18>;
130				interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
131				clocks = <&xtal>, <&xtal>, <&xtal>;
132				clock-names = "xtal", "pclk", "baud";
133				status = "disabled";
134			};
135
136			reset: reset-controller@2000 {
137				compatible = "amlogic,meson-s4-reset";
138				reg = <0x0 0x2000 0x0 0x98>;
139				#reset-cells = <1>;
140			};
141		};
142	};
143};
144