1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11	cpus {
12		#address-cells = <2>;
13		#size-cells = <0>;
14
15		cpu0: cpu@0 {
16			device_type = "cpu";
17			compatible = "arm,cortex-a35","arm,armv8";
18			reg = <0x0 0x0>;
19			enable-method = "psci";
20		};
21
22		cpu1: cpu@1 {
23			device_type = "cpu";
24			compatible = "arm,cortex-a35","arm,armv8";
25			reg = <0x0 0x1>;
26			enable-method = "psci";
27		};
28
29		cpu2: cpu@2 {
30			device_type = "cpu";
31			compatible = "arm,cortex-a35","arm,armv8";
32			reg = <0x0 0x2>;
33			enable-method = "psci";
34		};
35
36		cpu3: cpu@3 {
37			device_type = "cpu";
38			compatible = "arm,cortex-a35","arm,armv8";
39			reg = <0x0 0x3>;
40			enable-method = "psci";
41		};
42	};
43
44	timer {
45		compatible = "arm,armv8-timer";
46		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
47			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
48			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
49			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
50	};
51
52	psci {
53		compatible = "arm,psci-1.0";
54		method = "smc";
55	};
56
57	xtal: xtal-clk {
58		compatible = "fixed-clock";
59		clock-frequency = <24000000>;
60		clock-output-names = "xtal";
61		#clock-cells = <0>;
62	};
63
64	soc {
65		compatible = "simple-bus";
66		#address-cells = <2>;
67		#size-cells = <2>;
68		ranges;
69
70		gic: interrupt-controller@fff01000 {
71			compatible = "arm,gic-400";
72			#interrupt-cells = <3>;
73			#address-cells = <0>;
74			interrupt-controller;
75			reg = <0x0 0xfff01000 0 0x1000>,
76			      <0x0 0xfff02000 0 0x2000>,
77			      <0x0 0xfff04000 0 0x2000>,
78			      <0x0 0xfff06000 0 0x2000>;
79			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
80		};
81
82		apb4: apb4@fe000000 {
83			compatible = "simple-bus";
84			reg = <0x0 0xfe000000 0x0 0x480000>;
85			#address-cells = <2>;
86			#size-cells = <2>;
87			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
88
89			periphs_pinctrl: pinctrl@4000 {
90				compatible = "amlogic,meson-s4-periphs-pinctrl";
91				#address-cells = <2>;
92				#size-cells = <2>;
93				ranges;
94
95				gpio: bank@4000 {
96					reg = <0x0 0x4000 0x0 0x004c>,
97					      <0x0 0x40c0 0x0 0x0220>;
98					reg-names = "mux", "gpio";
99					gpio-controller;
100					#gpio-cells = <2>;
101					gpio-ranges = <&periphs_pinctrl 0 0 82>;
102				};
103			};
104
105			gpio_intc: interrupt-controller@4080 {
106				compatible = "amlogic,meson-s4-gpio-intc",
107					     "amlogic,meson-gpio-intc";
108				reg = <0x0 0x4080 0x0 0x20>;
109				interrupt-controller;
110				#interrupt-cells = <2>;
111				amlogic,channel-interrupts =
112					<10 11 12 13 14 15 16 17 18 19 20 21>;
113			};
114
115			uart_B: serial@7a000 {
116				compatible = "amlogic,meson-s4-uart",
117					     "amlogic,meson-ao-uart";
118				reg = <0x0 0x7a000 0x0 0x18>;
119				interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
120				status = "disabled";
121				clocks = <&xtal>, <&xtal>, <&xtal>;
122				clock-names = "xtal", "pclk", "baud";
123			};
124		};
125	};
126};
127