1ac4dfd0dSXianwei Zhao// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2ac4dfd0dSXianwei Zhao/* 3ac4dfd0dSXianwei Zhao * Copyright (c) 2021 Amlogic, Inc. All rights reserved. 4ac4dfd0dSXianwei Zhao */ 5ac4dfd0dSXianwei Zhao 6ac4dfd0dSXianwei Zhao#include <dt-bindings/interrupt-controller/irq.h> 7ac4dfd0dSXianwei Zhao#include <dt-bindings/interrupt-controller/arm-gic.h> 86383f5a2SQianggui Song#include <dt-bindings/gpio/gpio.h> 9ac4dfd0dSXianwei Zhao 10ac4dfd0dSXianwei Zhao/ { 11ac4dfd0dSXianwei Zhao cpus { 12ac4dfd0dSXianwei Zhao #address-cells = <2>; 13ac4dfd0dSXianwei Zhao #size-cells = <0>; 14ac4dfd0dSXianwei Zhao 15ac4dfd0dSXianwei Zhao cpu0: cpu@0 { 16ac4dfd0dSXianwei Zhao device_type = "cpu"; 179af9c58aSXianwei Zhao compatible = "arm,cortex-a35"; 18ac4dfd0dSXianwei Zhao reg = <0x0 0x0>; 19ac4dfd0dSXianwei Zhao enable-method = "psci"; 20ac4dfd0dSXianwei Zhao }; 21ac4dfd0dSXianwei Zhao 22ac4dfd0dSXianwei Zhao cpu1: cpu@1 { 23ac4dfd0dSXianwei Zhao device_type = "cpu"; 249af9c58aSXianwei Zhao compatible = "arm,cortex-a35"; 25ac4dfd0dSXianwei Zhao reg = <0x0 0x1>; 26ac4dfd0dSXianwei Zhao enable-method = "psci"; 27ac4dfd0dSXianwei Zhao }; 28ac4dfd0dSXianwei Zhao 29ac4dfd0dSXianwei Zhao cpu2: cpu@2 { 30ac4dfd0dSXianwei Zhao device_type = "cpu"; 319af9c58aSXianwei Zhao compatible = "arm,cortex-a35"; 32ac4dfd0dSXianwei Zhao reg = <0x0 0x2>; 33ac4dfd0dSXianwei Zhao enable-method = "psci"; 34ac4dfd0dSXianwei Zhao }; 35ac4dfd0dSXianwei Zhao 36ac4dfd0dSXianwei Zhao cpu3: cpu@3 { 37ac4dfd0dSXianwei Zhao device_type = "cpu"; 389af9c58aSXianwei Zhao compatible = "arm,cortex-a35"; 39ac4dfd0dSXianwei Zhao reg = <0x0 0x3>; 40ac4dfd0dSXianwei Zhao enable-method = "psci"; 41ac4dfd0dSXianwei Zhao }; 42ac4dfd0dSXianwei Zhao }; 43ac4dfd0dSXianwei Zhao 44ac4dfd0dSXianwei Zhao timer { 45ac4dfd0dSXianwei Zhao compatible = "arm,armv8-timer"; 46ac4dfd0dSXianwei Zhao interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 47ac4dfd0dSXianwei Zhao <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 48ac4dfd0dSXianwei Zhao <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 49ac4dfd0dSXianwei Zhao <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 50ac4dfd0dSXianwei Zhao }; 51ac4dfd0dSXianwei Zhao 52ac4dfd0dSXianwei Zhao psci { 53ac4dfd0dSXianwei Zhao compatible = "arm,psci-1.0"; 54ac4dfd0dSXianwei Zhao method = "smc"; 55ac4dfd0dSXianwei Zhao }; 56ac4dfd0dSXianwei Zhao 57ac4dfd0dSXianwei Zhao xtal: xtal-clk { 58ac4dfd0dSXianwei Zhao compatible = "fixed-clock"; 59ac4dfd0dSXianwei Zhao clock-frequency = <24000000>; 60ac4dfd0dSXianwei Zhao clock-output-names = "xtal"; 61ac4dfd0dSXianwei Zhao #clock-cells = <0>; 62ac4dfd0dSXianwei Zhao }; 63ac4dfd0dSXianwei Zhao 64bf386f26SXianwei Zhao firmware { 65bf386f26SXianwei Zhao sm: secure-monitor { 66bf386f26SXianwei Zhao compatible = "amlogic,meson-gxbb-sm"; 67bf386f26SXianwei Zhao 68085f7a29SShunzhou Jiang pwrc: power-controller { 69085f7a29SShunzhou Jiang compatible = "amlogic,meson-s4-pwrc"; 70085f7a29SShunzhou Jiang #power-domain-cells = <1>; 71bf386f26SXianwei Zhao }; 72bf386f26SXianwei Zhao }; 73085f7a29SShunzhou Jiang }; 74085f7a29SShunzhou Jiang 75ac4dfd0dSXianwei Zhao soc { 76ac4dfd0dSXianwei Zhao compatible = "simple-bus"; 77ac4dfd0dSXianwei Zhao #address-cells = <2>; 78ac4dfd0dSXianwei Zhao #size-cells = <2>; 79ac4dfd0dSXianwei Zhao ranges; 80ac4dfd0dSXianwei Zhao 81ac4dfd0dSXianwei Zhao gic: interrupt-controller@fff01000 { 82ac4dfd0dSXianwei Zhao compatible = "arm,gic-400"; 83ac4dfd0dSXianwei Zhao #interrupt-cells = <3>; 84ac4dfd0dSXianwei Zhao #address-cells = <0>; 85ac4dfd0dSXianwei Zhao interrupt-controller; 86ac4dfd0dSXianwei Zhao reg = <0x0 0xfff01000 0 0x1000>, 87ac4dfd0dSXianwei Zhao <0x0 0xfff02000 0 0x2000>, 88ac4dfd0dSXianwei Zhao <0x0 0xfff04000 0 0x2000>, 89ac4dfd0dSXianwei Zhao <0x0 0xfff06000 0 0x2000>; 90ac4dfd0dSXianwei Zhao interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 91ac4dfd0dSXianwei Zhao }; 92ac4dfd0dSXianwei Zhao 93d1e336eeSNeil Armstrong apb4: bus@fe000000 { 94ac4dfd0dSXianwei Zhao compatible = "simple-bus"; 95ac4dfd0dSXianwei Zhao reg = <0x0 0xfe000000 0x0 0x480000>; 96ac4dfd0dSXianwei Zhao #address-cells = <2>; 97ac4dfd0dSXianwei Zhao #size-cells = <2>; 98ac4dfd0dSXianwei Zhao ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; 99ac4dfd0dSXianwei Zhao 1006383f5a2SQianggui Song periphs_pinctrl: pinctrl@4000 { 1016383f5a2SQianggui Song compatible = "amlogic,meson-s4-periphs-pinctrl"; 1026383f5a2SQianggui Song #address-cells = <2>; 1036383f5a2SQianggui Song #size-cells = <2>; 1046383f5a2SQianggui Song ranges; 1056383f5a2SQianggui Song 1066383f5a2SQianggui Song gpio: bank@4000 { 1076383f5a2SQianggui Song reg = <0x0 0x4000 0x0 0x004c>, 1086383f5a2SQianggui Song <0x0 0x40c0 0x0 0x0220>; 1096383f5a2SQianggui Song reg-names = "mux", "gpio"; 1106383f5a2SQianggui Song gpio-controller; 1116383f5a2SQianggui Song #gpio-cells = <2>; 1126383f5a2SQianggui Song gpio-ranges = <&periphs_pinctrl 0 0 82>; 1136383f5a2SQianggui Song }; 1146383f5a2SQianggui Song }; 1156383f5a2SQianggui Song 11639363393SQianggui Song gpio_intc: interrupt-controller@4080 { 11739363393SQianggui Song compatible = "amlogic,meson-s4-gpio-intc", 11839363393SQianggui Song "amlogic,meson-gpio-intc"; 11939363393SQianggui Song reg = <0x0 0x4080 0x0 0x20>; 12039363393SQianggui Song interrupt-controller; 12139363393SQianggui Song #interrupt-cells = <2>; 12239363393SQianggui Song amlogic,channel-interrupts = 12339363393SQianggui Song <10 11 12 13 14 15 16 17 18 19 20 21>; 12439363393SQianggui Song }; 12539363393SQianggui Song 1260112d7f6SXianwei Zhao uart_b: serial@7a000 { 127ac4dfd0dSXianwei Zhao compatible = "amlogic,meson-s4-uart", 128ac4dfd0dSXianwei Zhao "amlogic,meson-ao-uart"; 129ac4dfd0dSXianwei Zhao reg = <0x0 0x7a000 0x0 0x18>; 130ac4dfd0dSXianwei Zhao interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; 131ac4dfd0dSXianwei Zhao clocks = <&xtal>, <&xtal>, <&xtal>; 132ac4dfd0dSXianwei Zhao clock-names = "xtal", "pclk", "baud"; 1330112d7f6SXianwei Zhao status = "disabled"; 134ac4dfd0dSXianwei Zhao }; 135c46952d2SZelong Dong 136c46952d2SZelong Dong reset: reset-controller@2000 { 137c46952d2SZelong Dong compatible = "amlogic,meson-s4-reset"; 138c46952d2SZelong Dong reg = <0x0 0x2000 0x0 0x98>; 139c46952d2SZelong Dong #reset-cells = <1>; 140c46952d2SZelong Dong }; 141ac4dfd0dSXianwei Zhao }; 142ac4dfd0dSXianwei Zhao }; 143ac4dfd0dSXianwei Zhao}; 144