1*ac4dfd0dSXianwei Zhao// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*ac4dfd0dSXianwei Zhao/* 3*ac4dfd0dSXianwei Zhao * Copyright (c) 2021 Amlogic, Inc. All rights reserved. 4*ac4dfd0dSXianwei Zhao */ 5*ac4dfd0dSXianwei Zhao 6*ac4dfd0dSXianwei Zhao#include <dt-bindings/interrupt-controller/irq.h> 7*ac4dfd0dSXianwei Zhao#include <dt-bindings/interrupt-controller/arm-gic.h> 8*ac4dfd0dSXianwei Zhao 9*ac4dfd0dSXianwei Zhao/ { 10*ac4dfd0dSXianwei Zhao cpus { 11*ac4dfd0dSXianwei Zhao #address-cells = <2>; 12*ac4dfd0dSXianwei Zhao #size-cells = <0>; 13*ac4dfd0dSXianwei Zhao 14*ac4dfd0dSXianwei Zhao cpu0: cpu@0 { 15*ac4dfd0dSXianwei Zhao device_type = "cpu"; 16*ac4dfd0dSXianwei Zhao compatible = "arm,cortex-a35","arm,armv8"; 17*ac4dfd0dSXianwei Zhao reg = <0x0 0x0>; 18*ac4dfd0dSXianwei Zhao enable-method = "psci"; 19*ac4dfd0dSXianwei Zhao }; 20*ac4dfd0dSXianwei Zhao 21*ac4dfd0dSXianwei Zhao cpu1: cpu@1 { 22*ac4dfd0dSXianwei Zhao device_type = "cpu"; 23*ac4dfd0dSXianwei Zhao compatible = "arm,cortex-a35","arm,armv8"; 24*ac4dfd0dSXianwei Zhao reg = <0x0 0x1>; 25*ac4dfd0dSXianwei Zhao enable-method = "psci"; 26*ac4dfd0dSXianwei Zhao }; 27*ac4dfd0dSXianwei Zhao 28*ac4dfd0dSXianwei Zhao cpu2: cpu@2 { 29*ac4dfd0dSXianwei Zhao device_type = "cpu"; 30*ac4dfd0dSXianwei Zhao compatible = "arm,cortex-a35","arm,armv8"; 31*ac4dfd0dSXianwei Zhao reg = <0x0 0x2>; 32*ac4dfd0dSXianwei Zhao enable-method = "psci"; 33*ac4dfd0dSXianwei Zhao }; 34*ac4dfd0dSXianwei Zhao 35*ac4dfd0dSXianwei Zhao cpu3: cpu@3 { 36*ac4dfd0dSXianwei Zhao device_type = "cpu"; 37*ac4dfd0dSXianwei Zhao compatible = "arm,cortex-a35","arm,armv8"; 38*ac4dfd0dSXianwei Zhao reg = <0x0 0x3>; 39*ac4dfd0dSXianwei Zhao enable-method = "psci"; 40*ac4dfd0dSXianwei Zhao }; 41*ac4dfd0dSXianwei Zhao }; 42*ac4dfd0dSXianwei Zhao 43*ac4dfd0dSXianwei Zhao timer { 44*ac4dfd0dSXianwei Zhao compatible = "arm,armv8-timer"; 45*ac4dfd0dSXianwei Zhao interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 46*ac4dfd0dSXianwei Zhao <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 47*ac4dfd0dSXianwei Zhao <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 48*ac4dfd0dSXianwei Zhao <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 49*ac4dfd0dSXianwei Zhao }; 50*ac4dfd0dSXianwei Zhao 51*ac4dfd0dSXianwei Zhao psci { 52*ac4dfd0dSXianwei Zhao compatible = "arm,psci-1.0"; 53*ac4dfd0dSXianwei Zhao method = "smc"; 54*ac4dfd0dSXianwei Zhao }; 55*ac4dfd0dSXianwei Zhao 56*ac4dfd0dSXianwei Zhao xtal: xtal-clk { 57*ac4dfd0dSXianwei Zhao compatible = "fixed-clock"; 58*ac4dfd0dSXianwei Zhao clock-frequency = <24000000>; 59*ac4dfd0dSXianwei Zhao clock-output-names = "xtal"; 60*ac4dfd0dSXianwei Zhao #clock-cells = <0>; 61*ac4dfd0dSXianwei Zhao }; 62*ac4dfd0dSXianwei Zhao 63*ac4dfd0dSXianwei Zhao soc { 64*ac4dfd0dSXianwei Zhao compatible = "simple-bus"; 65*ac4dfd0dSXianwei Zhao #address-cells = <2>; 66*ac4dfd0dSXianwei Zhao #size-cells = <2>; 67*ac4dfd0dSXianwei Zhao ranges; 68*ac4dfd0dSXianwei Zhao 69*ac4dfd0dSXianwei Zhao gic: interrupt-controller@fff01000 { 70*ac4dfd0dSXianwei Zhao compatible = "arm,gic-400"; 71*ac4dfd0dSXianwei Zhao #interrupt-cells = <3>; 72*ac4dfd0dSXianwei Zhao #address-cells = <0>; 73*ac4dfd0dSXianwei Zhao interrupt-controller; 74*ac4dfd0dSXianwei Zhao reg = <0x0 0xfff01000 0 0x1000>, 75*ac4dfd0dSXianwei Zhao <0x0 0xfff02000 0 0x2000>, 76*ac4dfd0dSXianwei Zhao <0x0 0xfff04000 0 0x2000>, 77*ac4dfd0dSXianwei Zhao <0x0 0xfff06000 0 0x2000>; 78*ac4dfd0dSXianwei Zhao interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 79*ac4dfd0dSXianwei Zhao }; 80*ac4dfd0dSXianwei Zhao 81*ac4dfd0dSXianwei Zhao apb4: apb4@fe000000 { 82*ac4dfd0dSXianwei Zhao compatible = "simple-bus"; 83*ac4dfd0dSXianwei Zhao reg = <0x0 0xfe000000 0x0 0x480000>; 84*ac4dfd0dSXianwei Zhao #address-cells = <2>; 85*ac4dfd0dSXianwei Zhao #size-cells = <2>; 86*ac4dfd0dSXianwei Zhao ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; 87*ac4dfd0dSXianwei Zhao 88*ac4dfd0dSXianwei Zhao uart_B: serial@7a000 { 89*ac4dfd0dSXianwei Zhao compatible = "amlogic,meson-s4-uart", 90*ac4dfd0dSXianwei Zhao "amlogic,meson-ao-uart"; 91*ac4dfd0dSXianwei Zhao reg = <0x0 0x7a000 0x0 0x18>; 92*ac4dfd0dSXianwei Zhao interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; 93*ac4dfd0dSXianwei Zhao status = "disabled"; 94*ac4dfd0dSXianwei Zhao clocks = <&xtal>, <&xtal>, <&xtal>; 95*ac4dfd0dSXianwei Zhao clock-names = "xtal", "pclk", "baud"; 96*ac4dfd0dSXianwei Zhao }; 97*ac4dfd0dSXianwei Zhao }; 98*ac4dfd0dSXianwei Zhao }; 99*ac4dfd0dSXianwei Zhao}; 100