1ac4dfd0dSXianwei Zhao// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2ac4dfd0dSXianwei Zhao/* 3ac4dfd0dSXianwei Zhao * Copyright (c) 2021 Amlogic, Inc. All rights reserved. 4ac4dfd0dSXianwei Zhao */ 5ac4dfd0dSXianwei Zhao 6ac4dfd0dSXianwei Zhao#include <dt-bindings/interrupt-controller/irq.h> 7ac4dfd0dSXianwei Zhao#include <dt-bindings/interrupt-controller/arm-gic.h> 8ac4dfd0dSXianwei Zhao 9ac4dfd0dSXianwei Zhao/ { 10ac4dfd0dSXianwei Zhao cpus { 11ac4dfd0dSXianwei Zhao #address-cells = <2>; 12ac4dfd0dSXianwei Zhao #size-cells = <0>; 13ac4dfd0dSXianwei Zhao 14ac4dfd0dSXianwei Zhao cpu0: cpu@0 { 15ac4dfd0dSXianwei Zhao device_type = "cpu"; 16*9af9c58aSXianwei Zhao compatible = "arm,cortex-a35"; 17ac4dfd0dSXianwei Zhao reg = <0x0 0x0>; 18ac4dfd0dSXianwei Zhao enable-method = "psci"; 19ac4dfd0dSXianwei Zhao }; 20ac4dfd0dSXianwei Zhao 21ac4dfd0dSXianwei Zhao cpu1: cpu@1 { 22ac4dfd0dSXianwei Zhao device_type = "cpu"; 23*9af9c58aSXianwei Zhao compatible = "arm,cortex-a35"; 24ac4dfd0dSXianwei Zhao reg = <0x0 0x1>; 25ac4dfd0dSXianwei Zhao enable-method = "psci"; 26ac4dfd0dSXianwei Zhao }; 27ac4dfd0dSXianwei Zhao 28ac4dfd0dSXianwei Zhao cpu2: cpu@2 { 29ac4dfd0dSXianwei Zhao device_type = "cpu"; 30*9af9c58aSXianwei Zhao compatible = "arm,cortex-a35"; 31ac4dfd0dSXianwei Zhao reg = <0x0 0x2>; 32ac4dfd0dSXianwei Zhao enable-method = "psci"; 33ac4dfd0dSXianwei Zhao }; 34ac4dfd0dSXianwei Zhao 35ac4dfd0dSXianwei Zhao cpu3: cpu@3 { 36ac4dfd0dSXianwei Zhao device_type = "cpu"; 37*9af9c58aSXianwei Zhao compatible = "arm,cortex-a35"; 38ac4dfd0dSXianwei Zhao reg = <0x0 0x3>; 39ac4dfd0dSXianwei Zhao enable-method = "psci"; 40ac4dfd0dSXianwei Zhao }; 41ac4dfd0dSXianwei Zhao }; 42ac4dfd0dSXianwei Zhao 43ac4dfd0dSXianwei Zhao timer { 44ac4dfd0dSXianwei Zhao compatible = "arm,armv8-timer"; 45ac4dfd0dSXianwei Zhao interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 46ac4dfd0dSXianwei Zhao <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 47ac4dfd0dSXianwei Zhao <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 48ac4dfd0dSXianwei Zhao <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 49ac4dfd0dSXianwei Zhao }; 50ac4dfd0dSXianwei Zhao 51ac4dfd0dSXianwei Zhao psci { 52ac4dfd0dSXianwei Zhao compatible = "arm,psci-1.0"; 53ac4dfd0dSXianwei Zhao method = "smc"; 54ac4dfd0dSXianwei Zhao }; 55ac4dfd0dSXianwei Zhao 56ac4dfd0dSXianwei Zhao xtal: xtal-clk { 57ac4dfd0dSXianwei Zhao compatible = "fixed-clock"; 58ac4dfd0dSXianwei Zhao clock-frequency = <24000000>; 59ac4dfd0dSXianwei Zhao clock-output-names = "xtal"; 60ac4dfd0dSXianwei Zhao #clock-cells = <0>; 61ac4dfd0dSXianwei Zhao }; 62ac4dfd0dSXianwei Zhao 63ac4dfd0dSXianwei Zhao soc { 64ac4dfd0dSXianwei Zhao compatible = "simple-bus"; 65ac4dfd0dSXianwei Zhao #address-cells = <2>; 66ac4dfd0dSXianwei Zhao #size-cells = <2>; 67ac4dfd0dSXianwei Zhao ranges; 68ac4dfd0dSXianwei Zhao 69ac4dfd0dSXianwei Zhao gic: interrupt-controller@fff01000 { 70ac4dfd0dSXianwei Zhao compatible = "arm,gic-400"; 71ac4dfd0dSXianwei Zhao #interrupt-cells = <3>; 72ac4dfd0dSXianwei Zhao #address-cells = <0>; 73ac4dfd0dSXianwei Zhao interrupt-controller; 74ac4dfd0dSXianwei Zhao reg = <0x0 0xfff01000 0 0x1000>, 75ac4dfd0dSXianwei Zhao <0x0 0xfff02000 0 0x2000>, 76ac4dfd0dSXianwei Zhao <0x0 0xfff04000 0 0x2000>, 77ac4dfd0dSXianwei Zhao <0x0 0xfff06000 0 0x2000>; 78ac4dfd0dSXianwei Zhao interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 79ac4dfd0dSXianwei Zhao }; 80ac4dfd0dSXianwei Zhao 81ac4dfd0dSXianwei Zhao apb4: apb4@fe000000 { 82ac4dfd0dSXianwei Zhao compatible = "simple-bus"; 83ac4dfd0dSXianwei Zhao reg = <0x0 0xfe000000 0x0 0x480000>; 84ac4dfd0dSXianwei Zhao #address-cells = <2>; 85ac4dfd0dSXianwei Zhao #size-cells = <2>; 86ac4dfd0dSXianwei Zhao ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; 87ac4dfd0dSXianwei Zhao 88ac4dfd0dSXianwei Zhao uart_B: serial@7a000 { 89ac4dfd0dSXianwei Zhao compatible = "amlogic,meson-s4-uart", 90ac4dfd0dSXianwei Zhao "amlogic,meson-ao-uart"; 91ac4dfd0dSXianwei Zhao reg = <0x0 0x7a000 0x0 0x18>; 92ac4dfd0dSXianwei Zhao interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; 93ac4dfd0dSXianwei Zhao status = "disabled"; 94ac4dfd0dSXianwei Zhao clocks = <&xtal>, <&xtal>, <&xtal>; 95ac4dfd0dSXianwei Zhao clock-names = "xtal", "pclk", "baud"; 96ac4dfd0dSXianwei Zhao }; 97ac4dfd0dSXianwei Zhao }; 98ac4dfd0dSXianwei Zhao }; 99ac4dfd0dSXianwei Zhao}; 100