1ac4dfd0dSXianwei Zhao// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2ac4dfd0dSXianwei Zhao/* 3ac4dfd0dSXianwei Zhao * Copyright (c) 2021 Amlogic, Inc. All rights reserved. 4ac4dfd0dSXianwei Zhao */ 5ac4dfd0dSXianwei Zhao 6ac4dfd0dSXianwei Zhao#include <dt-bindings/interrupt-controller/irq.h> 7ac4dfd0dSXianwei Zhao#include <dt-bindings/interrupt-controller/arm-gic.h> 8*6383f5a2SQianggui Song#include <dt-bindings/gpio/gpio.h> 9ac4dfd0dSXianwei Zhao 10ac4dfd0dSXianwei Zhao/ { 11ac4dfd0dSXianwei Zhao cpus { 12ac4dfd0dSXianwei Zhao #address-cells = <2>; 13ac4dfd0dSXianwei Zhao #size-cells = <0>; 14ac4dfd0dSXianwei Zhao 15ac4dfd0dSXianwei Zhao cpu0: cpu@0 { 16ac4dfd0dSXianwei Zhao device_type = "cpu"; 17ac4dfd0dSXianwei Zhao compatible = "arm,cortex-a35","arm,armv8"; 18ac4dfd0dSXianwei Zhao reg = <0x0 0x0>; 19ac4dfd0dSXianwei Zhao enable-method = "psci"; 20ac4dfd0dSXianwei Zhao }; 21ac4dfd0dSXianwei Zhao 22ac4dfd0dSXianwei Zhao cpu1: cpu@1 { 23ac4dfd0dSXianwei Zhao device_type = "cpu"; 24ac4dfd0dSXianwei Zhao compatible = "arm,cortex-a35","arm,armv8"; 25ac4dfd0dSXianwei Zhao reg = <0x0 0x1>; 26ac4dfd0dSXianwei Zhao enable-method = "psci"; 27ac4dfd0dSXianwei Zhao }; 28ac4dfd0dSXianwei Zhao 29ac4dfd0dSXianwei Zhao cpu2: cpu@2 { 30ac4dfd0dSXianwei Zhao device_type = "cpu"; 31ac4dfd0dSXianwei Zhao compatible = "arm,cortex-a35","arm,armv8"; 32ac4dfd0dSXianwei Zhao reg = <0x0 0x2>; 33ac4dfd0dSXianwei Zhao enable-method = "psci"; 34ac4dfd0dSXianwei Zhao }; 35ac4dfd0dSXianwei Zhao 36ac4dfd0dSXianwei Zhao cpu3: cpu@3 { 37ac4dfd0dSXianwei Zhao device_type = "cpu"; 38ac4dfd0dSXianwei Zhao compatible = "arm,cortex-a35","arm,armv8"; 39ac4dfd0dSXianwei Zhao reg = <0x0 0x3>; 40ac4dfd0dSXianwei Zhao enable-method = "psci"; 41ac4dfd0dSXianwei Zhao }; 42ac4dfd0dSXianwei Zhao }; 43ac4dfd0dSXianwei Zhao 44ac4dfd0dSXianwei Zhao timer { 45ac4dfd0dSXianwei Zhao compatible = "arm,armv8-timer"; 46ac4dfd0dSXianwei Zhao interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 47ac4dfd0dSXianwei Zhao <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 48ac4dfd0dSXianwei Zhao <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 49ac4dfd0dSXianwei Zhao <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 50ac4dfd0dSXianwei Zhao }; 51ac4dfd0dSXianwei Zhao 52ac4dfd0dSXianwei Zhao psci { 53ac4dfd0dSXianwei Zhao compatible = "arm,psci-1.0"; 54ac4dfd0dSXianwei Zhao method = "smc"; 55ac4dfd0dSXianwei Zhao }; 56ac4dfd0dSXianwei Zhao 57ac4dfd0dSXianwei Zhao xtal: xtal-clk { 58ac4dfd0dSXianwei Zhao compatible = "fixed-clock"; 59ac4dfd0dSXianwei Zhao clock-frequency = <24000000>; 60ac4dfd0dSXianwei Zhao clock-output-names = "xtal"; 61ac4dfd0dSXianwei Zhao #clock-cells = <0>; 62ac4dfd0dSXianwei Zhao }; 63ac4dfd0dSXianwei Zhao 64ac4dfd0dSXianwei Zhao soc { 65ac4dfd0dSXianwei Zhao compatible = "simple-bus"; 66ac4dfd0dSXianwei Zhao #address-cells = <2>; 67ac4dfd0dSXianwei Zhao #size-cells = <2>; 68ac4dfd0dSXianwei Zhao ranges; 69ac4dfd0dSXianwei Zhao 70ac4dfd0dSXianwei Zhao gic: interrupt-controller@fff01000 { 71ac4dfd0dSXianwei Zhao compatible = "arm,gic-400"; 72ac4dfd0dSXianwei Zhao #interrupt-cells = <3>; 73ac4dfd0dSXianwei Zhao #address-cells = <0>; 74ac4dfd0dSXianwei Zhao interrupt-controller; 75ac4dfd0dSXianwei Zhao reg = <0x0 0xfff01000 0 0x1000>, 76ac4dfd0dSXianwei Zhao <0x0 0xfff02000 0 0x2000>, 77ac4dfd0dSXianwei Zhao <0x0 0xfff04000 0 0x2000>, 78ac4dfd0dSXianwei Zhao <0x0 0xfff06000 0 0x2000>; 79ac4dfd0dSXianwei Zhao interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 80ac4dfd0dSXianwei Zhao }; 81ac4dfd0dSXianwei Zhao 82ac4dfd0dSXianwei Zhao apb4: apb4@fe000000 { 83ac4dfd0dSXianwei Zhao compatible = "simple-bus"; 84ac4dfd0dSXianwei Zhao reg = <0x0 0xfe000000 0x0 0x480000>; 85ac4dfd0dSXianwei Zhao #address-cells = <2>; 86ac4dfd0dSXianwei Zhao #size-cells = <2>; 87ac4dfd0dSXianwei Zhao ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; 88ac4dfd0dSXianwei Zhao 89*6383f5a2SQianggui Song periphs_pinctrl: pinctrl@4000 { 90*6383f5a2SQianggui Song compatible = "amlogic,meson-s4-periphs-pinctrl"; 91*6383f5a2SQianggui Song #address-cells = <2>; 92*6383f5a2SQianggui Song #size-cells = <2>; 93*6383f5a2SQianggui Song ranges; 94*6383f5a2SQianggui Song 95*6383f5a2SQianggui Song gpio: bank@4000 { 96*6383f5a2SQianggui Song reg = <0x0 0x4000 0x0 0x004c>, 97*6383f5a2SQianggui Song <0x0 0x40c0 0x0 0x0220>; 98*6383f5a2SQianggui Song reg-names = "mux", "gpio"; 99*6383f5a2SQianggui Song gpio-controller; 100*6383f5a2SQianggui Song #gpio-cells = <2>; 101*6383f5a2SQianggui Song gpio-ranges = <&periphs_pinctrl 0 0 82>; 102*6383f5a2SQianggui Song }; 103*6383f5a2SQianggui Song }; 104*6383f5a2SQianggui Song 105ac4dfd0dSXianwei Zhao uart_B: serial@7a000 { 106ac4dfd0dSXianwei Zhao compatible = "amlogic,meson-s4-uart", 107ac4dfd0dSXianwei Zhao "amlogic,meson-ao-uart"; 108ac4dfd0dSXianwei Zhao reg = <0x0 0x7a000 0x0 0x18>; 109ac4dfd0dSXianwei Zhao interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; 110ac4dfd0dSXianwei Zhao status = "disabled"; 111ac4dfd0dSXianwei Zhao clocks = <&xtal>, <&xtal>, <&xtal>; 112ac4dfd0dSXianwei Zhao clock-names = "xtal", "pclk", "baud"; 113ac4dfd0dSXianwei Zhao }; 114ac4dfd0dSXianwei Zhao }; 115ac4dfd0dSXianwei Zhao }; 116ac4dfd0dSXianwei Zhao}; 117